Transmit/Receive (T/R) Switch Topology Comparison

PilJae Park 2/23/2007 Slide 1

Transmit/Receive (T/R) Switch Topology ComparisonSeries-series Topology Series-shunt Topology

High impedanceblock

Rx

M1

M2

Tx

AntVC

VC VC

Rx

M3

M4

Tx

Ant

VC

In Tx mode High power handling capability is requiredLeakage to Rx path is bottleneck of power handling

High impedance block in the Rx path is required in series-shunt topology


Proposed T/R SwitchSeries topology for Tx path, series/shunt LC tank for Rx path

For Tx mode, VC is high and L1, C1 forms parallel LC resonance tank

For Rx mode, VC is low and L1, C2 forms series LC resonance tank

Tx path has small area and high Power handling capabilityLow IL input matching network can be absorbed into T/R switch

In Triple Well

M1

ON

Rx

Tx

VC

L1

C1

Ant

Tx mode equivalent circuit

M1

M2

M3

VC

Rx

Tx

L1

C1

C2Ant

VC

VC

Rx

L1Ant

C2

M1 Tx

VC

OFF

Rx mode equivalent circuit

Csd


Triple well MOS switch Inductive body biasMOS switch [2]

M1

Rs

VsRL

VG

L C

M2

Rs

Vs

VG

RL

Proposed Floating Triple Well Tx Switch Advantages

M3

Rs

VsRL

VG

Twin well MOS switch

Floating Triple well provides isolation to substrate Prevent power loss through the substrateSmaller area, wider bandwidth compared to the LC-tuned body bias

technique


Floating Triple well MOS Tx Switch Body Impedance

-5 -2.5 0 2.5 5

2.5

3.0

3.5

Vbody

[ohm]

Zbo

dy [

Ko

hm

]

M1

Rs

VsRL

Zbody

Vbody

Floating wells has better substrate isolation than LC tankEffective substrate impedance of high-Q LC tank is still less than 2 kSmaller area and wider bandwidth

GS

n+ n+

Psub

DnwellPwell

DRg


gs

sm

gssLNAin C

Lg

sCsLsZ

1)(,

gs

smSW

gssin C

LgsX

sCsLsZ

1)(

Zin,LNA

Cgs

Ls

gmVgs

+

-Vgs

Xsw

Zin

LNAT/R switch

Low IL Matching between T/R Switch and LNARx path of switch incorporates the LNA input matching network to

achieve lower IL and noise figureRx path IL of conventional T/R switch = IL of switch + IL of matching network

Rx

L1Ant

C2

M1

Tx

Vc2

OFF

SWsX


T/R Switch DesignTx switch design for low IL and high isolationRx path design consideration with inductor Q Simulation results of Tx and Rx path

M1

M2

M3

VC1

Rx

Tx

L1

C1

C2Ant

VC1

VC1

Tx path of T/R siwth

M1

M2

M3

VC1

Rx

Tx

L1

C1

C2Ant

VC1

VC1

Rx path of T/R siwth


Tx Switch Equivalent Circuit ModelTriple well NMOS equivalent circuit model

Triple well NMOS cross-section view

Rch

Rsub

Cgs

Rg

D1 D1'

D2

D3

Cgd

Rs

VsRL

Ron

RLZj Zj

Rs

Vs

RchRs

2Rsub

D1 D1'

D2'

D3'

RLVs

D2'

D3'

2Rsub

C’sd=Cgs//Cgd

Rch

RLZj Zj

Rs

Vs

C’sd

RLZj Zj

Rs

Vs

C’sd

GS

n+ n+

Psub

DnwellPwell

Pwell Dnwell

DRg

Psub

Rch


Insertion loss of Tx Switch IL of on Tx switch is a function of Ron and Zj

jLon

jL

ins

in

ZRR

ZR

ZR

ZIL

//

//2log20

Ron

RLZj Zj

Zin

Rs

Vs

01

23

4

0

5

10

15

200

1

2

3

Zj [Kohm]

Ron

[ohm]

IL [

dB

]

Zj [Kohm]

Ro

n [

oh

m]

0.5 1 1.5 2 2.5 3 3.5 41

3

5

7.5

10

12.5

15

17.5

20

1.0 dB

1.5 dB

2.0 dB

0.5 dB


Isolation Plot of Tx Switch

jLsd

jL

ins

in

ZRSC

ZR

ZR

ZIsolation

///1

//2log20

'

01

23

4 050

100150

200

10

20

30

40

C'sd

[fF]Zj [Kohm]

Iso

lati

on

[d

B]

RLZj Zj

Rs

Vs

C’sd

Zj [Kohm]

C' sd

[fF

]

0.5 1 1.5 2 2.5 3 3.5 4

50

100

150

20015 dB

20 dB

25 dB

30 dB35 dB

Isolation of off Tx switch is a function of C’sd and Zj


Width [m]0 50 100 150 200

C' sd

[fF

]

0

50

100

150

200

250

300

Ron

[oh

m]

0

10

20

30

40

Vgs 0 V Vgs 0.1 V Vgs 0.2 V Vgs 2.0 V Vgs 1.6V Vgs1.2V

Tx Switch Transistor Sizing TradeoffTradeoff between IL and isolation

width ↑ , IL ↓ and width ↓ , isolation ↑

Green dotted line indicates transistor width meeting isolation Blue line points out transistor width satisfying IL specification

Vgs 0 V Vgs 0.1 V Vgs 0.2 V Vgs 2.0 V Vgs 1.6V Vgs1.2V

IL < 1 dBIsolation > 15 dB


Insertion Loss of Rx Path in the T/R Switch

5 7.5 10 12.5 15 17.5 200.2

0.4

0.6

0.8

1

1.2

Q of inductor L1

Rx

IL [

dB]

Rx

L1Ant

C2

M1

Tx

Vc2

OFF

L1 : 5nH, C1 : 950fF

M1: 100u/120n

High Q inductor is desirable for lower receive ILIL is about 0.5 dB when Q is 10


Isolation of between Tx Signal to Tx Path in the T/R Switch

5 7.5 10 12.5 15 17.5 2010

15

20

25

Q of inductor L1

Isol

atio

n [d

B]

M1

ON

Rx

Tx

VC

L1

C1

Ant

L1 : 5nH, C1 : 950fF

M1: 100u/120n

High Q inductor is desirable for high isolationIsolation is about 17 dB when Q is equal to 10


Tx Path P1dB Simulation Results of T/R SwitchAll switches are on in Tx modePin at Tx port Pout at Ant port for Tx mode P1dB simulation

31 dBm of P1dB is achieved

0 5 10 15 20 25 30 35

0

5

10

15

20

25

30

35

Pin [dBm]

Pou

t [d

Bm

]M1

Mi

100u/0.12u

M3

VC

Rx

Pin

5 nH

950 fF

AntM2 750 fF

VC

VC

Rs

Vtx

RL

VC High

Pout


1.4 1.9 2.4 2.9 3.4

-50

-40

-30

-20

-10

0

Frequency [GHz]

S11

, S

22 [

dB]

S11S22

Rx Matching Simulation Results of T/R Switch

M1

Mi

100u/0.12u

M3

VC

RL

Tx

5 nH

950 fF

Ant M2 750 fF

VCRs

Vs

VC Low

RL

Rx

Port1

Port2

Matching between Ant and Rx is >20 dB at 2.3 GHz


Insertion Loss of T/R switchTx IL = 0.9 dB at 2.3 GHz Rx IL = 1.3 dB at 2.3 GHz

1.4 1.9 2.4 2.9 3.4

1

2

3

4

5

6

Frequency [GHz]

IL [

dB

]

Rx LossTx Loss


Isolation Simulation ResultsTx port to Rx port isolation >23 dB at 2.3 GHz

1.4 1.9 2.4 2.9 3.415

20

25

30

35

Frequency [GHz]

Isol

atio

n [d

B]

Isolation Tx modeIsolation Rx mode

M1

Mi

100u/0.12u

M3

VC

L1: 5 nH

C1: 950 fF

M2 C2: 750 fF

VC

VC

Rx

Tx

Ant


T/R Switch Layout8-metal, 1-poly UMC 130-nm technologyArea of 500 μm x 500 μm including test pads

core 230 μm x180 μm

Tx

Rx

ANTTx

ANTRx

L1

C1 C2M1 M2

M3

500 μm

500 μm

M1

Mi

100u/0.12u

M3

VC

L1: 5 nH

C1: 950 fF

M2 C2: 750 fF

VC

VC

Rx

Tx

Ant


Performance Summary Our design achieves the highest P1dB with comparable IL and isolation

Performance Frequency

P1dB IL RTx

Isolation

Topology & Design Feature

Tech-nology

Ref.

2.4 GHz 28 dBm 1.52 dB (Tx) 1.42 dB (Rx)

30 dB (Tx) 15 dB (Rx)

Series - shunt LC tank at body

0.18um CMOS

[2]

2.4 GHz 21.3 dBm

0.7 dB (Tx) 35 dB

5.8 GHz 20 dBm 1.1 dB (Tx) 27 dB

Series - series

(dual mode)

0.18um Triple-well CMOS

[4]

900 MHz 24.3 dBm

0.97 dB (Tx) 35.4 dB

2.4 GHz 20.6 dBm

1.1 dB (Tx) 20.6 dB

Series - Series 0.35um NMOS

0.18um CMOS

[5]

15 GHz 21.5 dBm

1.8 dB (Tx) 17.8 dB Series - Series 0.13um CMOS

[6]

2.3 GHz 31 dBm 0.9 dB (Tx) 1.4 dB (Rx)

23 dB (Tx) 24 dB (Rx)

Series - shunt (simulation

result)

0.13um CMOS

This work


References[1] “A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm

CMOS”, Palaskas, Y et al, Solid-State Circuits, 2006 IEEE International Conference, Feb. 6-9, 2006 Page(s):1420 - 1429

[2] “Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications”, Talwalkar, N.A. et al, EEE Journal of Solid-state circuit, Volume 39, Issue 6, June 2004.

[3] “21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)”, Ohnakado, T. et al, Solid-State Circuits, IEEE Journal of Volume 39, Issue 4, April 2004 Page(s):577 – 584

[4] Mei-Chao Yeh; Zuo-Min Tsai; Ren-Chieh Liu; Lin, K.-Y.; Ying-Tang Chang; Huei Wang; “Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance” Microwave Theory and Techniques, IEEE Transactions onVolume 54, Issue 1, Jan. 2006 Page(s):31 - 39

[5] Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p- silicon substrates, Heng-Jung Huang; O, K.K.; Solid-State Circuits, IEEE Journal of ,Volume 39, Issue 1, Jan. 2004 Page(s):35 – 41

[6] 15-GHz fully integrated nMOS switches in a 0.13um CMOS process, Zhenbiao Li; O, K.K.; Solid-State Circuits, IEEE Journal of Volume 40, Issue 11, Nov. 2005 Page(s):2323 - 2328

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Transmit/Receive (T/R) Switch Topology Comparison