Toward nanoelectronic cellular neural networks

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. 2000; 28:523–535

Toward nanoelectronic cellular neural networks

C. Gerousis1, S. M. Goodnick1;∗;† and W. Porod21Department of Electrical Engineering; Arizona State University; PO Box 875706; Tempe; Arizona 85287-5706;

U.S.A.2Department of Electrical Engineering; University of Notre Dame; Notre Dame; Indiana 46556; U.S.A.

SUMMARY

We investigate the use of nanoelectronic structures in cellular non-linear network (CNN) architectures,for potential application in future high-density and low-power CMOS-nanodevice hybrid circuits. We�rst investigate compact models for simulation of single-electron tunnelling (SET) transistors appropriatefor use in coupled SET–CMOS circuits. We then discuss simple CNN linear architectures using a SETinverter topology as the basis for the non-linear transfer characteristic of individual cells. This basicSET CNN cell acts as a summing node, which is capacitively coupled to the inputs and outputs ofnearest neighbour cells. Monte Carlo simulation results are then used to show CNN-like behaviour inattempting to realize di�erent functionality such as a connected component detector and shadowing.Copyright ? 2000 John Wiley & Sons, Ltd.

KEY WORDS: single-electron devices; cellular non-linear networks; nanoelectronics

1. INTRODUCTION

Nanoelectronics o�ers the promise of ultra-low power and ultra-high integration density. Sev-eral device structures have been proposed and realized experimentally, yet the main challengeremains the organization of these devices in new circuit architectures. For an introduction intothis problem area, the interested reader is referred to recent reviews in this �eld [1,2].Single-electron tunnelling (SET) transistors [3] have attractive properties which make them

excellent candidates for implementing ultra-dense and complex signal and image processingsystems. SET devices satisfy hardware requirements for large-scale neural networks such aslocal interconnectivity, small device size and low-power consumption. Current fabricationtechnology allows the integration of 1011 SET transistors per cm2 and a power consumptionof 10−9 W per transistor [4]. Ultimately, the goal is to build SET transistors capable ofoperation at room temperature, and compatible with conventional CMOS process technology.The potential for very dense arrays of SET transistors makes them attractive for the realization

∗ Correspondence to: S. M. Goodnick, Department of Electrical Engineering, Arizona State University, P.O. Box875706, Tempe, Arizona 85287-5706, U.S.A.

†E-mail: [email protected]

Contract/grant sponsor: O�ce of Naval Research MURI programme.

Received 28 April 2000Copyright ? 2000 John Wiley & Sons, Ltd. Revised 28 July 2000

524 C. GEROUSIS, S. M. GOODNICK AND W. POROD

Figure 1. Equivalent circuit for a single-electron transistor.

of CNN circuits, where locally connected cells may alleviate the necessity for individualexternal interconnects to every cell. The main disadvantage with SET devices is that it isdi�cult to realize structures with su�ciently small capacitances such that they function atroom temperature, while device to device variations for present structures are quite large, anissue that has to be overcome by greatly improved process technology, or some scheme ofself-assembly to realize uniform arrays of structures. Analog CNN architectures o�er somepromise in this regard as they are less subject to process variations that would be problematicfor all digital technologies.Here, we investigate the use of nanodevices in cellular non-linear network (CNN) archi-

tectures [5,6]. Speci�cally, we focus on nanostructures based on single-electron tunnelling(SET) devices [3]. CNN-type architectures for nanostructures are motivated by the followingconsiderations: on the one hand, locally interconnected architectures appear to be natural fornanodevices where some of the connectivity may be provided by direct physical device–deviceinteractions. On the other hand, CNN arrays with sizes on the order of 1000× 1000 (whichare desirable for applications such as image processing) will require the use of nanostructuressince such integration densities are beyond what can be achieved by scaling conventionalCMOS devices.We �rst discuss the basic operation of SET transistors based on the phenomena of single

electron charging below in Section 2. Based on the master equation approach governingtransport through systems of tunnel junctions, we derive a simpli�ed quasi-analytical modelfor the I–V characteristics of SET transistors suitable for use in conventional circuit simulationtools such as SPICE. We then discuss the realization of CNN arrays in Section 3, startingwith a model for a basic CNN cell using all SET transistors, and then the simulation ofa three-cell linear array using a commercial SET simulation tool, SIMON [7]. In the �nalsection, we conclude discussing the relative strengths and weaknesses of this approach.

2. SINGLE-ELECTRON TUNNELING (SET) TRANSISTORS

Figure 1 shows a schematic of a basic SET transistor, which consists of two tunnel junctionscharacterized by junction capacitances, Cs and Cd, and tunnelling resistances, Rs and Rd. Atunnel junction usually consists of a thin oxide or other insulator with a high potential barrier

Copyright ? 2000 John Wiley & Sons, Ltd. Int. J. Circ. Theor. Appl. 2000; 28:523–535

TOWARD NANOELECTRONIC CELLULAR NEURAL NETWORKS 525

separating two conducting electrodes (either metal or semiconductor). When energeticallyfavourable, electrons can tunnel across the oxide barriers resulting in current ow and anassociated resistance. If the capacitance, C, of a junction (roughly proportional to the surfacearea) is su�ciently small, the associate charging energy associated with the transfer of a singleelectron across the junction, e2=2C; may be appreciable, leading to single-electron e�ects inthe current voltage characteristics discussed in a variety of sources [3,8].In the so-called SET transistor of Figure 1, the two junctions are separated by a conducting

‘island’ (or ‘quantum dot’) which is coupled capacitively to a gate bias, while a source–drain bias is applied across the tunnel junctions as shown. If the size of the island or dot issu�ciently small, quantum con�nement may lead to the formation of discrete states formingan arti�cial atom or molecule. In order to inject an electron from the source into the islandunder a positive applied bias Va requires an additional voltage �V¿e=Ct (where Ct is thetotal capacitance of the island) to overcome the charging energy of moving the electron.This leads to the phenomena of Coulomb blockade, which exhibits itself as a suppressionof current in the I–V characteristics of the double junction system for small source–drainbiases, as illustrated in the simulated data shown in Figure 2(a). This region of Coulombblockade may be subsequently removed by changing the energy of the island itself withthe gate electrode, which allows electrons to tunnel from source to drain. This region wheretunnelling occurs is periodic in the gate bias corresponding to stable integer numbers of excesselectrons residing on the island, as illustrated in the simulated I–V characteristics shown inFigure 2(b), shown as a function of gate bias for a small applied source–drain bias.Formally, transport through such structures may be modelled using a master equation ap-

proach for the time-dependent distribution function governing the number of electrons residingon the individual islands of a SET array (see Reference [3] and reference therein). For a gen-eral array consisting of N islands, the probability of the array having a given arrangement ofexcess electrons on each island is given by the solution of the balance equation governingprocesses, which add and subtract electrons from each island

@f(n1; n2; : : : ; t)@t

=∑j=1; N

�+j (n1; : : : ; nj − 1)f(n1; : : : ; nj − 1; : : : ; t) + �−

j (n1; : : : ; nj + 1)f(n1; : : : ; nj + 1; : : : ; t)− [�+j (n1; : : : ; nj) + �−

j (n1; : : : ; nj)]f(n1; : : : ; nj; : : : ; t)

(1)

where f(n1; n2; : : : ; t) represents the normalized probability of the system being in a statecharacterized by n1 electrons on node 1, n2 electrons on node 2, etc., while �±

j represents thenet tunnelling rate into (upper sign) or out of (lower sign) island j. The tunnelling rate foran electron across a particular tunnel junction, �, may be approximately written as

�=1e2RT

−�E1− exp(�E=kBT ) (2)

where �E=Eafter − Ebefore is the change in the free energy during a tunnelling event, andRT is the resistance of the junction (which in general is a non-linear function of the appliedvoltage). The net tunnelling rate appearing in the r.h.s. of Equation (1) for a particular islandis the sum of the tunnelling rates across all junctions connected to the island. Solution of themaster equation determines the charge state of each junction, which in turn allows for thecalculation of the tunnelling currents and hence the overall terminal characteristics.The theoretical I–V characteristics shown in Figure 2 are calculated using two di�erent

techniques. A standard approach at present is to solve the master equation using Monte Carlo



Figure 2. (a) Drain current of a SET transistor as a function of drain–source voltage. (b) Draincurrent versus gate bias for the SET transistor in Figure 1. The parameters for this simulation areCs =Cd = 1:6 aF; Cg = 3:2 aF, Rs =Rd = 100M; T =3K. The solid curve corresponds to simulation

results using SIMON while the open circles correspond to analytic results.

techniques, where random tunnelling events are simulated using the computer random numbergenerator and the calculated probabilities for tunnelling based on Equation (2). The solid linesin Figures 2(a) and 2(b) are the result of using the commercial software package, SIMON 2.0,a single-electron circuit simulator based on a Monte Carlo simulation [7]. While providinga direct solution of the master equation, including higher-order corrections for phenomena



like co-tunnelling (tunnelling across multiple junctions), the disadvantage of Monte Carlobased simulation is the computation time and compatibility with commercial integrated circuitsimulation packages based on SPICE.The open circles in Figures 2(a) and 2(b) are simulated through a SPICE compatible SET

transistor model, which we have developed in previous work [9]. The advantage of the secondmodel is its compatibility with conventional MOS transistor modelling, and hence the abilityto model hybrid MOS=SET transistor circuits. Moreover, this model takes as its input thephysical parameters of the SET structure, and no extraction of SET equivalent-circuit modelsis needed, as in other models proposed in the literature [10].The main insight of our work is that out of all the many possible tunnel events which

contribute to the current (and which are included in the full Monte Carlo models), only a feware truly signi�cant and need to be considered. Speci�cally, current across the SET transistorshown in Figure 1 may be viewed as the combined process of an electron tunnelling �rstacross the source— and then the drain junction (with rates �s and �d, respectively). Thecurrent then can be written as

Ids = e�s�d�s + �d

(3)

where the rates (within the ‘orthodox theory’) are analytic functions of the SET parametersand the applied biases, Vds and Vgs. Speci�cally, the rates given by the changes in energy,which can be expressed as junction charges in the following way:

�Es =eC�Qs with Qs = (Cd + Cg=2)Vds + CgVgs − e=2 +Q0 (4a)

�Ed =eC�Qd with Qd = (Cs + Cg=2)Vds + CgVgs − e=2 +Q0 (4b)

In the above expressions, C� is the sum of all capacitances and Q0 represents some backgroundcharge. This model is valid a long as the central island has one extra electron, i.e. the onethat carries the current. The range of validity of the model can be expressed as

0¡Qs¡e and 0¡Qd¡e (5)

For bias conditions outside this range of validity, a straightforward extrapolation proceduremay be applied for the rates, and thus the current.This simple analytical model for the I–V characteristics of a single-electron transistor yields

excellent agreement with full-scale Monte Carlo simulations using SIMON 2.0 as shown inFigures 2(a) and 2(b), for both the dependence of I on Vds and Vgs. Our model is basedon the physical picture that the SET current is primarily carried by one extra electron onthe central island and with tunnelling rates, which are given by the ‘orthodox’ theory ofsingle-electron phenomena. This I–V model is su�ciently simple to make it useful for circuitsimulations.Based on the non-linear behaviour of the SET transistor shown in Figure 2, two such

transistors may be combined to form an inverter as proposed by various authors [4,11], andshown in the inset of Figure 3. The inverter can be formed by combining two SET transistorstogether as shown, with a common input, Vin, and a load capacitor, CL. Although not ideal,this structure does provide an inverter like transfer characteristic between the input and the



Figure 3. I–V characteristics for a SET inverter modeled using SIMON (data points) for various loadcapacitor values, and the analytic model (solid curve).

output, as shown by the SIMON 2.0 results for various values of the load capacitor. For largeload capacitance, the result using the analytic model developed above is shown, which is inexcellent agreement with SIMON. We will return to this inverter structure below in Section 3as it forms the basis of the nonlinear transfer characteristic necessary for CNN-typeapplications.

3. CNN CELL DESIGN USING SETS

Neural networks derived from neurobiology and adapted to integrated electronics have key fea-tures such as parallel processing, continuous time dynamics, and global interaction of networkelements. Some applications of neural networks that have been proposed include optimization,linear and non-linear programming, associative memory, pattern recognition, and computer vi-sion. A new circuit architecture called cellular non-linear networks (CNN) was �rst proposedby Chua and Yang [5]. The CNN is a parallel computer network capable of exceptionalspeed and power and has broad applications in the area of image and video signal processing,robotic and biological vision. The basic circuit unit of a CNN is called a cell. In its usualimplementation in MOS IC technology, it consists of linear resistors, capacitors, linear andnon-linear controlled sources, and independent sources. Each cell is a dynamical system thathas an input, output, and a state evolving in relation to dynamical laws. A cell is coupledto neighbouring cells and may interact directly with other cells within a sphere of in uence



Figure 4. Array of CNN cells, with a 3× 3 sphere of in uence (a) and a 5× 5 sphere of in uence (b).

Figure 5. An isolated CNN cell.

as seen in Figure 4 for the case of a planar array. Cells that are not connected directly cana�ect each other due to the propagation of the time dynamics of the CNN.For a two-dimensional CNN, there are four variables associated with a cell: the input uij,

threshold zij, state xij, and output yij. An isolated cell is schematically represented in Figure 5.The state equation of the cell consists of a system of ordinary di�erential equations

xij(t)=f(xij(t); zij(t); uij(t)) (6)

The output, if a function of xij only can be written as

yij(t)= gij(xij(t)) (7)

The standard isolated CNN cell that was �rst proposed by Chua and Yang has the stateequation

dxijdt= − xij + aijf(xij) + bijuij + zij (8)

where aij and bij are weighing coe�cients. The output, yij, is a non-linear function of xij,which in most applications switches between two bi-stable regions of operation, for example,the piecewise linear function

yij=f(xij)= 12(|xij + 1| − |xij − 1|)=

1; xij¿1xij; |xij|¿1−1; xij61

(9)

A CNN cell Cij is coupled locally to cells that lie within the sphere of in uence Sij(r)of radius r. Both the input ukl and the output ykl of all neighbouring cells within Sij are



Figure 6. CNN interconnects: (a) feedforward synapses; and (b) feedback synapses.

coupled to cell Cij. Each CNN cell can be considered as a neuron coupled to neighbouringneurons through synapses. The centre cell Cij receives a weighted feedforward signal bklukland a weighted feedback signal aklykl from each neighbouring cell Ckl. The feedforward andfeedback signals lines are illustrated schematically in Figure 6. The state equation of a standardCNN can be written as

xij(t)= − xij + zij +∑kl∈Sij

aklykl +∑kl∈Sij

bklukl (10)

and the output of standard CNN is

yij=f(xij) (11)

It is interesting to note that the master equation (1) for a SET array has the same form as thestandard CNN dynamical equation (10), both involving �rst-order equations in time. In thecase of a SET array, it is the total charge in the array that changes dynamically with time,and controls the voltages and currents in the system.The CNN template de�nes the interconnection weights among the cells and determines the

functionality of the CNN. The ‘cloning’ template consists of the control matrix A that modu-lates the action of the input signal, the feedback operator B that de�nes the interaction strengthbetween adjacent cells, and the threshold z that describes the transfer function. The buildingblock of a CNN in CMOS implementations of such architectures [12] is a summing nodecoupled to a transconductance element (voltage-to-current-transducer) that switches betweentwo stable operating points. The transconductance element resembles that of a CMOS inverterand because of its simplicity, it can be integrated in the CNN cell circuit. The summing nodecouples the outputs and inputs in adjacent neighbourhood cells to the input of the transducer.The SET realization of this ‘neuron’ is illustrated schematically in Figure 7, which is based

on a circuit proposed by Goosens et al. [13]. It consists essentially of the SET inverterdiscussed in Section 2, which provides the bistable behaviour similar to a CMOS transducerelement, and it has multiple capacitive inputs to the inverter to form the summing node suchthat the input voltage is the weighted sum of the external voltages, with weights determined



Figure 7. Schematic structure of a SET summing node=transducer element forapplication in CNN circuits.

Figure 8. Simulated results for di�erent input conditions for the circuit in Figure 7 using SIMON.

by the capacitance value of each input signal. The transfer characteristics of the neuron circuitas a function of various input voltages, obtained using SIMON 2.0, is shown in Figure 8,simulated at 300K. For the SET transistor to operate at room temperature, the tunnel ca-pacitances need to be chosen on the order of 10−19 F, such that the single-electron chargingenergy, e2=2C � kbT . Future reductions of the device dimension are predicted to reach suchsmall capacitances, and hence allow room-temperature operation, although at present this isdi�cult. As can be seen, a bi-stable operation is obtained based on the sum of the input volt-ages to the transducer node. One main di�erence from a conventional CMOS implementation



Figure 9. A three-cell SET–CCD network with a positive feedback template. The inset shows thecapacitive template values as well as the input to output truth table.

is that due to the periodic dependence on gate bias, the output characteristics are actuallyperiodic functions of the input rather than truly bi-stable.The SET neuron cell can be generalized to a one-dimensional CNN image processor for

connected component detection (CCD) which counts the number of connected components ofa 1− d vector in {+1;−1}N . The cloning template for a conventional CNN is given by [14]

A=[1 2 − 1]; B=0; Z =0 (12)

When the initial condition Vx1(0)= − 1, the left-most cell must be , the CNN counts thenumber of connected components of ’s. Conversely, if the initial condition Vx1(0)= +1 theCNN output will contain the number of connected components of ’s.A three-cell SET–CNN CCD circuit is shown schematically in Figure 9. The feedback

template of the SET–CNN is de�ned by the coupling capacitors that determine the weightsamong the cells, whose values are given in the �gure. In order to stabilize the circuit, it wasfound necessary to add an additional inverter stage to the output of the SET neuron of Figure7, and to take the feedback from the intermediate stage as shown in Figure 9. Figure 10shows simulated transient results for the three-cell SET–CNN using SIMON. As seen fromthe �gure, the output evolves dynamically from the initial state, with an output high for apixel of about 0:45V and an output low for a pixel of approximately 0:05V. The truth tableof the simulated three-cell SET–CCD network is shown in the inset of Figure 9. The tableshows only partial functionality of a CCD namely, starting from the left most cell, the �nalstate of pixels alternates between and , or vice versa. The problem in realizing the fullCCD truth table lies in the lack of negative feedback in the present implementation due to theuse of capacitive coupling to realize summing. Therefore, it is di�cult to realize the negativeelement of the cloning template given in Equation (12) in the present scheme.Unlike the CCD CNN which requires a negative feedback, a ‘shadowing’ CNN has only

positive control and feedback connections and requires only one inter-cell connection as de-



Figure 10. Simulated results for the three-cell SET–CCD. The curves show the cell output voltages.

Figure 11. A three-cell ‘shadowing’ SET–CNN. The inset shows the capacitive template values as wellas the truth table exhibiting full shadowing behaviour.

scribed by the template: A=[0 2 1]; B=1; Z =0. In the ‘shadowing’ CNN, cells to theleft or right of a ‘high’ cell in the input are ‘shadowed’, and in the output are high as welldepending on the orientation of the ‘light source’. The implementation of a ‘shadowing’ SET–CNN circuit is shown in Figure 11, where C12 and C23 are eliminated in the basic three-cellCNN of Figure 9, leaving the SET network with only one inter-cell connection. Also, thefeedback is now taken directly from the output rather than the intermediate stage as shown,which resembles more closely the CNN topology discussed earlier in connection with Figures4–6. The capacitance template is C11 =C22 =C33 = 0:1 aF and C21 =C32 = 0:55 aF.In the three-bit example of Figure 11, whenever a 1 occurs in the input, all the cells to the

right (including the high-input cell) are high in the output, corresponding to ‘shadowing’ ofthe output bits by the input bits. Since no negative feedback is required in the template, the



Figure 12. Transient response for the three-cell ‘shadowing’ SET–CNN. The curves showthe cell output voltages.

SET implementation of the shadowing CNN functions correctly in contrast to the CCD case,as shown by the truth table in the inset of Figure 11. The transient simulation results for twodi�erent input conditions in the ‘shadowing’ SET-CNN are shown in Figure 12. Again, theoutput evolves dynamically to a stable condition corresponding to the truth table of Figure11 according to the current input.

4. DISCUSSION AND CONCLUSIONS

Herein we have discussed the use of single-electron tunnelling (SET) transistors, and theirimplementation to realize CNN type architectures. The basic functionality required for CNN-like behavior exists in SET circuits through the realization of a non-linear input to outputtransformation using a SET inverter topology coupled with capacitive summing elements. Inparticular, a three-cell shadowing CNN was demonstrated as well as most of the requirementsfor connected component detection.The limitation of the use of capacitive elements to realize summing is that only positive

weights can be achieved, which precludes most templates of interest other than shadowing.Also, the template itself can only be changed by changing the physical values of capacitorsthemselves, and hence is not independently programmable, which ultimately would be desir-able for image processing applications. Hence, future work will address feedback using activeelements, such as SETs themselves to realize a full range of templates in a programmablefashion.

ACKNOWLEDGEMENTS

The authors would like to acknowledge the support of the O�ce of Naval Research MURI programmein this research.



REFERENCES

1. Likharev KK. Single-electron devices and their applications. Proceedings of the IEEE 1998; 87(4):602–632.2. Csurgay AI. The circuit paradigm in nanoelectronics. Proceedings of the ECCTD’97, 1997; 240–246.3. Ferry DK, Goodnick SM. Transport in Nanostructures, chapter 4. Cambridge University Press: Cambridge,1997.

4. Chen RH, Korotkov AN, Likharev KK. Single electron transistor logic. Applied Physics Letters 1996;68(14):1954–1956.

5. Chua LO, Yang L. Cellular neural networks: theory. IEEE Transactions on CAS 1998; 35:1257–1272.6. Chua LO, Yang L. Cellular neural networks: applications. IEEE Transactions on CAS 1998; 35:1273–1290.7. Wasshuber C, Kosina H. SIMON: a single-electron device and circuit simulator. Superlattices andMicrostructures 1997; 21(1):37–42.

8. Grabert H, Devoret MH (eds). Single Charge Tunneling, Coulomb Blockade Phenomena in Nanostructures;NATO ASI Series B: Physics, vol. 294. Plenum: New York, 1992.

9. Wang X, Porod W. Analytic I–V model for single-electron transistors. VLSI Design 2001, to appear.10. Yu YS, Lee HS, Hwang SW. SPICE macro-modeling for the compact simulation of single electron circuits.

Journal of Korean Physics Society 1998; 33(Suppl):S269–S272.11. Tucker JR. Complementary digital logic based on the Coulomb blockade. Journal of Applied Physics 1992;

72:4399–4413.12. Baktir I, Tan M. Analog CMOS implementation of CNN. IEEE Transactions of the CAS II 1993; 40:200

–206.13. Goossens J, Ritskes J, Verhoeven C, van Roermund A. Learning single electron tunnelling neural nets.

Proceedings of the ProRISC Workshop on Circuits, Systems and Signal Processing, vol. 1, 1997; 179–186.

14. CNN Software Library (Templates and Algorithms) V 7.2. Analogical and Neural Computing Laboratory,Computer and Automation Institute, Hungarian Academy of Sciences, 1998.


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Toward nanoelectronic cellular neural networks