Topic 7 Hagen

7/31/2019 Topic 7 Hagen

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7-1

Applying Digital Technology toPWM Control-Loop Designs

Mark Hagen and Vahid Yousefzadeh

A bstrAct

This topic discusses the application of digital-control to DC/DC-switching converters and how to model the digitally controlled system. The main blocks that appear in almost every digital controllerthe error

ADC, the compensator, and the digital PWM engineare discussed and used to model small-signal characteristics such as frequency response, stability criteria, the effects of quantization, as well as theimpact of sampling rate and delay introduced by the digital controller to the system. This model is extended to include nonlinear gain and its benefits. Finally, a graphical user interface is introduced and demonstrated for use with the design of a two-phase synchronous-buck converter.

I. I ntroductIon

Switch-mode power-supply (SMPS) convertersfind use in a wide variety of applications, rangingfrom a fraction of a milliwatt in on-chip power management to hundreds of megawatts in power systems. All of these applications require efficientand cost-effective static and dynamic power regulation over a wide range of operatingconditions. An analog or digital controller closesthe feedback loop around the switching converter and actively controls the on/off states of the power-semiconductor devices to achieve input or output

regulation. Fig. 1 shows a typical analog controller that uses analog feedback to provide output voltage

regulation.Over the past few decades, digital controllersin the form of digital-signal processors (DSPs),microcontrollers, and field-programmable gatearrays (FPGAs) have seen extensive application inmotor-drive controllers and high-voltage and high-current power electronics. In these applicationsthe control algorithms are generally sophisticated,while the semiconductor devices operate atrelatively low switching frequencies, e.g. at tensof kilohertz.

Fig. 1. Analog-controlled SMPS.

Compensator

PWM

1 2

Vg

Vout

RESR

RL2

RL1

L2

L1

i2

i1

R

C+

V

C

d (t) e (t)

Vref

++

+

+ +

Vramp Vramp

+

+


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Continued rapid advances in CMOS and VLSItechnology have enabled the development of ahigh-performance, practical, cost-effective, andlow-power digital SMPS controller. Fig. 2 shows a

block diagram of an advanced digital controller that closes the feedback around a SMPS. Such acontroller, because it is implemented in a digitalsilicon technology, usually includes a standardcommunication block; general-purpose ADCs(ADCs); digital I/Os; memory; and a processingunit (microcontroller) that handles programming,communication, diagnostics, power management,etc. The result is that a digital controller not onlyregulates the output voltage, but also can performcomplex sequencing and can monitor key

parameters like average current and power for thehost system.

This topic focuses on the use of digitaltechnology to implement a SMPS controller.Specific examples are for a non-isolated point-of-load (POL) application. We first review thetechniques necessary to model the discrete timecontroller. Then the new features and functionsthat digital control enables are discussed. Thereare three specific blocks that enable the digitalcontroller to achieve the high-performanceregulation requirements of an SMPS: the ADCused to sample the error voltage (and an associatedsetpoint reference DAC), the digital filter thatcompensates the error signal, and the digital pulse-

width modulator (DPWM) that converts the

sampled, compensated error signal into the gate-drive signals.

Because most digital controllers contain aserial interface, they can be easily configuredfrom design software. This allows the designsoftware to do the heavy lifting in terms of modeling the system and calculating appropriatecompensation for the SMPS. In this topic wediscuss the what goes on under the covers of thedesign software.

II. M odelIng A d IgItAl c ontroller

Switch-mode power supplies have always hada digital component; they have a control effortwith a discrete update interval. That interval is theswitching period. The net result is that there can

be a latency in the response to disturbance in thecontrol effort. When we analyze a SMPS system,this latency shows up as a rotation in the phase of the open-loop system. When we introduce digitalcomponents into the system, there are additional

phenomena that must be taken into account. Thesethings are:

Feedback quantization1.Control effort quantization2.Delay needed to sample the feedback and3.calculate the control effort

The key to implementing a digitally-controlled power supply is understanding these effects.

d [n ]

Vsense

Set/Measure V ;Report I , I ,Temperature andFaults

outin out

...c 1 c 2

e[n]

Vref

e(t)

Memory

+

Error ADC

Compensator G (z)C

DigitalPWM

ProcessingUnit

Monitor ADC Memory

DAC

Communication

Vg

Vout

RESR

RL2

RL1

L2

L1

i2

i1

R

C

+ V

C

+

Fig. 2. Digital controller in an SMPS.


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Fig. 3 shows the closed-loop block diagramfor a digitally controlled SMPS that first generatesan analog error voltage and then digitizes thatvoltage to calculate the PWM control effort. For this system the total open-loop gain is

T s G s H s( ) ( ) ( )=

(1)

Then the closed-loop gain, from the PWMcontrol effort, u, to the sensed output voltage,vsense , is

vu

G sG s H s

sense =+

( )( ) ( )1

(2)

The contributors to the closed-loop system areitemized in Table 1. To determine the frequencyresponse of the power supply, and from that,determine the stability margin of the system, we

need to define the dynamic gain for each block.Once we have the transfer function for each block,the standard measure of stability can be applied:

Gain Margin The inverse of the magnitudeof the open-loop gain, expressed in dB, at thefrequency where the phase of the open-loopgain is 180 degrees.Phase Margin The phase of the open-loopgain, expressed in degrees, where the magnitudeof the open-loop gain is 1.0 (0 dB).

In addition to developing a frequency-domainmodel of the system, it is important to develop atime-domain model of the digitally-controlled

power supply so that the effects of quantizationcan be observed. In the following sections we willwork our way around the feedback loop anddevelop the necessary description of eachfunctional block so that both a frequency-domainmodel and a time-domain model can be created.

III. P ower -s tAge M odelIng

The development of the frequency response of the plant is identical for analog or digitally-controlled power supplies. It is derived for theaverage model of the power stage(s). For a buck regulator, such as used in the POL power supply,the continuous-mode, small-signal-transfer function is simply

G s vduty

V G s plant out in LC( ) ( ),= =

(3)

where G LC(s) is the transfer function of the LClow-pass filter and load resistance of the power stage.

There are several reasons that the derivedfrequency response of the average model may beinsufficient when designing a digitally-controlled

G Delay 2 G Plant Vout G Div

KPWM KNLR KEADCd [n ] e[ n ]

u[ n ]

G(s )

H(s )

G Delay 1 G CLA KAFE ref Vr Ve

Vsense

KDAC+

Fig. 3. Closed-loop block diagram.

t Able 1. c losed -l ooP s ysteM

c ontrIbutors

K AFE Analog front-end gain in V/V

K EADC Error ADC gain in LSB/volt

K NLR Nonlinear boost gain

GCLA Control-law accelerator (digital compensator)gain

GDelay1 Total sampling and CLA computational delay

K PWM PWM gain in duty/LSB

GDelay2 On-time and any delay to multiple power stagesdriving V out

GPlant* Transfer function from the time location of thefalling edge of the PWM signal to V out of the

power stage

GDiv Divider network transfer function in V/V

*The frequency response of the plant is derived from the

average model of the power stage(s).


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power supply. Digital control introducesquantization of the error voltage and quantizationof the output-PWM control effort. There also areadditional delays in a digital system such as thetime it takes to convert the error voltage to anumerical value, and the time it takes the digitalfilter to calculate the control effort. Finally,

processing the error signal digitally enables non-linear gains to be applied to the signal. All of theseeffects are best observed in a time model of thesystem.

A time-domain model of the system shoulddescribe how variations in input voltage, loadcurrent, and duty cycle affect the output voltage.Since the power stage of a switching converter forms a nonlinear system, designing a linear controller usually involves linearizing this power stage. The traditional approach uses averagemodeling to provide a dynamic model for PWM-operated DC/DC converters [1]. The frequencyrange of interest is much smaller than the switchingfrequency, so the model ignores the switchingfrequency and its harmonics. The small-signallinear model of the power stage is easily derivedfrom the average model.

Although a linearized model based on switchaveraging provides accurate results at lowfrequencies, it starts to break down beyond about1/5 of the switching frequency, f sw. The phaseresponse exhibits large discrepancies between themodel and the measured behavior. This modelingerror becomes particularly important in the designof high-bandwidth switching converters.

Reference [2] discusses discrete-time modelingof DC/DC switching converters that take intoaccount the sampling effect of the PWM for analogcontrollers. Recently, the growing focus upondigital control for high-frequency DC/DCconverters has revived interest in discrete-timeanalysis and modeling [3]. Discrete-time modelingeasily incorporates the propagation delay of discrete components, computational delay, andDPWM delay into a dynamic model [4, 5]. Thefollowing sections discuss the techniques for switch averaging and discrete-time modeling infurther detail.

A. Review of the Average Model Switch averaging removes the switching

ripples in the inductor-current and capacitor-voltage waveforms over the switching period. Thefollowing equations define the low-frequencycomponents of the inductor and capacitor waveforms:

L d i tdt

v t

Cd v t

dti t

L TL T

C TC T

s

s

s

s

( ) ( )

( )( )

=

=

, and

,

(4)

where

x t Ts

( )

denotes the average of x(t) over an interval of oneswitching period, T

s:

x t x dT t

t T

s

s( ) ( ) .=+

(5)

Although averaging removes the high-frequency switching ripple, the average value stillvaries from one switching period to the next so asto model low-frequency variations. The differentialequations for capacitor voltages and inductor currents are derived for each switching interval(for example, the on time and the off time of theswitch in a simple buck converter). Averaging thedifferential equations for each switching interval

provides the desired average equations.The next step in obtaining the small-signal

model of the power stage involves linearizing theaverage equations. The capacitor voltage andinductor currents are generally nonlinear functionsof the signals in the converter (input and outputvoltages, duty cycle, etc.). To obtain the small-signal behavior of the power stage, perturb thesignals and the average values of capacitor voltagesand inductor currents around their steady-stateoperating point:

= +u t U ( ) ,

(6)

where


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equations for the small-signal values of . Fig. 4shows the small-signal model of a buck converter with inductor parasitic resistance, R L, and output-capacitor equivalent-series resistance, R esr . Dindicates the steady-state duty cycle, andD = 1 D.

The model of Fig. 4 provides the basis for

computing control-to-output-voltage (d-to-v out )and input-voltage-to-output-voltage (v g-to-v out )transfer functions.

B. Average Model with DelayA digital controller with an eADC sampling

once per switching period, generates a delayassociated with the sampling point within eachswitching interval. The average model presentedin the previous section does not include this delay.Therefore, the phase response differs significantly

from the actual small-signal transfer function. Theaverage model can be augmented with the knowndelay, t d, to produce a more accurate model:

G s

v

de G svd del

out t svd

d

= =( )

( ),

(7)

where G vd(s) is the control-to-output-voltagetransfer function found with average modelingand t d is the delay. From the point of view of the

power stage, the total delay is defined as the timefrom when the output voltage is sampled to the

falling edge of the controlled MOSFET switchingnode (for a trailing-edge modulation system).

t t td fallingedge sample= (8)

C. Discrete-Time Model Because averaging eliminates the high-

frequency components of the frequency response,it cannot predict sampling effects like perioddoubling that can occur in peak-current controlmode. Discrete-time modeling [4, 5] takes intoaccount PWM sampling. Also, an average modeldues not easily display the effects of quantizationand non-linear gain.

Fig. 5 shows a switching buck converter operating in closed-loop, digital-voltage-modecontrol. Fig. 6 shows waveforms illustrating thederivation of a discrete-time model thatapproximates the perturbation of the control-signalduty cycle, d, as a train of impulses. The

perturbation of the duty cycle occurs at themodulating edge of the PWM signal. The duty-cycle perturbation changes the state variables of the switching converter (capacitor voltages andinductor currents) at the modulating point and

propagates through the switching period. Discrete-time modeling obtains the capacitor-voltage andinductor-current values at the eADC sample pointsas a function of previous capacitor and inductor samples; the control signal, d; and the input

Fig. 4. Small-signal model of a buck converter with losses.

I dL

V d / Dg

R c

C Vg R load

Vout

1:D

R L L

iL

+

+

Fig. 5. Voltage-mode, closed-loop buck converter.

c(t)

R esr

R L

C

RHvo

H=1vc+

iLL

vref

DPWM eADCG(z)

Vg

+


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voltage, V g. The total delay, t d, shown in Fig. 6equals the time between eADC sampling and themodulation edge of the PWM signal.

To derive the discrete-time differentialequations for the capacitor voltage and inductor current, the state matrices for the power stage ateach switching interval must first be obtained:

x A x B V

v C x D Vq q g

out q q g

= +

= +

and

,

(9)

where q = 1 denotes on time, and q = 2 denotes off time.

For the switching buck converter with parasitic parameters shown in Fig. 5, the state matrices andvariables become:

A A AR R C

R R R C

R

R R L

R R R

L

esr esr

esr

L esr

= = =

+ +

+

+1 2

1( ) ( )

( )

( )

= = = =

= = =+

,

,B

L

B D D

C C CR

R R R

esr

1 2 1 2

1 2

0

1 0 0, , and

R R xv

iesr C

L

=, .

(10)

The z-domain control-to-output-voltagetransfer function can be determined from thesmall-signal discrete-time equations

x n=

Cxv n

x n [ ] [ ] [ ]

[ ] [ ].

d n

nout

+

=

1 1 and

(11)

Fig. 6. Waveforms illustrating derivation of a discrete-time model for a digitally-controlled SMPS.

nT s (n + 1)T s

(n 1)T + t +s d + nT + t +s d +

c(t)

x[n]x(t) + x(t)

x(t)x[n + 1]

t s t s

t

DTs

d

t d

td1 td1

1

1

12

2 2

2

p()d Tn s ()


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7-7

Table 2 shows the resulting discrete-time-model matrices and for the trailing- andleading-edge DPWM and the eADC samplinginstants during switch on and off time.

In Table 2, = (A 1 A 2)X p + (B 1 B 2)Vg,where X p = [V C IL]T represents the steady-statecapacitor voltage and inductor current. The small-signal z-domain control-to-output-voltage transfer function of the power stage is

G z

v

d

C I zzvd

out( )

( )

.= = 1 1

(12)

A software program such asMATLAB or Mathcad can easily

solve this equation. Alternatively, onecan further simplify the equation byreducing the exponential matricesusing the approximation e ATs I + AT s.The simplified results for the buck switching converter are shown inReference [4].

Fig. 7 compares the control-to-output-voltage magnitude and phaseresponse of a buck converter modeledwith the approaches described earlier

in this section. The parameters for

this converter are: L = 1 H; C = 4 x 200 F;R esr = 2 m; R L = 8.6 m; V g = 10 V; V out = 1 V;R = 10 ; f sw = 500 kHz; and t d = 0.25T s + DT s,where D 0.1 and T s = 2 s. This shows that theaverage model including the total delay, t d, closelyapproximates the accurate frequency response of the discrete-time model.

The Texas Instruments Fusion Digital Power Designer PC program provides both an averagemodel with delay and a discrete-time model of thetarget system to assist in configuring the design of digital-power applications.

t Able 2. t he d Iscrete -t IMe -s tAte M AtrIces

Trailing-Edge DPWM

0 t < DT s, on-time sampling e e eA DT t A D T A ts s1 2 1( )

e e TA DT t A D T ss s1 2( )

DTs t < T s, off-time sampling e e eA T t A DT A t DTs s s2 1 2( ) ( ) e TA T t ss2

( )

Leading-Edge DPWM

0 t < DT s, off-time sampling e e eA D T t A DT A ts s2 1 2( )

e e TA D T t A DT ss s2 1( )

DTs t < T s, on-time sampling e e eA T t A D T A t D Ts s s1 2 1( ) ( ) e TA T t ss1

( )

Fig. 7. The control-to-output-voltage magnitudeand phase response of a buck converter.

40

10

20

30

20

0

30

100

M a g n i t u d e ( d B

)

0.1 1 10 100Frequency (kHz)

135

180

90

0

45

P h a s e

( d e g r e e s

)

No Delay

DelayIncluded

MATLAB is a registered trademark of TheMathWorks, Inc. Mathcad is a registered trademark of Parametric Technology Corporation.


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IV. d IVIder n etwork M odel

To estimate the stability margin from theaverage model or examine the cycle-by-cycle

behavior with the discrete-time model, we need todescribe each circuit around the feedback loop.The next circuit after the power stage is thevoltage-divider network. This circuit produces a

scaled sense voltage for the controller. It also can provide a compensation zero and a pole that actsas an anti-alias filter for the digital-controller ADC.

the compensation zeros that are created by thedigital filter in the controller, so C z is typically not

populated.Adding capacitor C p adds a pole to the overall

open-loop gain and can serve the useful purpose of attenuating frequency content in the sensed voltagethat has a frequency greater than 1/2 the samplerate of the controller ADC and compensator.Sampling theory states that harmonic frequenciesaround integer multiples of the sample rate(typically the same as the switching frequency, f sw)will alias to near DC and can cause an error in theregulated voltage. By rolling off the sense voltagefor frequencies above the ADC sample rate, weattenuate these errors.

CR R f p

=1

21 2 (for C = 0)2

(14)

To model the divider network in the discrete-time domain, we translate the transfer functionfrom the s domain to the z domain. In this case the

bilinear transformation is chosen. The bilinear, or Tustin transformation estimates the expressionz = e sT as

z esT

sT

sT=

+

1 2

1 2

/

/ (15)

Then we can express s as

s f

z

zsw=+

2

1

1

(16)

Substituting Equation (16) into (13) yields atransfer function in z. From the z-domain transfer function, we can write the discrete differenceequations shown in Equation (17) below.

This is the technique used in the TI Fusion Digital Power Designer program.

Fig. 8. Divider network.

CpR2

R1

G (f )Div

Cz

Vout

Vsense

To model the divider we first write out thetransfer function for the circuit in s. Here K div isthe DC divider ratio R 2/(R 1+R 2).

G s K R C s

K R C C sdiv div

z

div z p

( ) =+

+( ) +1

1

1

1

(13)

To calculate the system open-loop gain for aBode plot, this transfer function is evaluated ats = j2f and the resulting vector of values multi-

plied by the complex vector of gain values for the power stage. A compensation zero can be created by including a capacitor in the C z location.However, this zero will not be programmable like

v n v n K vsense

pole

pole sense Div

zero

pole se[ ]=

+

[ ]+

+

+

1

11

1

1

nnse Div

zero

pole sensen K v n

[ ]+

+

[ ]1

11

,

(17)

where

zero zsim

pole Div z psim

R CT

K R C CT

=

= +( )

1

1

2

2

,

.

and

(18)


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V. c oMPensAtor M odel

Digital controllers compensate the error voltage using digital-filter techniques. This enablesthe compensator to be programmable. It alsoallows the manufacturer to incorporate a nonlinear response to the error. The required number of

poles and zeros in the digital filter depends on the

application. For a voltage-mode buck regulator,two zeros are needed to compensate for the second-order plant (power stage) and a pole at the origin isneeded to minimize steady-state error. Controlengineers will recognize this as a proportional,integral, derivative (PID) compensator. Equation(19) is this two-zero, one-pole filter expressed inthe discrete-time, or z domain. Here z 1 representsa unit-sample delay.

G zd z

e z

K K z K z

zc ( )

( )

( )

= =+ +

0 11

22

11

(19)

One approach to constructing a digital filter to be used as the compensator is shown in Fig. 9.Here the multiplication of the error by thenumerator-filter coefficients K 0, K 1 and K 2 is doneusing a table look-up technique. This is the methodused by the Texas Instruments UCD9112 digitalcontroller. By using a table for each product in thenumerator of the compensator-transfer function,

non-linear gains can be built into the table. Thedown side to this technique is that the tables growgeometrically with increasing dynamic range onthe error signal. In the UCD9112 the sampled-error signal has a 4-bit range so each table is16 elements long.

Additional poles can be incorporated into thecompensator to shape noise in the compensatederror. The addition of a second pole has the effectof smoothing the quantization error in thecompensator output. In general, a two-zero/two-

pole digital filter has the following form:

G zd ze z

b b z b z

a z a zc ( )

( )( )

= =+ +

0 11

22

11

221

(20)

The discrete-time-domain difference equationresulting from Equation (20) is:

d n b e n b e n b e n

a d n a d n

[ ] [ ] [ ] [ ]

[ ] [ ]

= + +

0 1 21 2

1 2

1 2

(21)

Expressing the difference equation in this formis called the direct form. A direct-form digitalfilter has a topology that follows this equation asshown in Fig. 10. The Texas Instruments UCD92xxfamily of digital-POL controllers uses this filter arrangement for the compensator.

Fig. 9. Table look-up implementation of a digital filter.

e[n]

Numerator Denominator

e[n 2]

d[n 1]

d[n]

K0N K1N K2N

K00 K10 K20

z 1 z 1

z 1

K01 K11 K21

... ... ...... ... ...

Fig. 10. Direct-form digital-filter implementation.

e[n]

e[n 1] e[n 2]

z 1 z 1

b 0 b 1 b 2

d[n 1]

d[n 2]

d[n]

z 1z 1

a 1 a 2

Numerator Denominator


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Finally, the two-pole, two-zero digital filter can be realized as a parallel-filter structure. Somedigital controllers use this implementation for thecompensator. The classic proportional, integral,derivative (PID) controller is a parallel filter structure. Even if the hardware realization of thefilter is not implemented as a PID controller, it isuseful to express the filter in this formmathematically.

G zd ze z

K K z

zK

zzc P I D

( )( )( )

= = +

+

11

(22)

In Equation (22), we see that a PID compensator is the sum of the voltage error multiplied by a

proportional gain, K P, the voltage error multiplied by a integral gain, K I, and accumulated, and thevoltage error subtracted from the previous voltageerror and multiplied by K D. We can multiply this

expression out so that it is expressed as a ratio of polynomials with a common denominator as inEquation (23) below to show that the PID controller is an equivalent representation of the direct-formfilter.

In Fig. 11, d I[n] is the integrator state andrepresents the average duty cycle for the controlled

loop. d D[n] is the derivative state and is zero atsteady state. Of the three K gains, K D is the largestand is a function of the location of the zeros in thecompensator-transfer function. We will come back to this interpretation of the compensator when wediscuss quantization.

A. Choosing the Digital-Compensator Coefficients

One of the most straightforward ways todetermine what compensation to apply to a switch-mode power supply is to express the total open-loop gain as described in Equation (1) and plot themagnitude and phase of the loop gain as a Bode

plot. From the Bode plot, the stability metrics of phase margin and gain margin can be determinedand adjustments to the compensation made untilthe desired metrics are obtained. Since most power engineers are familiar with the behavior of thetotal loop gain as the gain and compensating zerosare changed, it is advantageous to first define thecompensation as a continuous-time transfer function with specified gain, zeros, and poles.Then this continuous-time transfer function is

G zK K K z K K K z K K

z zc

P I D P I D P D( ) =+ +( ) +( )+ +( ) + +( )

+( ) +

2

2

1 2

1

(23)

Fig. 11. PID digital-filter implementation.

e[n]

z 1

z 1

z 1

e[n 1]

KP

KD

K l

d [n]D

d [n]P

d [n]l

d[n]Proportional

Integral

Derivative


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7-11

transformed to the discrete-time domain todetermine the discrete filter coefficients.

G s K

s s

ss

c DCz z

p

( ) =+

+

+

1 2

2

1 1

1

(24)

Either Equation (24) or (25) can be used todescribe the continuous-time prototype controller.If the compensating zeros are complex, Equation(25) is a more convenient form.

G s K

s sQ

ss

c DCr r

p

( ) =+ +

+

2

2

2

1

1

(25)

Once the design parameters of r , Q, p2 andK DC are determined, the continuous-time transfer function is mapped to the z-domain using the

bilinear transformation.

s f z

zsw=

+2

1

1 (26)

Here f sw is the sampling frequency used by thecompensating digital filter. This is typically theswitching frequency. This mapping results in thefollowing relationship between the continuous-

time design parameters and the discrete-filter coefficients:

b K f

f Q f

b K

DC p

sw p

sw

c c sw

DC p

0 2

1

22 1 1

2

2

= +

+ +

=

f f

f f

b K f

sw p

sw

c sw

DC p

sw p

+

+

= +

4 1

2

2

2 +

2 1 122

f Q f

sw

c c sw

(27)

af

f

af

f

sw

sw p

psw p

sw p

1

2

42

2

2

= +

= +

(28)

To evaluate the frequency response of thecompensator as part of the total open loop gain,the discrete-time transfer function in z is evaluated

by substituting

z e j T= , (29)

where T is the sample period for the compensatingdigital filter. This is preferable to evaluating thecontinuous-time prototype compensation-transfer function because there are distortions introducedwhen doing the bilinear mapping from continuoustime to discrete time. This is because the bilinear transformation maps the entire left-half s-planeinto the unit circle of the z-domain. As a result, thespecified continuous-time transfer function willdiffer slightly from the discrete-time transfer function at frequencies near the Nyquist frequency.This distortion does not cause a problem as long asthe Bode plot, and the stability metrics derivedfrom it, are constructed using the discrete-time


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transfer-function polynomial and the substitutionof Equation (29). Equation (29) assumes there isan exact mapping between the continuous anddiscrete-time domains (see Fig. 12).

The most basic method of designing thecompensator tunes the zeros and poles to obtainthe desired bandwidth while maintainingreasonable phase and gain margins (>45 and>10 dB, respectively). However, these criteriamay not be sufficient to provide optimal

performance. Fig. 13 shows the loop gainof the switching converter introduced later in this paper for two different compensators.Both were designed in the s-domain andmapped to the z-domain with a bilinear transformation. Furthermore, bothcompensators contain a high-frequency

pole at p = 2 50 kHz and a DC gainof K dc 21150. The first compensator includes one real zero at the corner frequency, 0, of the power stages control-to-output-voltage transfer function, z1 =0 = 2 5.4 kHz, and a second zero atz2 = 2 6 kHz. This compensator,Gc1 (z), achieves a phase margin of m = 50, a bandwidth of f c = 30 kHz, anda gain margin of G m = 18 dB.

The second compensator, G c2, provides thesame bandwidth, f c, while maintaining a higher

phase margin. This compensator contains twocomplex zeros at the corner frequency of the

power stages control-to-output-voltage transfer function, 0. The Q c value of the compensator inEquation (25) is close to the Q value of the power stages control-to-output-voltage transfer function.

0.1 100

Response of discrete timepolynomial with coefficientscalculated using bilinear transformation

Response of continuoustime polynominal usingK , , , andDC z1 z2 p2

Examplef = 350 kHzGain = 150 kf = 3 kHz, 18 kHzf = 0 Hz, 50 kHz

sw

zerospoles

101Frequency (kHz)

50

40

30

20

10

45

0

45

90

G a

i n ( d B )

P h a s e

( D e g r e e s

)

Fig. 12. Frequency response of continuous-time and discrete-time compensator.

20

0

20

40

M a g n i t u d e ( d B )

10 k 100 k 1 M 10 MFrequency (Hz)

135

180

90

45

P h a s e ( D e g

r e e s ) T1

T1

T2

T2

Fig. 13. The closed-loop gain of the buck converter with (1)real zeros and (2) complex zeros.


13/28

7-13

This results in approximate cancellationof the double pole of the power-stageoutput filter. Fig. 13 shows that G c2(z)flattens the loop gain and increases the

phase margin to m = 65. Intuitively, thesecond compensator would be expectedto perform better than the first. However,the closed-loop converter with G

c2(z)

responds poorly to load transients. Fig. 14shows why. The closed-loop outputimpedance, Z out_cl , of the converter withthe Q of the zeros set to match the Q of the power stage, has a higher peak outputimpedance and therefore has a poorer response to load transients. For thisreason, it is advantageous for the designsoftware to present the expected closed-loop output impedance. The closed-loopoutput impedance is

ZZ

Tout clout op

_ _ .=

+1 (30)

Fig. 15 shows the results of simulatingthe closed-loop buck converter inMATLAB Simulink with the twocompensators, G c1(z) and G c2(z), for aload transient of 1 to 10 A. The closed-loop feedback using G c2(z) introducessignificant ringing at 0 due to the larger

magnitude of Z out_cl2 at this frequency.

100

80

60

40

20

0

M a g n i t u d e ( d B )

0.1 1 10 100Frequency (kHz)

Zout_c/2Zout_c/1

Zout_op

Fig. 14. The magnitude response of the open-loop and closed-loop output impedance.

0.94

0.96

0.98

1

1.02

1.04

0

5

10

iL2

0.1

0.15d 2

d 1

0.2

0.25

0 50 100 150 200 250Time (s)

D u t y C y c l e

I n d u c t o r

C u r r e n t

( A )

O u t p u t

V o l t a g e ( V )

vo1vo2

iL1

Fig. 15. Simulation results for a load transient of 1 to 10 A.

Simulink is a registered trademark of TheMathWorks, Inc.


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7-14

T o pi c7

VI. M odelIng the V oltAge -s ense Adc And

d IgItAl -PwM e ngIne

The three blocks that close the feedback loopand regulate the output voltage in a switchingconverter are the input ADC, the compensatingdigital filter, and the digital-PWM engine. Theinput ADC and the output digital PWM introduce

quantization error into the system. Also, thesefunctional blocks are the key elements indetermining the precision at which the outputvoltage can be regulated.

Regulating the sensed feedback signal to thedesired level requires a precise reference voltage,Vref . When this reference is programmable, it can

be used to precisely control soft start/stop rampsunder closed-loop control, to perform margining,and to provide a means of automated calibration.Factors that define the resolution requirements for

the setpoint-reference DAC are: 1) the desiredsetpoint resolution, and 2) the allowable error inthe output voltage during the soft start/stop rampdue to the discrete steps in the DAC outputcompared to a linear ramp. Resolution of a fewmillivolts is usually adequate.

There are two ways to subtract the sensedoutput voltage from the setpoint reference. It can

be done in a summing amplifier ahead of the ADCor it can be done digitally (see Fig. 16), after thesensed output voltage has been converted to

numerical values. In the first case, in order to provide programmability to the voltage setpoint, asetpoint reference DAC is provided and the error voltage is converted by the ADC. Since theresulting error voltage has a much smaller dynamicrange than the sensed output voltage, a fast,narrow-range ADC can be implemented in thecontroller. In this case the setpoint resolution, thatis, the precision to which the output voltage can be

programmed, is defined by the setpoint referenceDAC. The resolution of the error ADC is important

to the dynamic control of the output voltage, butdoes not influence the average DC-output voltage.An extreme example of this is the thermostat inyour house. It contains a precision setpointreference and a one-bit ADC with infinitely largeresolution.

The other way a digital controller can subtractthe sensed output voltage from the setpoint

reference is to first digitally sample the outputvoltage with an ADC with a wide dynamic rangeand then subtract this numerical value from adigital setpoint reference. In this case, the reso-lution of the ADC does in fact define the resolutionat which the system can set the output voltage.

Examples of digital controllers that use thenarrow-range ADC and separate setpoint-DAC arethe UCD9112 and UCD9240. On the other hand,

TI DSP controllers such as the TMS320C2801 usea full-range ADC.

A. Consequences of Sense-Voltage QuantizationWith any ADC, whether an absolute type or

window type, there is a trade-off between dynamicrange and resolution. By including an analog

programmable gain block in the error-voltagesignal path, the dynamic range and resolution can

be tailored for a given application. The system inFig. 17 has programmable gains of 1, 2, 4, and 8.

For an analog gain of G AFE = 1, this error ADC provides a resolution of 8 mV/LSB and a dynamicrange of 256 mV, while for G AFE = 8, it has aresolution of 1 mV/LSB and a dynamic range of 32 mV. Voltage-mode digitally-controlled DC/DC converters usually require an eADC resolutionof better than 0.2%. For example, non-isolatedDC/DC applications usually need error-ADC

error ADC

ref DAC

e[n]

KAFE

Vsensev (t)o

v (t)e

ref

+

+

ADC

KAFE

Vsensev (t)o v [n]o

ref

e[n]+

Fig. 16. Comparison of analog and digital

setpoint reference.

a. Digital setpoint.

a. DAC generated analog setpoint.


15/28

7-15

resolutions of 1 to 5 mV. The required range of theeADC depends on its application and should cover the required operational range for the load.

When we calculated the coefficients for thedigital-compensation filter, the dynamic range of the digitized output-sense voltage was not taken

into account. Most of the response to fastdisturbances to the control effort (such as a loadstep) is provided by the effective differential gainof the compensator. The digital filter generatesthis control effort by subtracting the most recenterror-voltage sample from the previous error sample and multiplying by a gain. In fact thedifferential gain is typically the largest gain in thecompensator. If the error voltage saturates becauseof the dynamic range of the ADC, the differentialcontribution to the control effort will drop to zero

and the transient response will be substantiallydegraded.

As an example of the effect of error-ADCsaturation, consider a system based on a continuous-time compensator with a DC gain of 14500, andzeros at 1.9 kHz and 16 kHz. Expressing thedigital compensator as a parallel-form PID filter,the gain coefficients are:

K P = 0.86; K I = 0.03; K D = 2.31In this case, the differential gain is 77 times

larger than the integral gain, so if the error ADCsaturates, a substantial portion of the control effortwill be lost.

If the dynamic range of the error voltage is oneside of the coin, quantization error introduced bythe error ADC is the other side of the coin. Theerror ADC effectively rounds the error voltage todiscrete integer values. Therefore, the output of the ADC, e[n], changes at voltages defined as

e n q n[ ] ,= +

1

2 (31)

where q is the quantization interval, or resolution,of the ADC. The ADC output gain, relative to thecontinuous-time input-error voltage is then shownin Fig. 18b. At steady state, the error voltage will

be near zero and a discrete sequence of error values {0, 0, 0, ...} will be applied to thecompensator. When the system is perturbed by asmall amount, the sequence will include isolated+1 or 1 values. Here it is instructive to use a

direct-form compensation filter to observe whathappens. For the example where the continuous-

error ADC

VDAC

ref

6-BitResult

PMBus

G AFE =1, 2, 4, or 8

G eADC =8 mV/LSBEAP x

V =1.563 mV/LSB

ref

EAN x vead

+

+

Micro-controller

Fig. 17. Block diagram of an eADC together witha programmable DAC.

Fig. 18. Error-voltage quantization.

8 6 4 2 0Error (q)

D i s c r e t e E r r o r

2 4 6 8 10 10

10

8

6

4

2

0

2

4 6

8

10 8 6 4 2 0

Error (q)

E f f e c t i v e

G a

i n

2 4 6 8 10 10

2.5

2

1.5

1

0.5

0

a. ADC in/out transfer function with quantization. b. ADC gain due to quantization.


16/28

7-16

T o pi c7

time prototype compensator has a DC gain of 14500, and zeros at 1.9 kHz and 16 kHz, thedirect-form numerator coefficients are

b0 = 0.539; b 1 = 0.942; b 2 = 0.406.This means that an isolated +1q error value willgenerate a control-effort output sequence of

{d, d, d + 0.539%, d 0.942%, d + 0.406%,d + 0.0034, d + 0.0034, d + 0.0034,...},

where d is the nominal duty cycle and % means percent of the switching period. So, in this example,if the switching frequency is 333 kHz, the pulsewidth will swing from increase by 16.2 ns, thendecrease by 28.3 ns, then increase by 12.2 ns, thenreturn to the nominal pulse width plus 100 ps.

B. Application of Nonlinear GainTo comply with todays tight requirements for

the transient performance of switching converters,the digital controller can apply nonlinear signal

processing to the compensation. This applicationof nonlinear gain can in some cases make up for the loss of phase margin due to the computationaldelay inherent in a digital controller. Digital non-linear control techniques remain the subject of much research. The main difficulty with thesetechniques is to define stability criteria in the

presence of all transients and operating conditions.This section introduces one of the digital nonlinear-control techniques implemented in TI devices.

Fig. 19 shows the diagram of a digital non-linear gain block. This block is situated betweenthe error ADC and the digital-compensation filter.

The error signal is compared to a set of program-mable limits which partition the dynamic range of the error signal into segments. This allows thegain to be individually programmed for each error-signal segment. As a result, the loop gain can bereduced for quiescent operating conditions wherethe error signal is near zero and the loop gain can

be boosted when a transient forces the error awayfrom zero. Fig. 20 shows an example where thecomparator limits are set to 6, 3, +3, and +5error-signal LSBs and the gains are set to 5.0, 3.0,1.0, 3.0, and 4.0.

Loop stability should be determined using thelargest gain applied by the nonlinear-gain block.This is particularly true if the gain is larger for error-signal values away from zero. It is these gainvalues that will be seen by the system during atransient and will determine the amount of ringingin the transient response.

Fig. 19. Digital controller with nonlinear quantization.

Fig. 20. Application of nonlinear gain.

x (n)CLAe(n)>>2

6

106 X

limit 0

limit 1

limit 2

limit 3

gain 0

gain 1

gain 2

gain 3

gain 4

SelectLogic

MUX

8 6 4 2 0

Error in LSBs

B o o s t e d E r r o r

2 4 6 8 10 10

40

30

20

10

0

10

20

30

40

50

8 6 4 2 0

Error in LSBs

E f f e c t i v e

G a

i n

2 4 6 8 10 10

6

5

4

3

2

1

0

a. Transfer function after nonlinear gain. b. Gain with nonlinear gain applied.


17/28

7-17

Fig. 21 shows captured scope traces of theoutput voltage with varying amounts of nonlinear-gain boost. The top trace has a uniform gainthrough the nonlinear-gain block, the second traceis the transient response for a case where a 3Xgain is applied when LSBs. The third trace showsthe response when the gain is 4X when LSBs.

VII. d IgItAl PwM e ngIne

The DPWM forms one of the most importantelements of a digital controller for a switchingconverter. As shown in Fig. 2, the DPWM obtainsthe duty-cycle information, d, at the output of thecompensator and generates switching signals, c 1 to cn, for the switching converter. High-resolution,high-frequency DPWMs are required to achievehigh-bandwidth, precise-voltage regulation indigitally-controlled switching converters. Although

dithering or sigma-delta approaches can be appliedto improve effective DPWM resolution to someextent, it is very desirable to achieve high-hardwareresolution using relatively minimal-hardwareresources. A direct implementation of an analogPWM in the digital domain produces a counter-

based DPWM [6]. An n-bit counter increments ateach input clock period, t clk . When the counter reaches its maximum value, it resets and startscounting from zero. The counter-based DPWMsinput-clock frequency, f clk , directly depends on the

number of bits in the counter, n, and the desiredswitching frequency, f sw: f sw = 1/T s, and f clk = 2 nf sw.A counter-based DPWM has the advantages of simplicity and linearity, however, this schemerequires many bits to achieve highresolution. Therefore, the requiredclock frequency, f clk , can becomeunreasonably large. For example,a 10-bit DPWM at f sw = 1 MHzrequires a clock frequency of f clk 1 GHz. This makes the

imple mentation of a high-resolution, high-frequency counter-

based DPWM very costly.Hybrid DPWMs [7, 8, 911]

can provide high resolution andhigh frequency without the veryhigh input clock frequencies

required by counter-based DPWMs, or the verylarge areas required by pure delay-line-basedDPWMs [12]. Fig. 22 shows an example of ahybrid DPWM with an open-loop delay line [13].The counter provides the most significant portionof the duty-cycle command, and the delay line

provides the least significant portion.The counter increments at each input clock,

clk. The output, c 1, is set high at the zero value of

0 200 600 800 1000

Time (s)

400

V

( V )

o u

t

1.3

1.25

1.2

1.15

1.1

1.05

1

0.950.9

0.85

0.8

load current

4X boost

3X boost

no boost

rmspk-pk

Fig. 21. V out with and without nonlinear-gain boost.

Parameter

Peak-to-Peak Output

Excursion

RMS ErrorDuring

QuiescentOperation

Uniform gain of 1X 130.5 mV 5.2 mV

Gain boosted 3X for |verr | > 5108.1 mV 5.0 mV

Gain boosted 4X for |verr | > 5

88.4 mV 5.0 mV

Fig. 22. Hybrid DPWM with external clock.

clkcnt

?=

del 0

delclk

i0 il i2 iL-1

msb (duty)

lsb (duty)

S = {cnt = 0}

output_sr

Counter n_bit

del 1 del 2 del L-1

R

D

Gate

Aclr Q

c 1


18/28

7-18

T o pi c7

the counter. Comparing the output of the counter with the most significant bits of the input duty-cycle command, msb(duty), produces the signaldelclk. The width of delclk equals one clock periodof the input clk signal. The signal delclk propagatesthrough the delay line. The output of each delaycell taps out and connects to an L:1 multiplexer.The multiplexer output is selected by observingthe least significant portion of the input duty-cyclecommand, lsb(duty). The appropriate input of themultiplexer is then connected to the output, R,which resets c 1. It is important to note that thefrequency of signal c 1 is still determined accordingto the relationship f clk = 2 Nf sw, where N representsthe number of bits in the counter. The hybridDPWM uses a smaller counter and thereforerequires a lower input-clock frequency than acounter-based DPWM with the same resolution.

To guarantee monotonicity and nearly optimallinearity, the total delay of the delay line shouldequal one clock period of the input clock. However,even in a very careful design, the cell delay varieswith process and temperature. Therefore, anadjustable delay cell is required to achieve thedesirable delay through the delay line. Furthermore,an active-control scheme must control the delaythrough each individual delay cell. In References[12, 14, 15], analog or digital phase-locked loopsor delay-locked loops adjust the delay of the delay

line in a DPWM in order to synchronize theoperation to an external clock.Fig. 23 shows another implementation of a

hybrid DPWM using a combination of a ring

oscillator and a counter to provide high resolution[7, 9]. This structure propagates a pulse around aring containing L-delay cells. Unlike the structureshown in Fig. 22, this topology does not require anexternal clock. Instead, the ring oscillates and so

provides an internal clock. The output of one of the delay cells connects to the input clock of then-bit counter that determines the switchingfrequency of the DPWM. The output, c 1, is setwhen the counter value, cnt, equals zero. Like thehybrid delay line of Fig. 22, both the appropriatedelay-cell output and the output of the n-bit counter determine the reset point of the DPWM. Reference[10] provides a complete list of different hybridDPWM architectures.

We can determine the effect of the finite pulse-width resolution out of a digital PWM by notingthat the output voltage of a buck regulator isD V

in. Then, expressing D in terms of the

effective clock rate of the PWM, the switching period and the number of clock cycles determined by the digital-compensator calculated control-effort, n, we can quantify the change in V out for each discrete change in the PWM output. This isshown in Equations (32) and (33).

V DVNT

TVout in

clk

swin

= =

(32)

V Resolutionout = T f Vclk sw i n

(33)

For example, if V in is 12 V, T clk = 250 ps, andf sw = 500 kHz, the V out Resolution is 1.5 mV.

Fig. 23. Hybrid DPWM with ring oscillator.

del 0

i0 il i2 iL-1lsb (duty)

clkcnt

?=

msb (duty)

Counter n_bit

del 1 del 2 del L-1

S = {cnt = 0}

output_sr

R 2

R 3

D

Gate

Aclr Q

c 1


19/28

7-19

A. Limit Cycling Digital-PWM resolution and error-ADC

resolution together determine output-voltageregulation. If the change in the output voltageresulting from a one-step change in the digitalPWM is much greater than the input resolution of the error-voltage ADC, limit cycling can occur [16, 17]. Limit cycling is the condition where theoutput voltage oscillates around the nominal outputvoltage. It can be predicted by examining thequantization in each of the three major blocks inthe controller. Limit cycling occurs when thevoltage resolution coming out of the integrator state is larger than the voltage resolution cominginto the integrator state. When this occurs, theregister or variable holding the integrator stateacts as a hysteretic memory element, where wehave to dump charge into or out of the state

before a change in the output can be observed.To determine if limit cycling will occur, the

quantization (expressed in volts) must be calculatedfor the signal path into the integrator state and for the signal path out of the integrator state. InFig. 24, we can work backwards from the PWMsignal to the integrator state. From Equation (33),we know the change in output voltage for eachLSB change in the PWM counter threshold. Thecounter threshold is the result of the compensator output times the switching period. In the UCD9240,

this is a fixed-point multiply where d[n] is a 16-bitsigned value and Period is a 14-bit unsigned value.The result is a 30-bit value, of which we keep18 bits by rounding and then dropping the bottom11 bits and the now redundant sign bit. So for thisdevice, when the switching frequency is 500 kHz,the value in the Period resistor is 500. This meansthat the integrator state must change by 4 LSBs for the counter threshold to change by one LSB andfor the output voltage to change by 1.5 mV. Further simplifying, for this device, each one LSB changein the integrator state causes a V in/215, or 0.366 mV,change in the output voltage with a 12-V input.

V

d n

f

f V

Period

f

f

V f

out sw

clk in

sw

clk

in clk

[ ]=

=

1 16 2

16 2

11

11

f f

V

sw

in=

+2 4 11

(34)

Working from the input, the effect on theintegrator state for a one-LSB error is the ADCgain times the nonlinear gain times the integrator gain of the compensator. The integrator gain (K I)is the sum of the b 0, b1, and b 2 multiply operations.For an example power supply, we choose the ADCgain to be 1/resolution = 1/2 mV; the nonlinear gain to be 2.0; and the integrator gain to be933 1532 + 611 = 12. Then the input voltagechange that causes a one-LSB change in the

Fig. 24. Location of the integrator state in the controller system.

ADC

Non-linear Gain

Block

AFE

e[n]v (t)en

Compensator

x[n]

x[n 1]z 1

x[n 2]

z 1

b 0 b 1 b 2

Period

d[n 1]

>>11

>>3

>>3>>3

d[n]

z 1

Integrator State

Periodx16

RampCounter

Reset

PWMPWM Engine

Ramp

Control Effort

f clk+

+


20/28

7-20

T o pi c7

other conditions. Real-time system identificationand controller autotuning can fine-tune controller

parameters, either during development or in actualoperation. This section describes the systemidentification and autotuning techniques used inthe TI UCD9240 digital controller.

A. System IdentificationPower-distribution systems containing

multiple-power sources may experience dynamic- performance degradation and even instabilitiescaused by uncertainties in the system parametersand interactions between different power modules.

An intelligent system within each power modulecan perform system identification. A central or distributed controller can use these results to fine-tune controller parameters. The inherent flexibilityand programmability of digital controllers makethem attractive platforms for automatic systemidentification. There are several digital-systemidentification techniques [1820]. In each case,the system is perturbed by an excitation signal andthen the response to that excitation is measured.The excitation signal can be an impulse, a step,

white noise, or a sine wave. Exciting the system by injecting a sine wave into the feedback loop isthe technique used by power system/dynamicnetwork analyzers because it produces the highestsignal-to-noise measurement of the system-transfer function. The UCD9240 digital controller and itssupporting design software use this approach.

integrator state is 0.667 mV. So in this case, thecriteria that the output resolution be finer than the

input resolution is satisfied.d n v t K K b b b

v td n K

err ADC NLR

err

AD

[ ]= + +( )

[ ]=

1 2

12

0 1 23

3

( )

( )

CC NLR K b b b 0 1 2+ +( )

From Equation (35), we can see that thecompensator gain, including the ADC andnonlinear gains, determines if limit cycling willoccur. Fig. 25 shows the output voltage for a

system where the nonlinear gain has been reduced by a factor of 8, from 4.0 to 0.5, for the zero-error voltage gain. In this case the input resolution is nolonger larger than the output resolution and limitcycling occurs.

VIII. s ysteM I dentIfIcAtIon And

A utotunIng

Most SMPS controllers are designed to obtainthe highest achievable dynamic performance. Suchdesigns require precise knowledge of the system

parameters and operating conditions. Furthermore,for a power module that operates in parallel or interacts with other modules, the overall systemmodel might not be predictable. Therefore, acontroller optimized for one set of operatingconditions might actually become unstable under

(35)

Fig. 25. Limit cycling with low nonlinear gain.

LimitCycling

No LimitCycling


21/28

7-21

The system identificationis entirely performed in theUCD9240 and the results arereported back to the GUI.This technique synthesizes adigital-sinusoidal signal andinjects it into the closed-loopsystem. Then the response tothat excitation is measured atanother point in the loop.From this measured closed-loop response the open-loopgain is calculated. Repeatingthis over a range of frequencies provides the datanecessary to create the Bode plot for the system.Fig. 26 shows the location of the injected signal,r[n], and of the measurement points e[n] and d[n]in the UCD9240.

In the usual way, we can write the transfer function from the reference to the output voltage.

vref

K T zT z

where

T z K H z K G

out DAC

AFE PWM D

=+

=

( )( )

,

( ) ( )

1

eelay Plant DivG G .

In the same way, we can write the transfer functionfrom the excitation x[n] to d[n].

d zx z

K K H zT z

DAC AFE( )( )

( )( )

=+1

(37)

Then we can solve Equation (37) for G Plant .G

K G G

K xd K H z

PlantPWM Delay Div

DAC

AFE

=

1

1 ( )

(38)

To generate the excitation signal, atable look-up technique is used. Thetable contains a sequence for one

period of the sine wave and a pointer isstepped through the table at differentrates to generate each excitationfrequency. To measure the response,the same table is used to generate acosine and a sine sequence. These twosequences are multiplied by theresponse vector, d[n], and summed toobtain a complex estimate of theresponse at the excitation frequency.This is repeated at each frequency for which a measurement is desired. Fromthe complex estimate of the response,we can generate the Bode plot for thesystem (see Fig. 27).

Compensator H(z)KPWM d [n ] e[n ]

r [n ]

ve vr KAFE + +KDAC

Excitation

Nominalref

VsenseG Delay 2 G Plant Vout G Div

u[ n ]

Power Stage G (s )

Digital Controller MeasuredResponse

(36)

Fig. 27. Bode plot measured with Auto-ID versus model.

30

20

10

0

10

20

0

50

100

150

200

250

G a

i n ( d B )

Frequency (kHz)

P h a s e ( D e g

r e e s )

1000100101

Model

Auto ID

Fig. 26. The injection and measurement for system identification inthe UCD9240.


22/28

7-22

T o pi c7

Because most of the gains in the system aredigitalthe compensator, the digital PWM, thecomputational delay, etc.this technique producesan accurate estimate of the transfer function of the

power stage. Then, once we have that estimate, wecan use it to make decisions about the optimalcompensation of the loop.

B. Autotuning Traditional controllers usually require redesign

or retuning during development to account for wide variations in the power-supply parametersand operating conditions. Most of the well-knowndigital autotuning techniques [21, 22] try to shapethe frequency response of the closed-loop gain.The controller coefficients are tuned to achieve thedesired phase and gain margins and loop bandwidth.These techniques do not guarantee optimal time-domain-transient performance.

A user interface that can communicate withthe digital controller provides an adequate tool for autotuning. The TI GUI [23] can performautotuning based on both the frequency responseof the system and the time-domain simulationresults. Autotuning based on frequency responsecan use the simulation results or the systemidentification technique described in Section VI.A.Fig. 28 shows the Auto-Tune design screen of theTI GUI for the UCD9240. The autotuning processuses criteria such as crossover frequency, phasemargin, gain margin, DC gain (the loop gain at

10 Hz), and the maximum closed-loop outputimpedance for frequency-response shaping. Theuser chooses the desired value and the weightapplied to each criterion. The GUI also supportstime-domain criteria including settling time,overshoot, and undershoot. The GUI iterates thecompensator coefficients to achieve the desiredfrequency response and time-domain simulationresults. After evaluating the results, the user can

load the final compensator coefficients into thedevice register of the UCD9240.

Fig. 28. TI GUI Auto-Tune design screen for the

UCD9240.


23/28

7-23

IX. d esIgn e XAMPle

This section describes a design example basedon the UCD9240 digital controller [7]. Fig. 29shows the implementation of a two-phase buck converter using an integrated driver and power MOSFET (DrMOS) [24], and the UCD9240digital-power POL-system controller [7]. The

signals CS.1 and CS.2 are used for current sharingwithin the UCD9240.

The power-stage parameters are as follows:L1 = L 2 = 0.363 H, inductor DC resistanceDCR1 = DCR2 = 2.4 m W, total output capaci tanceC = 3 470 + 12 47 F, capacitor ESR = 1 m W,Vin = 10 V, V out = Vref = 1 V, f sw = 350 kHz, and thevoltage-sense gain = 0.8.

A. UCD9240 Digital Controller Fig. 2 shows a simplified block diagram of the

UCD9240 digital controller [7]. This controller incorporates a window-type error ADC withanalog front-end gain, G AFE , and programmablegains of 1, 2, 4, and 8. The output of the eADC hasa 6-bit signed-integer format. The resolution of theerror ADC equals 1 mV for G AFE = 8. TheUCD9240 also provides a programmable referenceusing a 10-bit DAC. The DAC has a dynamic

Fig. 29. Block diagram of a two-phase buck converter using theUCD9240 digital controller.

P/CGND

P/CGND

0.363 H

0.363 H

13.3 k

13.3 k

CS.1

CS.2CS.1 CS.2

10 pF59 k

15 k VFB

C1

C 2

To Load

8 x 47F

3 x 470F

INA126

INA126

0.1 F

0.1 F

2 x 47F

2 x 47F

PWN

PWN

C1

C 2

Vsw

Vsw

V /VCin in

V /VCin in

R2J20602NP

R2J20602NP

PA0513.441

PA0513.441

UCD9240

Vin

Vin

+

+

range of 1.6 V, giving a resolution of 1.6 mV.Furthermore, the sampling frequency of the eADCdepends on the digital PWM switching frequency,f sw. The sampling location during one switching

period is programmable.The UCD9240 includes a high-resolution

hybrid DPWM as shown in Fig. 23. The digitalPWM implements a 4-bit ring oscillator. The clock frequency of the counter equals 250 MHz.However, because of the hybrid nature of thePWM engine, the resolution of the duty cycle isactually 250 ps. The PWM engine uses a

programmable switching frequency between15 kHz and 2 MHz with 4-ns resolution. It also

provides several outputs for synchronousrectification and supports programmable deadtimes with 250-ps resolution. The dead-time

programmability of the DPWM module helpsoptimize efficiency in a synchronously rectifiedDC/DC converter [25].

The input to the digital PWM consists of asigned 16-bit duty-cycle value from thecompensator. The PWM-engine design ensuresthat for any programmed value of switchingfrequency, the maximum value of the duty cycle(7FFF hex) provides a 100% PWM output(always on).


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The UCD9240 also contains a direct-form,two-zero/two-pole compensator like the one shownin Fig. 10. It also includes a cascaded first-order filter that adds another programmable pole andzero to the compensator. The compensator coefficients occupy a programmable 12-bit format.The sampling rate of the compensator issynchronized with the sampling rate of the eADC.In addition, a nonlinear gain block, shown inFig. 19 resides at the input of the compensator.

B. Controller DesignThe first step in designing the controller is to

model the power stage. A PC program [23] isavailable for the UCD9240 digital controller thatallows the user to design the controller withminimal effort. The user interface provides the

power stage, loop gain, and compensator frequencyresponse. Nonlinear gain is applied to improve thetime-domain-transient performance, and thecontroller coefficients are loaded into the UCD9240device registers.

Fig. 30 shows the window that receives the parameters of the two-phase synchronous buck converter. To obtain the small-signal model of the

power stage, the GUI models the two-phasesynchronous buck converter as an equivalent one-

phase synchronous converter with the inductor,L = L 1 L 1/(L1+L2); inductor series resistance,R L = R L1 ||R L2; and phase-capacitor equivalent-series resistance, R esr = R esr1 ||R esr2 . The GUIcomputes the control-to-output-voltage transfer function in a manner similar to that described. TheGUI can configure the sampling point of theeADC as a function of the phase of the switching

period. The GUI applies the total delay, from theeADC sample point to the falling edge of theDPWM, to the loop-gain response. The user canenter the s-domain compensator parameters byobserving the frequency response of the plant(power stage).

Fig. 31 shows the compensator design window.The GUI accepts the compensator coefficients invarious forms, including real zeros, complex zeros,

or PID coefficients. The user interface calculatesthe z-domain compensator-transfer function usinga bilinear mapping technique. The resultingz-domain transfer function is then applied to the

plant transfer function to provide the loop gain.The UCD9240 implements bit formatting andarithmetic in such a manner that the equivalentgain of the eADC and DPWM equals unity(neglecting the quantization effect on the gain).Therefore, the gain factors for the loop gain arethe control-to-output-voltage transfer function of the power stage, G vd; the output-voltage sense, H;and the compensator, G c.

Fig. 30. Power-stage parameters window.

Fig. 31. Compensator design window.


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Fig. 32 shows the loop gain and the control-to-output-voltage frequency response. As shown inFig. 31, the GUI also provides the frequencyresponse of the open-loop output impedance,Zout_op , and the closed-loop output impedance,Zout_cl . Fig. 33 shows that the magnitude of Z out_cl significantly decreases as compared to Z out_op atthe output-filter corner frequency. By observingthe loop gain and Z out frequency response, the user can fine-tune the compensator to provide optimalresults. The user can also apply the autotuningtechnique described in Section VIII.B to obtainthe desired frequency and time-domain response.

Fig. 34 shows the GUI window settings for thenonlinear-gain block. These nonlinear gainsimprove the transient performance. The thresholdvalues are defined based on the range of error, e.These values have a a 6-bit signed-integer formatand lie between 32 to 31. The gain blocks use a4.2-bit format where a value of 1 indicates unitygain. For the power stage and controller mentionedearlier, the nonlinear gain and threshold valuesimprove transient performance while maintainingstability.

To verify the performance of the designedcontroller, the user interface provides a time-domain load-transient simulation. In this part of the GUI, the user specifies the range and rate of the load step and the frequency of the load transient.

Fig. 32. Loop gain and control-to-output-voltage frequency response.

Fig. 33. Frequency response of open-loop and closed-loop output impedance.

Fig. 34. Settings for the nonlinear-gain block.

Open-LoopOutput Impedance

Closed-LoopOutput Impedance


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The output voltage and inductor current are thencomputed based on the power-stage parameters,and the compensator coefficients are found withthe discrete differential equations. Fig. 35 showswaveforms where a load transient of 50 A to 25 Awith a 5-A/s rate was applied to the output. Thetop waveform shows the value of v o Vref . Thelower waveforms show the inductor currents of the two phases.

C. Experimental ResultsThis section describes experimental results

based upon a two-phase synchronous buck converter implemented with the UCD9240. Thecompensator and nonlinear gains were based onthe values provided in the previous section. A loadtransient of 25 to 50 A with a rate of 5 A/s wasapplied to the output. A LeCroy scope set at2 mV/div and 100 MS/s recorded the effect of loadtransients on the output voltage. A low-noiseLeCroy probe measured the voltage. The sampleddata was captured through the USB port of thescope and plotted with MATLAB. Fig. 36 showsthe response to the step-down load transient. Theoutput-voltage overshoot closely follows theresults derived from the simulation. Fig. 37 showsthe experimental response to the 25- to 50-A step-up load transient. The step-up load-transientresponse exhibits a smaller-than-expectedundershoot (around 25 mV). However, the outputvoltage suffers from a longer settling time in thestep-up load transient. This longer settling timecompared to the simulation results is the effect of the load transient on the supply voltage, V in.Fig. 35 shows the effect of the load transient onthe input voltage (V g 10 V). Increasingthe low-esr bypass input capacitance, C in,improves the results.

Fig. 35. Simulation results of a 50- to 25-A load transient for a synchronous two-phase buck converter.

Fig. 36. The step-down load-transient response.

0 10 20 50 60 70 80 90 100

Time (s)4030

V

V

( m V )

o u

t

r e

f

100

50

0

50

100

0 10 20 50 60 70 80 90 100

Time (s)4030

V

V

( m V )

o

r e

f

V

1 0 V ( m V )

g

50

0

50

0

150

300

Fig. 37. The step-up load-transient response.


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X. c onclusIon

The development of a system model for acontinuous-conduction, voltage-feedback buck regulator was reviewed. This model was aug-mented to include the effects of quantization error and computational delay, which are unique todigital control. This model was then used to show

the onset of limit cycling due to error-voltagequantization and output-pulse-width quantization.The ability of a digitally controlled system tomeasure the transfer function of the closed-loopsystem without external test equipment was also

presented. The system model was also used toidentify (measure) the transfer function and howthe programmability of the digital controller can

be used to automatically tune the compensationfor the feedback loop of a switch-mode power supply.

The above digital-control fuctions wereimplemented with the TI Fusion Digital Power

Designer software. The software GUI simplifiesthe design steps required to develop a digitallycontrolled switching converter.

XI. A cknowledgeMents

The authors would like to thank our colleaguesin TIs digital power group for their contributionsto this article, particularly Michael Muegel for hiswork on the GUI. I would also like to thank AlanHastings, whose advice greatly contributed to thequality of this seminar topic.

XII. r eferences

[1] R. Erickson and D. Maksimovic, [Chapter title, in] Fundamentals of Power Electronics,2nd ed. Norwell, MA: Kluwer, 2000.

[2] A.R. Brown and R.D. Middlebrook, Sampled-data modeling of switching regulators, Proc.IEEE Power Electron. Specialists Conf., pp.349369, 1981.

[3] L. Corradini and P. Matavelli, Analysis of multiple sampling technique for digitallycontrolled DC-DC converters, Proc. IEEEPower Electron. Specialists Conf., pp. 16,June 2006.

[4] D. Maksimovic and R. Zane, Small-signaldiscrete-time modeling of digitally controlledPWM converters, IEEE Trans. Power Electron., Vol. 22, No. 6, pp. 25522556, Nov.2007.

[5] V. Yousefzadeh, M. Shirazi, and D. Maksimovic,Minimum phase response in digitally

controlled boost and flyback converters, Proc.IEEE Appl. Power Electron. Conf. andExposition, pp. 865870, 2007.

[6] W. Gu-Yeon and M. Horowitz, A low power switching power supply for self-clockedsystems, Int. Symp. Low Power Electron. andDesign, 1996, pp. 313317.

[7] UCD9240 Digital Point of Load SystemController, UCD9240 Datasheet, TI Literature

No. SLUS766

[8] Digital Dual-Phase Synchronous Buck Controller, UCD9112 Datasheet, TI Literature

No. SLVS711A

[9] B.J. Patella, A. Prodic, A. Zirger, and D.Maksimovic, High frequency digital PWMcontroller IC for DC-DC converters, IEEETrans. Power Electron., Vol. 18, No. 1, pp.438446, Jan. 2003.

[10] A. Syed, E. Ahmed, D. Maksimovic, and E.Alarcon, Digital pulse width modulator architectures, Proc. IEEE Power Electron.Specialists Conf., Vol. 6, pp. 46894695, June2004.

[11] A.P. Dancy, R. Amirtharajah, and A.P.Chandrakasan, High efficiency multiple-output DC-DC conversion for low-voltagesystems, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., Vol. 8, No. 3, pp. 252263, June2000.

[12] A.P. Dancy and A.P. Chandrakasan, Ultra low

power control circuits for PWM converters,Proc. IEEE Power Electron. Specialists Conf.,Vol. 1, pp. 2127, June 1997.

[13] V. Yousefzadeh, T. Takayama, and D.Maksimovic, Hybrid DPWM with digitaldelay-locked loop, IEEE Comput. Power Electron., Troy, NY, 2006, pp. 142148.


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[14] A. Syed, E. Ahmed, and D. Maksimovic,Digital PWM controller with feed-forwardcompensation, Proc. IEEE Appl. Power Electron. Conf. and Exposition, Vol. 1, pp.6066, Feb. 2004.

[15] A.V. Peterchev, Xiao Jinwen, and S.R. Sanders,Architecture and IC implementation of a

digital VRM controller, IEEE Trans. Power Electron., Vol. 18, No. 1, Part 2, pp. 356364,Jan. 2003.

[16] A.V. Peterchev and S.R. Sanders, Quantizationresolution and limit cycling in digitallycontrolled PWM converters, IEEE Trans.Power Electron., Vol. 18, No. 1, pp. 301308,Jan. 2003.

[17] H. Peng, A. Prodic, E. Alarcon, and D.Maksimovic, Modeling of quantization effects

in digitally controlled DC-DC converters,IEEE Trans. Power Electron., Vol. 22, No.1, pp. 208215, Jan. 2007.

[18] B. Miao, R. Zane, and D. Maksimovic, Systemidentification of power converters with digitalcontrol through cross-correlation methods,IEEE Trans. Power Electron., Vol. 20, No. 5,

pp. 10931099, Sept. 2005.

[19] B. Johansson and M. Lenells, Possibilities of obtaining small-signal models of DC-to-DC

power converters by means of systemidentification, Proc. Telecommun. EnergyConf., 2000, pp. 6575.

[20] M. Hagen, In situ transfer function analysis,measurement of system dynamics in a digital

power supply, Digital Power Forum, 2006.

[21] M. Shirazi, R. Zane, D. Maksimovic, L.Corradini, and P. Mattavelli, Autotuningtechniques for digitally-controlled point-of-load converters with wide range of capacitive

loads, Proc. IEEE Appl. Power Electron.Conf. and Exposition, pp. 1420, 2007.

[22] W. Stefanutti, P. Mattavelli, S. Saggini, and M.Ghioni, Autotuning of digitally controlled

buck converters based on relay feedback,Proc. IEEE Power Electron. Specialists Conf.,June 2005.

[23] Texas Instruments. Digital power software:Fusion digital power designer. [Online].Available: http://focus.ti.com/docs/toolsw/

folders/print/fusion_digital_power_designer.html

[24] Integrated driver MOS FET (DrMOS),Renesas, R2J20602NP Datasheet,REJ03G1480-0200, Nov. 30, 2007, http://documentation.renesas.com/eng/products/transistor/rej03g1480_r2j20602npds.pdf

[25] V. Yousefzadeh and D. Maksimovic,Sensorless optimization of dead times inDC-DC converters with synchronous

rectifiers, IEEE Trans. Power Electron., Vol.21, No. 4, pp. 9941002, July 2006.

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