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Timer Counter

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1. INTERRUPTS

Interrupts, thng c dch l Ngt, l mt tn hiu khn cp gi n b x l, yu cu b x l tm ngng tc khc cc hot ng hin ti nhy n mt ni khc thc hin mt nhim v khn cp no , nhim v ny gi l trnh phc v ngt isr (interrupt service routine ). Sau khi kt thc nhim v trong isr, b m chng trnh s c tr v gi tr trc b x l quay v thc hin tip cc nhim v cn dang d. => Nh vy, ngt c mc u tin x l cao nht, ngt thng c dng x l cc s kin bt ng nhng khng tn qu nhiu thi gian.

S lng ngt trn mi dng chip l khc nhau, ng vi mi ngt s c vector ngt, vector ngt l cc thanh ghi c a ch c nh c nh ngha trc nm trong phn u ca b nh chng trnh

Phn loi1. Internal Interrupt ( Ngt trong ): Cc tn hiu dn n ngt c th xut pht t cc thit b bn trong chip (ngt bo b m timer/counter trn, ngt bo qu trnh gi d liu bng RS232 kt thc) 2. External Interrupt (Ngt ngoi) l loi ngt duy nht c lp vi chip (ngt bo c 1 button c nhn, ngt bo c 1 gi d liu c nhn). -> thun tin cho giao tip gia mi trng bn ngoi vi chip. Trn chip atmega8 c 2 ngt ngoi c tn l INT0 v INT1 tng ng 2 chn s 4 (PD2) v s 5 (PD3).

Vector name ADC_vect ANA_COMP_vect EE_RDY_vect INT0_vect INT1_vect SPI_STC_vect SPM_RDY_vect TIMER0_OVF_vect TIMER1_CAPT_vect TIMER1_COMPA_vect TIMER1_COMPB_vect TIMER1_OVF_vect TIMER2_COMP_vect TIMER2_OVF_vect TWI_vect USART3_UDRE_vect

Old vector name SIG_ADC SIG_COMPARATOR SIG_EEPROM_READY SIG_INTERRUPT0 SIG_INTERRUPT1 SIG_SPI SIG_SPM_READY SIG_OVERFLOW0 SIG_INPUT_CAPTURE1

Description ADC Conversion Complete Analog Comparator EEPROM Ready External Interrupt 0 External Interrupt Request 1 Serial Transfer Complete Store Program Memory Ready Timer/Counter0 Overflow Timer/Counter Capture Event

SIG_OUTPUT_COMPARE1A Timer/Counter1 Compare Match A SIG_OUTPUT_COMPARE1B Timer/Counter1 Compare MatchB SIG_OVERFLOW1 SIG_OUTPUT_COMPARE2 SIG_OVERFLOW2 SIG_2WIRE_SERIAL SIG_USART3_DATA Timer/Counter1 Overflow Timer/Counter2 Compare Match Timer/Counter2 Overflow 2-wire Serial Interface USART3 Data register Empty

Ngt ngoi:Khi lm vic vi cc thit b ngoi vi ca AVR, hu nh chng ta ch thao tc trn cc thanh ghi chc nng c bit - SFR (Special Function Registers) trn vng nh IO, bao gm mt tp hp cc thanh ghi iu khin, trng thi, ngtkhc nhau. Vi ngt ngoi cn quan tm n 3 thanh ghi: MCUCR, GICR v GIFR

ngt ngoi

a) Thanh ghi iu khin MCU MCUCR (MCU Control Register) l thanh ghi xc lp ch ngt cho

Falling Edge Rising Edge

i vi hot ng ngt ngoi, ch quan tm n 4 bit thp. Bn bit thp l cc bit Interrupt Sense Control (ISC): +2 bit ISC11:ISC10 dng cho INT1 +2 bit ISC01:ISC00 dng cho INT0

b) Thanh ghi iu khin ngt chung GICR (General Interrupt Control Register)Ch c 2 bit cao (bit 6 v bit 7) l c s dng cho iu khin Ngt.

Bit 7 INT1 gi l bit cho php ngt 1(Interrupt Enable), set bit ny bng 1 ngha bn cho php ngt INT1 hot ng. tng t, bit INT0 iu khin ngt INT0.

c)Thanh ghi c ngt chung GIFR (General Interrupt Flag Register)

Sau khi xc lp cc bit sn sng cho cc ngt ngoi, vic sau cng chng ta cn lm l set bit I, tc bit cho php ngt ton cc, trong thanh ghi trng thi chung ca chip (thanh ghi SREG)

Cu trc ca hm ngt:

interrupt [vector_name] void vector_name_isr(void)

2. TIMER/COUNTER

I: c im: + c lp vi CPU +Tnh nng: nh th(nh ra khong thi gian, m thi gian), m s kin, ngoi ra chip AVR cn c tnh nng iu chnh to ra cc xung iu rng PWM. +Cc b Timer/Counter c chia theo rng thanh ghi cha gi tr nh thi hay gi tr m ca chng, c th trn chip Atmega8 c 2 b Timer 8 bit (Timer/Counter0 v Timer/Counter2) v 1 b 16 bit (Timer/Counter1). +Cc ch lm vic ca 3 b Timer ny cng khng ging nhau.

Timer/Counter0: l mt b nh thi, m n gin vi 8 bit. Ch hoat ng ca Timer/Counter0 coi nh 2 chc nng c bn l to ra mt khong thi gian v m s kin. Timer/Counter1: l b nh thi, m a nng 16 bit, c 5 ch hot ng chnh. Ngoi cc chc nng thng thng, Timer/Counter1 cn c dng to ra xung iu rng PWM dng cho cc mc ch iu khin. C th to 2 tn hiu PWM c lp trn cc chn OC1A (chn 15) v OC1B (chn 16) bng Timer/Counter1. Timer/Counter2: tuy l mt module 8 bit nh Timer/Counter0 nhng Timer/Counter2 c n 4 ch hot ng nh Timer/Counter1, ngoi ra n n cn c s dng nh mt module canh chnh thi gian cho cc ng dng thi gian thc (ch asynchronous). Tuy nhin Ch asynchronous ca Timer/Counter2 khng c s dng ph bin

II. S dng Timer/Counter.C mt s nh ngha quan trng trc khi s dng cc T/C trong AVR: BOTTOM: l gi tr thp nht m mt T/C c th t c, gi tr ny lun l 0. MAX: l gi tr ln nht m mt T/C c th t c, gi tr ny c quy nh bi bi gi tr ln nht m thanh ghi m ca T/C c th cha c. C th: T/C0 v T/C2 c MAX = 255, T/C1 = 65535 TOP: l gi tr m khi T/C t n n s thay i trng thi, khng nht thit phi bng MAX, TOP c th thay i bng cch iu khin cc bit iu khin tng ng hoc c th nhp trc tip thng qua mt s thanh ghi.

TIMER/COUNTER 0: 8 bits Thanh ghi: c 4 thanh ghi c thit k ring cho hot ng v iu khin T/C0, l:1. TCNT0 (Timer/Counter Register) 2. TCCR0 (Timer/Counter Control Register) 3. TIMSK (Timer/Counter Interrupt Mask Register) 4. TIFR (Timer/Counter Interrupt Flag Register)

1. TCNT0 (Timer/Counter Register): + l 1 thanh ghi 8 bit cha gi tr vn hnh ca T/C0 + Thanh ghi ny cho php c v ghi gi tr mt cch trc tip E.g: TCNT0 = 131;

2. TCCR0 (Timer/Counter Control Register):

+ l thanh ghi iu khin hot ng ca T/C0.+Tuy l thanh ghi 8 bit nhng thc cht ch c 3 bit c tc dng l CS00, CS01 v CS02 l cc bit chn ngun xung nhp cho T/C0 (Clock Select).

Bng 1: chc nng cc bit CS0X

T/C0 ch s dng bt s 0 (TOIE0) trong thanh ghi ny TOIE0 bit l bit cho php ngt khi c trn T/C0. Khi bit TOIE0=1, v bit I trong thanh ghi trng thi c set nu mt trn xy ra s dn n ngt trn.

3. TIMSK (Timer/Counter Interrupt Mask Register):

4. TFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b T/C. Trong thanh ghi ny bit s 0, TOV0 l c ch th ngt trn ca T/C0. Khi c ngt trn xy ra, bit ny t ng c set ln 1. Thng thng trong iu khin cc T/C vai tr ca thanh ghi TIFR khng qu quan trng.

Hot ng: T/C0 c kch bi mt tn hiu (signal), c mi ln xut hin tn hiu kch gi tr ca thanh ghi TCNT0 li tng thm 1 n v, thanh ghi ny tng cho n khi n t mc MAX l 255, tn hiu kch tip theo s lm thanh ghi TCNT0 tr v 0 (trn), lc ny bit c trn TOV0 s t ng c set bng 1. Tuy nhin, yu t to s khc bit chnh l tn hiu kch v ngt trn, kt hp 2 yu t ny chng ta c th to ra 1 b nh thi gian hoc 1 b m s kin.

l thanh ghi16 bits a chc nng, c th ti ra xung iu rng PWM iu khin ng c. 2 thanh ghi 8 bits (c tn kt thc bng cc k t L v H) to thnh thanh ghi 16 bits

TIMER/COUNTER 1:

T/C1 c 6 nhm thanh ghi l:

1. TCNT1 gm 2 thanh ghi 8 bits: TCNT1H v TCNT1L (Timer/Counter Register) 2. TCCR1A v TCCR1B (Timer/Counter Control Register) 3. OCR1A v OCR1B (Ouput Compare Register A v B) 4. ICR1 (InputCapture Register 1) 5. TIMSK (Timer/Counter Interrupt Mask Register) 6. TIFR (Timer/Counter Interrupt Flag Register)

1. TCNT1 gm 2 thanh ghi 8 bits: TCNT1H v TCNT1L (Timer/Counter Register) * l 2 thanh ghi 8 bit to thnh thanh ghi 16 bits (TCNT1) cha gi tr vn hnh ca T/C1. * C 2 thanh ghi ny cho php bn c v ghi gi tr mt cch trc tip.

2. TCCR1A v TCCR1B (Timer/Counter Control Register)

+ L 2 thanh ghi iu khin hot ng ca T/C1. + L 2 thanh ghi hon ton c lp. + Cc bit trong 2 thanh ghi ny bao gm cc bit chn mode hay chn dng sng (WGM), cc bit quy nh dng ng ra (COM), cc bit chn gi tr chia prescaler cho xung nhp (Clock Select CS)

Trong thanh ghi TCCR1B c 3 bit l CS10, CS11 v CS12. y l cc bit chn xung nhp cho T/C1 nh truong T/C0.

Bng 2 s tm tt cc ch xung nhp trong T/C1.

* Ouput Compare: V vic so snh lin tc gia TCNT1 vi cc thanh ghi OCR1A v OCR1B * Khi gi tr so snh bng nhau th 1 Match xy ra, khi mt ngt hoc 1 s thay i trn chn OC1A (hoc/v chn OC1B) xy ra (y l cch to PWM bi T/C1). * A v B i din cho 2 knh (channel) A v B v th m chng ta c th to 2 knh PWM bng T/C1.

3. OCR1A v OCR1B (Ouput Compare Register A v B)

4. ICR1 (InputCapture Register 1) 16 bits:Khi c 1 s kin trn chn ICP1 (chn 14 trn Atmega8) thanh ghi ICR1 s capture gi tr ca thanh ghi m TCNT1. Mt ngt c th xy ra trong trng hp ny, v th Input Capture c th c dng cp nht gi tr TOP ca T/C1.

5. TIMSK (Timer/Counter Interrupt Mask Register)TIMSK cng c dng quy nh ngt cho T/C1, nhng T/C1 ch s dng 4 bt trong TIMSK: TOIE1, OCIE1A, OCIE1B, TICIE1 C tt c 4 loi ngt trn T/C1:

TIMSK: + Bit 2 trong TIMSK l TOIE1, bit quy nh ngt trn cho thanh T/C1. + Bit 3, OCIE1B l bit cho php ngt khi c 1 Match xy ra trong vic so snh TCNT1 vi OCR1B. + Bit 4, OCIE1A l bit cho php ngt khi c 1 Match xy ra trong vic so snh TCNT1 vi OCR1A. + Bit 5, TICIE1 l bit cho php ngt trong trng hp Input Capture c dng.

6. TIFR (Timer/Counter Interrupt Flag Register)L thanh ghi c nh cho tt c cc b T/C. Cc bit t 2 n 5 trong thanh ghi ny l cc c trng thi ca T/C1.

5 mode ca T/C1

Ch PWMPWM (Pulse Width Modulation) l xung iu rng l khi nim ch tn hiu xung c chu k (Time period) c c nh, duty cycle (thi thi gian tn hiu mc HIGH) ca n c th c thay i.

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