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Test Synthesis KRZYSZTOF KUCHCINSKI DEPT. OF COMPUTER SCIENCE, LTH Outline Digital system testing Design for testability Test points Scan path Built-In Self-Test (BIST) High-level test synthesis Testability analysis Testability improvement transformations Partitioning K. Kuchcinski Test Synthesis 1 Digital system testing

TestSynthesis - Lunds tekniska högskola

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Page 1: TestSynthesis - Lunds tekniska högskola

Test SynthesisKRZYSZTOF KUCHCINSKI

DEPT. OF COMPUTER SCIENCE, LTH

Outline

Digital system testing

Design for testabilityTest pointsScan pathBuilt-In Self-Test (BIST)

High-level test synthesisTestability analysisTestability improvement transformationsPartitioning

K. Kuchcinski Test Synthesis 1

Digital system testing

Page 2: TestSynthesis - Lunds tekniska högskola

Testing activitiesExecutable Design

Specification

Verification(e.g., simualtion)

Functionally correctspecification

Synthesis(with testability)

Specification forproduction

Production

Productiontest

K. Kuchcinski Test Synthesis 2

Production Testing Activities

Correct DesignSpecification

Test PatternGeneration

TestPatterns

TestApplication

• Fault detection• Fault diagnosis

• Test pattern generation– ATPG (Automating Test Pattern generation)– BIST (Built-In Self Test)

• Testability improvements used (scan, BIST, etc.)

K. Kuchcinski Test Synthesis 3

Digital System Testing

In1

C

In2

S

Carry

x1

a1

x2

a2 o1

T1

T2

T3

• General strategy is to apply a test pattern to primary inputs and observe primaryoutputs

• Other variations of the basic technique exist, for example Iddq (Integrated CircuitQuiescent Current), BIST

• Test pattern generation is NP-complete problem

• Fault model required for systematic test generation procedure

K. Kuchcinski Test Synthesis 4

Page 3: TestSynthesis - Lunds tekniska högskola

Test Pattern Generation

In1

C

In2

S

Carry

x1

a1

x2

a2 o1

T1

T2

T3

stuck-at-0

Output correct 1Output incorrect 0

• stuck-at-0 and stuck-at-1 fault model,

• fault sensitizing- finds an input pattern that produces a value 1 (0) at the faulty linein case of stuck-at-0 (stuck-at-1) fault,

• fault propagation- find additional input patterns which will produce different values atthe primary outputs for the correct and faulty circuit.

K. Kuchcinski Test Synthesis 5

Test Pattern Generation (cont’d)

• Reconvergent fanout- different paths from the same line reconverging at the samecomponent

a1

o2

A

B

C

Outstuck-at-1

o1

K. Kuchcinski Test Synthesis 6

Design for testability

Page 4: TestSynthesis - Lunds tekniska högskola

Design for Testability

• ad hoc techniques– test points– partitioning

• structured techniques– scan path– BIST

• the main goal is to improve controllability and obesrvability of selected lines in adesign

– Controllability indicates the relative difficulty of setting a particular line to a specificvalue from primary inputs

– Observability indicates the relative difficulty of propagating a value assigned to aparticular line to a primary output

• Controllability and observability reflect the two phases of test generation, namelytest sensitizing and test propagation

K. Kuchcinski Test Synthesis 7

Test Points

a1 o1C1 C2. . .

. . .C1. . .

C2. . .

original design 0/1-injection and observation

CP0 CP1

OP

• very simple method

• large overhead in terms of lines (can be alleviated a little bit by using addressing oftest points and multiplexing observation points)

• can be used to lines (not only to registers)

K. Kuchcinski Test Synthesis 8

Scan Path

R3R2R1R0 R3R2R1R0

Combinational logic

Combinational logic Combinational logic

Combinational logic

• full scan reduces the sequential test generation problem to a combinational one• Boundary scan (IEEE Std 1149.1-1990),• Full vs. partial scan.

K. Kuchcinski Test Synthesis 9

Page 5: TestSynthesis - Lunds tekniska högskola

Scan Path

sr sr sr

Clk

SI In In In

Out Out Out

SOSC

K. Kuchcinski Test Synthesis 10

Scan Path (cont’d)

a1D

SC

SD

o1

a2

Q

QD flip-flop

K. Kuchcinski Test Synthesis 11

BIST

Combinational logic Combinational logic

PatternGenerator

Signatureanalysis

LFSR

LFSR

BISTcontrolunit

Problems:• alliasing,• random pattern resistance,• . . .

K. Kuchcinski Test Synthesis 12

Page 6: TestSynthesis - Lunds tekniska högskola

Reconfigurable 3-bit LFSR module

Q

DM

N S

x1 Q

DM

N S

x2 Q

DM

N S

x3

I1 I2 I3

N S Mode

M=1 x Normal Operation

0 0 Input Generator

0 1 Signature Analyzer

K. Kuchcinski Test Synthesis 13

Reconfigurable 3-bit LFSR module (cont’d)

Q

D

x1 Q

D

x2 Q

D

x3

I1 I2 I3

N=1: Normal operation

K. Kuchcinski Test Synthesis 14

Reconfigurable 3-bit LFSR module (cont’d)

Q

D

x1 Q

D

x2 Q

D

x3

I1 I2 I3N=O, S=1: Signature Analyzer

K. Kuchcinski Test Synthesis 15

Page 7: TestSynthesis - Lunds tekniska högskola

Reconfigurable 3-bit LFSR module (cont’d)

Q

D

x1 Q

D

x2 Q

D

x3

I1 I2 I3

N=O, S=0: Input Generator

K. Kuchcinski Test Synthesis 16

Software-based test BIST

• To reduce the hardware overhead cost in the BIST applications the hardware LFSRcan be replaced by software.

• Attractive to test SoCs, because of the availability of computing resources directly inthe system (a typical SoC usually contains at least one processor core).

• The TPG software is the same for all cores and is stored as a single copy.

• All characteristics of the LFSR are specific to each core and stored in the ROM .

• For each additional core, only the BIST characteristics for this core have to bestored.

K. Kuchcinski Test Synthesis 17

High-level test synthesis

Page 8: TestSynthesis - Lunds tekniska högskola

High-Level Test Synthesis

• Testablility analysis– testability measures– testability calculation algorithm

• Testability transformations– partial scan insertion– test points insertion– partitioning

K. Kuchcinski Test Synthesis 18

Testability measures

• Controllability and observability are assigned to lines in the design

• They have a combinational and sequential factors CC, SC, CO, SO

• CC and CO are between 0 and 1, where 1 is the best controllability/observability

• SC and SO are natural numbers representing number of clock cycles needed tocontrol/observe a line

• heuristics are developed to find components controllability transfer factor (CTF) andobservability transfer factor (OTF)

– CTF reflects the probability of setting a value at a unit’s output by randomly exercisingits inputs.

– OTF reflects the probability of observing a unit’s input by randomly exciting its otherinputs and observing its outputs.

K. Kuchcinski Test Synthesis 19

Testability measures (cont’d)

• controllability of an combinational componentCCout = CCin ∗ CTFUSCout = SCin + clk(Si)clk(Si) is the number of clock cycles needed for data operation at a functional unit.

K. Kuchcinski Test Synthesis 20

Page 9: TestSynthesis - Lunds tekniska högskola

Testability Analysis Algorithm

for all primary inputs doCCprim_in = 1;SCprim_in = 0;

doselect a next unit U;-- calculate controllability at a unit U’s outputs by-- using the average controllability calculated-- at its inputsif U is a combinational unit then

CCout = CCin ∗ CTFU;SCout = SCin + clk(Si);if U is a sequential unit then

CCout = CCin ∗ CCcond(Si ,Sj );SCout = SCin + clk(Si ,Sj);

if U is involved in a feedback loop thenCCout = CCout ∗ CCloop;SCout = SCout + SCloop;

until all primary outputs are reached;

K. Kuchcinski Test Synthesis 21

Testability Improvement Transformations

Partial scan insertion

• calculate a testability evaluation for registers as a average testability (combinationaland sequential)

• select registers which are in a data path loop; selected registers must be in differentloops,

• if the testability still does not satisfy requirements select a number of registers withthe worst testability,

• re-calculate testability measures and repeat previous phase if necessary

Test points insertion

• Insertion of T-cells on similar principles as for registers

K. Kuchcinski Test Synthesis 22

Partitioning

• The partitioned circuit works in two modes: normal and test mode,

• The main objective of data path partitioning is to use testability analysis results andother heuristics to find partitioning boundaries and isolate data communicationamong partitions in the test mode.

• The main procedure– selecting partitioning boundaries, and– identifying partitions by clustering a set of components surrounded by the partitioning

boundaries.

K. Kuchcinski Test Synthesis 23

Page 10: TestSynthesis - Lunds tekniska högskola

Partitioning (cont’d)

Selection of registers and/or lines to be boundary components:

• break feedback loops identified by the testability analysis algorithm

• select registers or lines with the worst testability

• eliminate fanout points

• BIST heuristic

K. Kuchcinski Test Synthesis 24

Partitioning example

In1 In2

R2R1

S4S3

S7

S2S1

S6

S5

S8

Out3Out2

P1

P2

Out1

preliminary partitioning further partitioning

In1 In2

R2R1

S4S3

S7

S2S1

S6

S5

S8

Out3Out2

P1c

P2

Out1

T2

T1

P1b

P1a

K. Kuchcinski Test Synthesis 25