VLSI Testing Introduction

VLSI Testing Introduction

Virendra SinghIndian Institute of Science

Bangalorevirendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 1

Jan 16, 2008 E0-286@SERC 2

Reading MaterialReading MaterialText Book:M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2005Reference Books:

1. H. Fujiwara, Logic Testing and Design for Testability, MIT Press, 1985

2. M. Abramovici, M. Breuer, and A.D. Friedman, Digital System Testing and Testable Design, Jayco Pub., 2002

3. S. Mourad and Y. Zorian, Principles of Testing Electronic Systems, John Wiley, 2000Journals:IEEE TC, TCAD, and TVLSI ACM TODAES

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AcknowledgementAcknowledgementProf. Hideo Fujiwara, NAIST, JapanProf. Kewal K. Saluja, Univ. of Wisconsin, USAProf. Michiko Inoue, NAIST, JapanProf. Vishwani D. Agrawal, Auburn Univ., USAProf. Samiha Mourad, Santa Clara Univ., USAProf. Erik Larsson, Linkoping Univ., SwedenDr. Rubin Parekhji, TI, BangaloreDr. Subir Roy, TI, Bangalore

Jan 16, 2008 E0-286@SERC 4

VLSI Realization ProcessVLSI Realization Process

Determine requirements

Write specifications

Design synthesis and Verification

Fabrication

Manufacturing test

Chips to customer

Customer’s need

Test development

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DefinitionsDefinitions

Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes.

Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function.

Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

Jan 16, 2008 E0-286@SERC 6

Verification vs. Test Verification vs. Test

VerificationVerifies correctness of design.Performed by simulation, hardware emulation, or formal methods.

Performed once prior to manufacturing.Responsible for quality of design.

TestVerifies correctness of manufactured hardware.Two-part process:1. Test generation: software

process executed once during design

2. Test application: electrical tests applied to hardware

Test application performed on every manufactured device.Responsible for quality of devices.

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Problems of Ideal TestsProblems of Ideal Tests

Ideal tests detect all defects produced in the manufacturing process.Ideal tests pass all functionally good devices.Very large numbers and varieties of possible defects need to be tested.Difficult to generate tests for some real defects. Defect-oriented testing is an open problem.

Jan 16, 2008 E0-286@SERC 8

Real TestsReal Tests

Based on analyzable fault models, which may not map on real defects.Incomplete coverage of modeled faults due to high complexity.Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss.Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level.

Jan 16, 2008 E0-286@SERC 9

Testing as Filter ProcessTesting as Filter Process

Fabricatedchips

Good chips

Defective chips

Prob(good) = y

Prob(bad) = 1- y

Prob(pass test) = high

Prob(fail test) = high

Prob(failtest) = lowProb(passtest) =

low

Mostlygoodchips

Mostlybad

chips

Testedchips

Jan 16, 2008 E0-286@SERC 10

Roles of TestingRoles of Testing

Detection: Determination whether or not the device under test (DUT) has some fault.Diagnosis: Identification of a specific fault that is present on DUT.Device characterization: Determination and correction of errors in design and/or test procedure.Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

Jan 16, 2008 E0-286@SERC 11

Costs of TestingCosts of Testing

Design for testability (DFT) Chip area overhead and yield reduction Performance overhead

Software processes of test Test generation and fault simulation Test programming and debugging

Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

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Design for Testability (DFT)Design for Testability (DFT)DFT refers to hardware design styles or added hardware that reduces test generation complexity.

Motivation: Test generation complexity increasesexponentially with the size of the circuit.

Logicblock A

Logicblock B

Primaryinputs(PI)

Primaryoutputs

(PO)

Testinput

Testoutput

Int.bus

Example: Test hardware applies tests to blocks Aand B and to internal bus; avoids test generationfor combined A and B blocks.

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Testing PrincipleTesting Principle

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ADVANTEST Model T6682 ATE

ADVANTEST Model T6682 ATE

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Cost of Manufacturing Testing

Cost of Manufacturing Testing

0.5-1.0GHz; analog instruments; 1,024 digital pins: ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation

= $0.854M + $0.085M + $0.5M = $1.439M/year

Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

Jan 16, 2008 E0-286@SERC 16

Cost Analysis GraphCost Analysis Graph

40,000

25,000

20,000

200k150k100k50k

100

50

000

Miles Driven

Fixe

d, T

otal

and

Var

iabl

eC

osts

($)

Ave

rage

Cos

t (c

ents

)

Total

cost

Fixed cost

Variable cost Average cost

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A Modern VLSI Device System-on-a-chip (SOC) A Modern VLSI Device

System-on-a-chip (SOC)

DSPcore

RAMROM

Inter-facelogic

Mixed-signalCodec

Dataterminal

Transmissionmedium