TDCB status and Firmware updates. Andrea Burato (INFN Pisa) On behalf of TDCB working group. TDAQ working group meeting 24.03.2010. Summary / Outline. Status of the TDC Board TDCB firmware funtionalities and features Firmware updates: TDC / FPGA comunication Periodic-trigger mode - PowerPoint PPT Presentation
TDCB status and Firmware updatesTDAQ working group meeting24.03.2010 Andrea Burato (INFN Pisa)On behalf of TDCB working group
Summary / OutlineStatus of the TDC BoardTDCB firmware funtionalities and featuresFirmware updates:TDC / FPGA comunicationPeriodic-trigger modeRegisters manual
Status of TDC BoardBrief reminder: New FPGA Cyclone III and new PCB with some correction and improvement Layout made at CERN on December 09 20 PCB produced and 2 board assembled for testingCost 956 all includedWorst case including T.V.A. (not present in production) and withorders of very small components volume for prototypesAfter testing some other boards can be assembled. Ask now!!
Status of TDC BoardCables for preliminary TDCB V3 testing:Two amphenol cables skewclear 34 couples high performance halogen freeNot final solution too good and too expensiveCost 230 (prototype) Started market survey: twisted-pair cable + VHDCI connector Investigation for a home-made solution (Pisa)
TDCB firmware TDC / FPGA interface Main features: TDCB-FPGA / TELL1 (PP-FPGA) interface Trigger functionality jtag TDC configuration settings data transfer from TDC to FPGA I2C comunication for slow control data transfer from FPGA to TELL1In previous test TDCB-FPGA were not used and TDCsspoke directly to TELL1 through FPGA, now it changesTDCB Firmware
TDCB firmwareTDC / FPGA interface Data transfer from TDC buffer into FPGA internal FIFO (new feature) TDC configuration via jtag
TDCB firmwareTDCB-FPGA / TELL1 (PP-FPGA) interface I2C comunication to write an read TDCB-FPGA registers data transfer from FPGA internal FIFOs to PP FIFOs (new feature)TDCB: One FIFO of 32x256 words for each TDC One read-out buffer for each FIFO PP sees the FIFO like a TDCPP-firmware remains the same
TDCB firmwareComplete read-out scheme: Possibility to make pre-processing using RAM equipped on TDCB Possibility to inject data for testing Monitoring
TDCB firmwareTrigger functionalityBefore: TDC continuously reading (triggerless mode)Now: TDC used in trigger mode with a periodic trigger from FPGA TDC sends data belonging to a changeable time window Each TDC red independently on a different bus (40 Mhz) but same trigger
Firmware UpdatesPeriodic-trigger modeTtrg range: 0.4 - 38.4 s with step of 0.4 s A periodic trigger is sent from the FPGA to TDCTDC side TDC load in readout buffer all data that match a specific time window Each data packet, send to FPGA, concerns a trigger In periodic trigger mode the time window is equal to trigger periodAll data are sending to FPGA
Firmware UpdatesPeriodic-trigger modeFPGA side Adds Time Stamp (TS) at the beginning of data packet from TDCTS ID: Time Stamp identification codeCourse count: LSB 0.4 s range from 0.4 s to100 s Transfers data into internal FPGA FIFO (one for each TDC) Adds to data packet a final word with words count
Conclusions 20 PCB ready 2 board assembled and ready for test 2 Amphenol prototype cables New firmware feature: periodic trigger modeTo do list: Test new card Measure clock jitter / time resolution Test again TDC rate limits Firmware improvementsAfter testing some other boards can be assembled. Ask now!!