Target Controller Electronics Upgrade Status P. Smith J. Leaver

Target Controller Electronics Upgrade Status

P. Smith

J. Leaver

04/19/23 Imperial College 2

Control Electronics Upgrade

• Target controller upgrade - Stage 1:

– Use existing designs for analogue circuitry

– Replace digital control circuitry with USBDAQ

– Recreate existing functionality, but with PC control interface

• Tasks:

– Prepare analogue circuitry + housing (crate)

– Design interface between USBDAQ & analogue boards

– Implement controller logic in firmware

– Write software drivers & GUI for user interaction


Analogue Circuitry

• Decided to leave existing controllers intact– If problems encountered during upgrade, have 2 fully functional

backup systems

• New set of vero boards made:– Opto-isolated inputs

– Optical & LED drivers

– 50R line drivers

– D/A converter for target position

– Optical analogue amplifiers for quadrature signals

• Required purchase of additional components (~£300)– Can recover approx. half this cost by component reuse at Stage 2

• Analogue circuits will be reviewed/improved at Stage 2 & reimplemented as PCBs


Controller Crate

• Inter-board wiring to be completed when P Smith returns from PAC

1 2 3

4 5 6 7 8 9 10 11

USBDAQ

Interface Board


Controller Crate Panels• 4 new panels required - currently being designed

• May be able to produce in-house at Sheffield

– Workshop has new CNC tool with lettering capability

• Unfortunately omitted from original expenses estimate

– Cost unsure, but should be reasonable

• Controller panel:

– Enable switch added – cannot operate system until key inserted & turned

– Other components just display status – reduced importance, as normal control/monitoring will be via USB


Interface Board

• FPGA on USBDAQ has (max) 3.3V IO

• Existing circuitry uses older technology, runs at 5V

Need active level translation

- Control (FPGA → analogue circuitry): 36 channels

- Feedback (analogue circuitry → FPGA): 10 channels

• Use custom interface board

USBDAQ Analogue Circuitry

3.3V 5V


3.3V → 5V Translation

FPGA Outputs:

3.3V

(x40)

SN74LVC16T245(x2)

SN74LVC8T245(x1)

5V

3.3V

C1

C2

R1

R2

R3

(DNF)

(DNF)

(DNF)

(DNF)

Level translators

C1, C2, R1, R2: Do not fit, but if required:

* Parallel Termination:- R2 = 50Ω- C2 = 0Ω (resistor)

* AC Termination:- R2 = 50Ω- C2 = ~120pF

* Thevenin Termination:- R1, R2 = 100Ω- C1, C2 = 0Ω (resistor)

* Split AC Thevenin Termination:- R1, R2 = 100Ω- C1, C2 = ~120pF






R3: Fit 0 Ω, but if required:

* Series Termination:- R3 = 30Ω




FPGA Inputs:

5V

(x16)74LVC244A

(x2)

3.3V

5V

C1

C2

R1

R2

R3

(DNF)

(DNF)

(DNF)

(DNF)

(VCC = 3.3V)

5V tolerant buffers(Schmitt triggeredinputs)

5V → 3.3V Translation
















Target Interface Board PCB Design

• PCB Dimensions:– 10 cm x 10 cm– 1.6 mm thick

• Layer stackup:

Layer 1 Signal

Layer 2 GND

Layer 3 Signal

Layer 4 5V

Layer 5 3.3V

Layer 6 Signal

Layer 7 GND

Layer 8 Signal




• Layer stackup:

Layer 1 Signal

Layer 2 GND

Layer 3 Signal

Layer 4 5V

Layer 5 3.3V

Layer 6 Signal

Layer 7 GND

Layer 8 Signal

3.3V → 5V

5V → 3.3V

US

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Con

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• Layer stackup:

Layer 1 Signal

Layer 2 GND

Layer 3 Signal

Layer 4 5V

Layer 5 3.3V

Layer 6 Signal

Layer 7 GND

Layer 8 Signal


Interface Board Production

• 4 boards: (Cheaper than 2!)

– PCB Manufacture: £843

– Components: £294.93

• All parts have been delivered

• PCBs pass visual inspection/short circuit tests

• Component assembly to be performed by P Smith

– Originally planned to use Cemgraft, but easier (in principle) & cheaper to do in-house

– Also, good experience for P Smith (can determine whether practical to assemble Stage 2 PCBs in-house)


Firmware & Software

• Most ‘peripheral’ logic modules written & simulated– Quadrature counter

– PWM generator

– Delay generator

– Timer for ISIS synchronisation

– USB controller (provided with USBDAQ - functionality verified)

• P Smith & J Leaver to spend 2 days at IC next week– Establish common code base

– Set out plan for implementing controller logic (& integration with existing modules)

– Determine IO mapping

• Software development ‘on hold’ until details of controller firmware are finalised


Schedule

• Original schedule:

– Stage 1 complete by mid-July

• This has slipped…

• Building new analogue boards took longer than reusing parts from old controllers

– Caused ~1 week delay

• Need to populate Interface Board & complete inter-board wiring

– Another ~1 week delay

• Limited availability of J Leaver in May (due to DAQ & Controls review) shifts software development to June (but should not affect final deadline)

• Not too worried by overall delay of a couple of weeks

– Will have a better idea how this fits into the general scheme of things when installation schedule is finalised

• In the worst case, still have both old controllers as contingency!


Schedule

Documents

Target Controller Electronics Upgrade Status P. Smith J. Leaver