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A 3.3V Second-Order Sigma-Delta Modulator forDigital Audio

. - Mohammad Yavari and amid Shoaei

Electrical & Computer Engineering Department, University of Tehran, Iran

P.O, 14395-515, Tehran, Iran

yavari@ece. utac.i r

mmvavari@yahoo.com

Abstract: This paper presents the design of a second-order Sigma-Delta modulator for digital audio.This modulator has been designed at 3.3 V power supply with oversampling ratio of 256-and simulatedin a 0.6 J..lmCMOS technology. The simulated results give SNDR of 94 dB for a 24 KHz signalbandwidth. The sampling frequency is 12.288 MHz and the Nyquist rate of the modulator is 48 KHz.

Index terms: Sigma-Delta modulation, switched capacitor circuits, operational amplifier, digital audio,non-ideality effects, comparator hystersis, non-overlapping clock generation.

1. INTRODUCTION

SIGMA-DELTA modulation is a widely used and thoroughly investigated technique for analog ~ignal intoa high frequency digital sequence [1], [2]. The basic properties of the Sigma-Delta modulators include:1) the sampling frequency is much higher than the Nyquist rate of the input signal, 2) a low resolution

quantizer is used within a feedback loop configuration, 3) the noise energy generated in the quatizer is shapedtoward higher fretIuencies. Moreover, by trading accuracy with speed, Sigma-Delta modulators allow highperformance to be achieved with a low sensitivity to analog component imperfections and without requiringcomponent trimming.

In the past decade, Q,versampled Sigma-Delta modulation has been the technology of choice for audioAJD converters. This is 9ue to in~ensitivity to component mismatch and the cost merit when using a fine-lineCMOS process. Such ADC's for performance-driven applications like professional audio are usuallyclassified as high-end and require.at least 16-b resolution. Several Sigma-Delta ADC's with 16-b and higherperformance have been previously reported [3], [4], (5], (6], [7], [8], however all operate with 5-V powersupply to take advantage of the larger signal swing or use a more complex modulator than the second-order.I.n this paper our goal is to-design'a second-order modulator for digital audio with low complexity s,tructurethat has more benefits than' the high~ order and cascade modulators for implementation. .

Section (2) presents the desig,'iing at' a Sigma-Delta modulator in system level; the effect of non-idealities is modeled and simulated in this section. In section (3) the required building blocks of the modulatoris designed. Section (4) presents the result of simulations that has been performed in circuit level withHSPICE.

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2. SYSTEM LEVEL DESiGN

A. Modulator ArchitectureFig. 1 shows the second-order sigma-delta modulator. The peak Signal-to-Noise (SNR) of an ideal nth

order Sigma-Delta modulator with oversampling ratio OSR and b-bits in the quantizer can be expressed as:

SNR peak= 3; (2b -1)(2n + l)(O:R )2n+l (1)The main problem of multi-bit Sigma-Deltamodulators is the linearityof quantizer, therefore a one-bit

quantizerhas beenconsidered.Relation (I) tells that oversamplingratio (OSR)sMuld be at least 256 for 16-bresolution. It shouldbe noted that for simplicityin the design of decimationfilters, oversampling ratio shouldbe a power of two. With considering OSR of 256 and one-bit DAC relation (I) gives SNR of 109 dB.Therefore a secondorder modulator with this oversamplingratio is suitablefor 16-b resolution.

B. Non-IdealitiesIn relation (1) the effect of the non-idealitiesis ignored. The non-idealities include clock jitter, switches

thermal noise, op-amp noise, finite dc gain, finite bandwidth, slew rate, limited swing of op-amps andcomparator hystersis [9]. With modeling each of the non~idealities,the proposed second-order modulator hasbeen simulated at behavioral level simulation [10]. These simulations give the required specifications of the-buildingblocksof the modulator, which are shown in Table 1.

In high-resolution Sigma-Delta modulators, the sampling capacitance is determined by noiserequirements due to the KT/C noise of the switches. For fully differentialmodulators, the SNR due to KT/Cnoise can be written as:

SNR = (2x or x Vref)2 x Csx OSRKTIC 2 4KT

With considering the sampling capacitance of IpF the maximum SNR due to KT/C noise is 106 dB,which is suitable for 16-bresolution. The maximumsignal to noise + distortion ratio (SNDR) that has beenobtained with this non-idealities is 102dB. . The power spectral density (PSD) of the modulator has shown inFig. 2, whereas Fig.3 shows the SNDR versus the input signal level. From this figure the dynamic range (DR)of 10ydB is Obtainedthat is suitable for 16-bresolution. .

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3. CIRCUIT LEVEL DESIGN

A. OperationalAmplifierFig. 4 shows the folded cascode fully differentialop-amp that achieves high bandwidth with capacitive

loads. The use of a PMOS differential pair eliminates the need of chopper stabilization, since the 1/f noise is30 times lower than NMOS in this process. For achievingthe 60 dB dc gain and 92 MHz bandwidth there isno need for gain enhancement and other techniques. The common mode feedback is a switched capacitorcircuit that has..shownin Fig. 5. It senses the output common mode voltage and controls the bias current ofM3 and M4, therefore sets the output common mode voltages to in1<i-supply.The simulated op-amp unitygain bandwidthis-98MHzwith a 1pF load, and the dc gain is 65 dB in the worst case. .

B. ComparatorThe second major component of the modulator is the comparator. The performance of the modulator is

relatively insensitive to comparator' offset and hystersis since the effects of these impairments are attenuatedby' the same second order noise shaping that attenuates the large quantization noise. The regenerative latchshown in Fig. 6 has been used to implement the comparator. In this latch, the cross-coupled devices MJ-M4and M7-Ms are strobed at their drains, rather than sources, to eliminate back-gating effects-and promote fasterregeneration [2].

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C. Clock GenerationThe integrators need a 2-phase non-overlapping clock (with delays) to minimize signal-dependent

charge injection errors. Fig. 7 shows the circuit that has been used for this work. The delays and non-overlaptimes are affected by the delaysin the inverterchain and theNOR gates.

D. Modulator Circuit SchematicA circuit schematic of the modulator is shown in Fig. 8. The modulator is controlled by two-phase, non-

overlapping clocks together with delayed versions of these clocks. Because of the large signal swings in thefirst integrator of the modulator, switches Sl and S2are full CMOS transmission gates and the other switchesare NMOS transistors only. In the switches Sl and S2which sample the input and the feedback references inthe first integrator, it is important to maintain a relatively constant resistance with variations in the "voltagebeing sampled in order to avoid signal dependent charge injection. This was accomplished by making thePMOS transistors in those switches 2.5 times larger than the NMOS transistors. While this does not onlyequalize the on-resistance of the two transistors, it significantly reduces the variation. Large switch sizes at theinput have the disadvantage of increased kickback into the signal source, which have difficulty absorbing thecharge.

4. SIMULATION RESULTS

The modulator of Fig. 8 has been simulated in a 0.6 flm, 3.3-V CMOS technology with HSPICE and theresult SNDR has been obtained is 94 dB. Fig. 9 shows the power spectral density for a 1.5 KHz, -3dBsinusoidal input signal, and 8192 FFT points. The power efficiency of the ADC's that has been mentioned inthe references of this paper are compared with following figure of merit and shown in Fig. 10.

FM 4KTxSNDRxf N= (3)P

where P is the total power dissipation of the converter and SNDR is expressed as a ratio rather than in dB.. /

5. CONCLUSION

In this paper a second order Sigma-Delta modulator for digital audio has been designed and simulated ina 0.6 flI1)CMOS process. It uses only a 3.3 V power supply and achieves 94 dB SNDR that is suitable for 16-

b resolution. The modulator power consu";ption is 3.5 mW.

REFRENCES

.[1] J. C. Candy and G. C. Temes, "Oversampling Delta-Sigma Data Converters," P~cataway, NJ: IEEEPress, 1992, ISBN 0-87942-285-8. . .

[2] S. R. Northworthy, R. Schreier,and G. C. Temes, "Delta-SigmaData Converters," Piscataway,NJ: IEEEPress, 1997; ISBN 0-7803:r045-4. .

[3] L. A. Williams, B. A. Wooley,"A Third-Order Sigm~-DyltaModulatorwith ExtendedDynamicRange,"JSSC, March 1994.

[4] 1.Fujimori et aI, "A 5-V Single-ChipDelta-Sigma Audio AID Converterwith 111dB DynamicRang~,"JSSC,MarchI997.. .

[5] A. L. Coban, "A I-V 1.0 mW Audio CJ.l:Modulator with 98 dB Dynamic Range," ISSCC, 1999.[6] Shahriar Rabii, B. A. Wooley, "A 1.8-V Digital-Audio Sigma-Delta Modulator in 0.8-1ID1CMOS," JSSC,

June, 1997.[7] K. Y. Leung et aI, "A 5V, 118dB CJ.l:Analog-to-Digital Converter for Widebandj)igital Audio," ISSCC,

1997.-f,

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[8] M. Dessouky et ai, "A IV ImW Digital-Audio~I Modulator with 88dB Dynamic Range using LocalSwitchBootstrapping," Custom integratedcircuits conference,2000.

[9] B. E. Boser, B. A. Wooley, " The Design of Sigma-Delta Modulation Analog to Digital Converters,"JSSC, Dec. 1988.

[10]S. Brigatiet ai, " Modeling Sigma-DeltaModulatorNon-idealities in SIMULINK,"ISCAS, 1999.

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