Switch FabricSwitch Fabric

Team MembersXuan BaoJacob Cox

Bryan FlemingWenzhong Wu

20 February 2009

Switch Fabric Receive Handle

Block Diagram

Switch Fabric Receive Handle

InterfaceInterfaces to Receiver Interface:Output:Data_Read: out std_logic; --read enable signal to Rcv FIFO, handshakeLength_Read: out std_logic; -- read enable signal to Rcv length FIFOPacket_Finished: out std_logic; handshake--packet end signalPacket_ Error: out std_logic; --packet error signalInput:Data: in std_logic_vector(7 downto 0); --data busPacket_Length: in std_logic_vector(11 downto 0); --packet length bus and validsignalbusConnection_Ready: in std_logic_vector;--input handshakeCheck_Counter: in std_logic_vector(11 downto 0);--Rcv’s counter value, for protecting from counter errorInput_Port_Number: in std_logic_vector(1 downto 0);

Interfaces to Data FIFO:Output:Data_Output: out std_logic_vector(7 downto 0);--prepare data for transmit side

Switch Fabric Receive Handle

Interface

Data_wrreq: out std_logic;--write enable to data FIFOInput:FIFO_Empty: in std_logic; --1 port in from FIFO Interfaces to Address FIFO:Output:Address: out std_logic_vector(7 downto 0);--output to address FIFOAddress_InputPortNumber: out std_logic_vector(1 downto 0);--expose input port number to address lookupAddress_wrreq: out std_logic--write enable to address FIFOInput:Address_FIFO_Empty: in std_logic;

Interfaces to Length FIFOOutput: Packet_Length_Output: out std_logic_vector(10 downto 0); --expose length information to transmitter handleLength Wrreq: out std_logic;

Switch Fabric Receive Handle8

Function

Switch Fabric Receive Handle8

State Machine

Switch Fabric Receive Handle8

Simulation Results

Switch Fabric Transmit Interface

11..012

8

3

SF_fifo2xmt_interface

ODL_empty[2]

ODL_empty[1]

ODL_empty[0]

Clkxmt_dwtreq

xmt_lwtreq

i_O_FIFO

rd_D_FIFO i_O_FIFO i_L_FIFO

xmt_wordsused

i_D_FIFO o_D_xmt

i_L_FIFO o_L_xmt

reset

T R A NS M I T P O R TS

12

8

Xmt Interface to Xmt

SF_fifo2xmt_interface

ODL_empty[2]

ODL_empty[1]

ODL_empty[0]

Clkxmt_dwtreq

xmt_lwtreq

i_O_FIFO

rd_D_FIFO i_O_FIFO i_L_FIFO

xmt_wordsused

i_D_FIFO o_D_xmt

i_L_FIFO o_L_xmt

reset

XMT Data Fifo(0)

XMT Length Fifo(0)

XMT Length Fifo(1)

XMT Length Fifo(2)

XMT Length Fifo(3)

XMT Data Fifo(3)

XMT Data Fifo(2)

XMT Data Fifo(1)

12

8

Switch Fabric Transmit Interface

Data Write Request

Drop Packets

Final Data Packet Write Length

SF_ODLFifo_XmtInterface_Xmt0to3SF_ODLFifo_XmtInterface_Xmt0to3

Data Enters Data_FIFO

1000 0010

Write Requests to the Transmit FIFOs

Number of words already in the Transmit FIFO

SF_fifo2xmt_interface

Clkxmt_dwtreq

xmt_lwtreq

i_O_FIFO

xmt_wordsused

i_D_FIFO o_D_xmt

i_L_FIFO

o_L_xmt

reset

rd_D_FIFO

rd_O_FIFO

rd_L_FIFO

SF_FIFO_monitor

ODL_empty[2..0]

Clk xfer_D_req

Send_L

i_O_FIFO

o_read_D o_read_L

i_L_FIFO

xfer_L_req

reset

o_read_O

o_L_FIFO

8

CounterC

i_count [11-0]Clk

o_Snd_L

i_read_L

reseto_count[11-0]

ODL_empty[2]

ODL_empty[1]

ODL_empty[0]

12

&

xmt_port_monitor

Clk

reset

SF_PacketCom

ing

xmt_wordsused12

SF_PacketLength

SF_PacketFinished

SF_dwtreq

SF_lwtreq

xmt_lw

treq

xmt_dw

treq

counter_fifo_monitor_merger

SF_fifo2xmt_interface

Merger of FIFO_Monitor, Counter, and Port_Monitors results in successful initiation, countdown, and termination of data transfer.

Fifo Empty Signals

CounterC

o_count[11-0]

i_count [11-0]

“x000”

Clk

o_Snd_L

s_snd_L <= '0‘s_en <=’0’

reset = ‘0'

i_read_L = ‘1‘ & reset =‘0’

F

s_snd_L <= '0‘s_en <=’1’

T

T

F

s_count =i_count- 1 & reset =‘0’

T

s_snd_L <= ‘1‘s_en <=’1’

s_count = i_count

s_count [11-0]

F

s_snd_L

reset

s_en

i_read_L

SF_FIFO_monitorSF_FIFO_monitor

ODL_FIFO = “000”

Send_L = ‘1’

s_i_O_FIFO = “000 to 111”

reset = ‘1’

Idle

ODL_FIFO =0000

Reset =0

F

T

T

F

Get_Length

F Reset =0

T

Send_Data

F Reset =0

T

NS_FIFO<=0000NS_length<=x0000s_o_read_L<=0s_o_read_O<=0o_read_D<=0xfer_D_req<=0000xfer_L_req<=0000

Get_LengthIdle

NS_FIFO<=i_O_FIFONS_length<=i_L_FIFOs_o_read_L<=1s_o_read_O<=1o_read_D<=0xfer_D_req<=0000xfer_L_req<=0000

Send_L =0F T

s_o_read_L<=1s_o_read_O<=1o_read_D<=0

Send_Data

xfer_D_req<=0001xfer__L_req<=0001

xfer_D_req<=1110xfer_L_req<=1110

xfer_D_req<=0010xfer_L_req<=0010

xfer_D_req<=0100xfer_L_req<=0100

xfer_D_req<=1000xfer_L_req<=1000

xfer_D_req<=1101xfer_L_req<=1101

xfer_D_req<=1110xfer_L_req<=1110

xfer_D_req<=1011xfer_L_req<=1011

xfer_D_req<=0000xfer_L_req<=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=0000

CS_FIFO=other

ASM of FIFO_Monitor FSM

SF_FIFO_monitor

Read Signals Asserted for Output and Length FIFOs

Read Signal Asserted for Data FIFO on the next clock

Write signals asserted for Transmitters

All FIFOs have Data = 0

Send Length indicates a count is complete

counter_fifo_monitor_mergercounter_fifo_monitor_merger

Switch Fabric Transmit Interface

Write Signals Asserted two clocks after all FIFOs have data

Output DestinationPacket LengthFifo Empty Signals

Fifo Read Signals

Length

Write Signals Terminate