Stereo, 24-Bit, 192 kHz, Multibit DAC AD1853€¦ · REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed

REV. AInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

aAD1853

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1999

Stereo, 24-Bit, 192 kHz, Multibit DAC

FEATURES

5 V Stereo Audio DAC System

Accepts 16-/18-/20-/24-Bit Data

Supports 24 Bits and 192 kHz Sample Rate

Accepts a Wide Range of Sample Rates Including:

32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz

Multibit Sigma-Delta Modulator with “Perfect Differential

Linearity Restoration” for Reduced Idle Tones and

Noise Floor

Data Directed Scrambling DAC—Least Sensitive to Jitter

Differential Output for Optimum Performance

120 dB Signal to Noise (Not Muted) at 48 kHz

(A-Weighted Mono)

117 dB Signal to Noise (Not Muted) at 48 kHz

(A-Weighted Stereo)

119 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Mono)

116 dB Dynamic Range (Not Muted) at 48 kHz Sample

Rate (A-Weighted Stereo)

–107 dB THD+N (Mono Application Circuit, See Figure 30)

–104 dB THD+N (Stereo)

115 dB Stopband Attenuation (96 kHz)

On-Chip Clickless Volume Control

Hardware and Software Controllable Clickless Mute

Serial (SPI) Control for: Serial Mode, Number of Bits,

Interpolation Factor, Volume, Mute, De-Emphasis, Reset

Digital De-Emphasis Processing for 32, 44.1 and 48 kHz

Sample Rates

Clock Auto-Divide Circuit Supports Five Master-Clock

Frequencies

Flexible Serial Data Port with Right-Justified, Left-

Justified, I2S-Compatible and DSP Serial Port Modes

28-Lead SSOP Plastic Package

PRODUCT OVERVIEWThe AD1853 is a complete high performance single-chip stereodigital audio playback system. It is comprised of a high per-formance digital interpolation filter, a multibit sigma-deltamodulator, and a continuous-time current-out analog DACsection. Other features include an on-chip clickless stereo at-tenuator and mute capability, programmed through an SPI-compatible serial control port. The AD1853 is fully compatiblewith all known DVD formats and supports 48 kHz, 96 kHz and192 kHz sample rates with up to 24 bits word lengths. It alsoprovides the “Redbook” standard 50 µs/15 µs digital de-emphasisfilters at sample rates of 32 kHz, 44.1 kHz and 48 kHz.

The AD1853 has a very flexible serial data input port thatallows for glueless interconnection to a variety of ADCs, DSPchips, AES/EBU receivers and sample rate converters. TheAD1853 can be configured in left-justified, I2S, right-justified,or DSP serial port compatible modes. The AD1853 acceptsserial audio data in MSB first, twos complement format.

The AD1853 operates from a single +5 V power supply. It isfabricated on a single monolithic integrated circuit and is housed ina 28-lead SSOP package for operation over the temperaturerange 0°C to +70°C.

FUNCTIONAL BLOCK DIAGRAM

SERIALDATA

INTERFACE

8 FSINTERPOLATOR

SERIAL CONTROLINTERFACE

AUTO-CLOCKDIVIDE CIRCUIT

VOLUMEMUTE

CONTROL DATAINPUT

3 2

DIGITALSUPPLY

CLOCKIN

ANALOGOUTPUTS

22

ZEROFLAG

ANALOGSUPPLY

DE-EMPHASISMUTERESET

2SERIALMODE

DIGITALDATA INPUT

AD1853

MULTIBIT SIGMA-DELTA MODULATOR

ATTEN/MUTE

IDACMULTIBIT SIGMA-DELTA MODULATOR

8 FSINTERPOLATOR

ATTEN/MUTE

VOLTAGEREFERENCE

IDAC

INT2 INT4

APPLICATIONS

Hi End: DVD, CD, Home Theater Systems, Automotive

Audio Systems, Sampling Musical Keyboards, Digital

Mixing Consoles, Digital Audio Effects Processors

REV. A–2–

AD1853–SPECIFICATIONSTEST CONDITIONS UNLESS OTHERWISE NOTEDSupply Voltages (AVDD, DVDD) +5.0 VAmbient Temperature +25°CInput Clock 24.576 MHz (512 × FS Mode)Input Signal 996.094 kHz

–0.5 dB Full ScaleInput Sample Rate 48 kHzMeasurement Bandwidth 20 Hz to 20 kHzWord Width 20 BitsInput Voltage HI 3.5 VInput Voltage LO 0.8 V

ANALOG PERFORMANCE (See Figures)

Min Typ Max Units

Resolution 24 BitsSignal-to-Noise Ratio (20 Hz to 20 kHz)

No Filter (Stereo) 114 dBNo Filter (Mono—See Figure 30) 117 dBWith A-Weighted Filter (Stereo) 117 dBWith A-Weighted Filter (Mono—See Figure 30) 120 dB

Dynamic Range (20 Hz to 20 kHz, –60 dB Input)No Filter (Stereo) 107.5 113 dBNo Filter (Mono—See Figure 30) 116 dBWith A-Weighted Filter (Stereo) 110 116 dBWith A-Weighted Filter (Mono—See Figure 30) 119 dB

Total Harmonic Distortion + Noise (Stereo) –94 –104 dB0.00063 %

Total Harmonic Distortion + Noise (Mono—See Figure 30) –107 dB0.00045 %

Analog OutputsDifferential Output Range (±Full Scale w/1 mA into IREF) 3.0 mA p-pOutput Capacitance at Each Output Pin 30 pFOut-of-Band Energy (0.5 × FS to 75 kHz) –90 dB

CMOUT 2.75 VDC Accuracy

Gain Error ±3.0 %Interchannel Gain Mismatch –0.15 0.01 +0.15 dBGain Drift 25 ppm/°C

Interchannel Crosstalk (EIAJ Method) –125 dBInterchannel Phase Deviation ±0.1 DegreesMute Attenuation –100 dBDe-Emphasis Gain Error ±0.1 dB

NOTESSingle-ended current output range: 1 mA ± 0.75 mA.

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).Specifications subject to change without notice.

DIGITAL I/O (+25C–AVDD, DVDD = +5.0 V 10%)

Min Typ Max Units

Input Voltage HI (VIH) 2.4 VInput Voltage LO (VIL) 0.8 VInput Leakage (IIH @ VIH = 3.5 V) 10 µAInput Leakage (IIL @ VIL = 0.8 V) 10 µAInput Capacitance 20 pFOutput Voltage HI (VOH) DVDD–0.5 DVDD–0.4 VOutput Voltage LO (VOL) 0.2 0.5 V

Specifications subject to change without notice.

REV. A –3–

AD1853POWER

Min Typ Max Units

SuppliesVoltage, Analog and Digital 4.5 5 5.5 VAnalog Current 12 15 mADigital Current 28 33 mA

DissipationOperation—Both Supplies 200 mWOperation—Analog Supply 60 mWOperation—Digital Supply 140 mW

Power Supply Rejection Ratio1 kHz 300 mV p-p Signal at Analog Supply Pins –77 dB20 kHz 300 mV p-p Signal at Analog Supply Pins –72 dB


TEMPERATURE RANGE

Min Typ Max Units

Specifications Guaranteed 25 °CFunctionality Guaranteed 0 70 °CStorage –55 125 °C


DIGITAL FILTER CHARACTERISTICS

Sample Rate (kHz) Passband (kHz) Stopband (kHz) Stopband Attenuation (dB) Passband Ripple (dB)

44.1 DC–20 24.1–328.7 110 ±0.000248 DC–21.8 26.23–358.28 110 ±0.000296 DC–39.95 56.9–327.65 115 ±0.0005192 DC–87.2 117–327.65 95 +0/–0.04 (DC–21.8 kHz)

+0/–0.5 (DC–65.4 kHz)+0/–1.5 (DC–87.2 kHz)


GROUP DELAY

Chip Mode Group Delay Calculation FS Group Delay Units

INT8x Mode 5553/(128 × FS) 48 kHz 903.8 µsINT4x Mode 5601/(64 × FS) 96 kHz 911.6 µsINT2x Mode 5659/(32 × FS) 192 kHz 921 µs


DIGITAL TIMING (Guaranteed Over 0C to +70C, AVDD = DVDD = +5.0 V 10%)

Min Units

tDMP MCLK Period (With FMCLK = 256 × FLRCLK)* 54 nstDML MCLK LO Pulsewidth (All Modes) 0.4 × tDMP nstDMH MCLK HI Pulsewidth (All Modes) 0.4 × tDMP nstDBH BCLK HI Pulsewidth 20 nstDBL BCLK LO Pulsewidth 20 nstDBP BCLK Period 140 nstDLS LRCLK Setup 20 nstDLH LRCLK Hold (DSP Serial Port Mode Only) 5 nstDDS SDATA Setup 5 nst

DDHSDATA Hold 10 ns

tPDRP

PD/RST LO Pulsewidth 5 ns

*Higher MCLK frequencies are allowable when using the on-chip Master Clock Auto-Divide feature.


REV. A

AD1853

–4–

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection.Although the AD1853 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges. Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Min Max Units

DVDD to DGND –0.3 6 VAVDD to AGND –0.3 6 VDigital Inputs DGND – 0.3 DVDD + 0.3 VAnalog Outputs AGND – 0.3 AVDD + 0.3 VAGND to DGND –0.3 0.3 VReference Voltage (AVDD + 0.3)/2Soldering +300 °C

10 sec

*Stresses greater than those listed under Absolute Maximum Ratings may causepermanent damage to the device. This is a stress rating only; functional operationof the device at these or any other conditions above those indicated in theoperational section of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min Typ Max Units

θJA (Thermal Resistance[Junction-to-Ambient]) 109 °C/W

θJC (Thermal Resistance[Junction-to-Case]) 39 °C/W

ORDERING GUIDE

Model Temperature Package Description Package Options

AD1853JRS 0°C to +70°C 28-Lead Shrink Small Outline RS-28AD1853JRSRL 0°C to +70°C 28-Lead Shrink Small Outline RS-28 on 13" Reels

PIN CONFIGURATION

TOP VIEW(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD1853

FILTR

OUTL–

OUTL+

AGND

IREF

DEEMP

ZEROR

DGND

MCLK

CLATCH

CCLK

INT2

INT4

CDATA

FCR

OUTR–

OUTR+

AVDD

FILTB

IDPM1

IDPM0

DVDD

SDATA

BCLK

L/RCLK

ZEROL

MUTE

RST

REV. A

AD1853

–5–

PIN FUNCTION DESCRIPTIONS

Pin Input/Output Pin Name Description

1 I DGND Digital Ground.2 I MCLK Master Clock Input. Connect to an external clock source. See Table II for allowable

frequencies.3 I CLATCH Latch input for control data. This input is rising-edge sensitive.4 I CCLK Control clock input for control data. Control input data must be valid on the rising edge

of CCLK. CCLK may be continuous or gated.5 I CDATA Serial control input, MSB first, containing 16 bits of unsigned data. Used for specifying

control information and channel-specific attenuation.6 I INT4× Assert HI to select interpolation ratio of 4×, for use with double-speed inputs (88 kHz or

96 kHz). Assert LO to select 8× interpolation ratio.7 I INT2× Assert HI to select interpolation ratio of 2×, for quad-speed inputs (176 kHz or 192 kHz).

Assert LO to select 8× interpolation ratio.8 O ZEROR Right Channel Zero Flag Output. This pin goes HI when Right Channel has no signal

input for more than 1024 LR Clock Cycles.9 I DEEMP De-Emphasis. Digital de-emphasis is enabled when this input signal is HI. This is used to

impose a 50 µs/15 µs response characteristic on the output audio spectrum at an assumed44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected viaSPI control register.

10 I IREF Connection point for external bias resistor. Voltage held at VREF.11 I AGND Analog Ground.12 O OUTL+ Left Channel Positive line level analog output.13 O OUTL– Left Channel Negative line level analog output.14 O FILTR Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage refer-

ence with parallel 10 µF and 0.1 µF capacitors to the AGND (Pin 11).15 I FCR Filter cap return pin for cap connected to FILTB (Pin 19).16 O OUTR– Right Channel Negative line level analog output.17 O OUTR+ Right Channel Positive line level analog output.18 I AVDD Analog Power Supply. Connect to analog +5 V supply.19 O FILTB Filter Capacitor connection, connect 10 µF capacitor to FCR (Pin 15).20 I IDPM1 Input serial data port mode control one. With IDPM0, defines one of four serial modes.21 I IDPM0 Input serial data port mode control zero. With IDPM1, defines one of four serial modes.22 O ZEROL Left Channel Zero Flag output. This pin goes HI when Left Channel has no signal input

for more than 1024 LR Clock Cycles.23 I MUTE Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal operation.24 I RST Reset. The AD1853 is placed in a reset state when this pin is held LO. The AD1853 is

reset on the rising edge of this signal. The serial control port registers are reset to thedefault values. Connect HI for normal operation.

25 I L/RCLK Left/Right clock input for input data. Must run continuously.26 I BCLK Bit clock input for input data.27 I SDATA Serial input, MSB first, containing two channels of 16/18/20/24 bit twos-complement

data.28 I DVDD Digital Power Supply Connect to digital +5 V supply.

REV. A

AD1853

–6–

SDATAINPUT

LSBMSB–2MSB–1 LSB+2 LSB+1 MSB–2MSB–1MSB LSB+2 LSB+1 LSB

BCLKINPUT

L/RCLKINPUT

LEFT CHANNEL RIGHT CHANNEL

MSBLSB

Figure 1. Right-Justified Mode


MSB–2MSB–1 LSB+2 LSB+1 LSB MSB–2MSB–1MSB LSB+2 LSB+1 LSB MSB

L/RCLKINPUT

BCLKINPUT

SDATAINPUT

MSB

Figure 2. I2S-Justified Mode

MSB–2MSB–1 LSB+2 LSB+1 LSB MSB–2MSB–1MSB LSB+2 LSB+1 LSB MSB–1MSB

L/RCLKINPUT

BCLKINPUT

SDATAINPUT


MSB

Figure 3. Left-Justified Mode

SDATAINPUT

MSB–1 LSB+2 LSB+1 LSB MSB–1 LSB+2 LSB+1 LSBMSB MSB–1MSB

L/RCLKINPUT LEFT CHANNEL RIGHT CHANNEL

BCLKINPUT

MSB

Figure 4. Left-Justified DSP Mode

L/RCLKINPUT LEFT CHANNEL RIGHT CHANNEL

BCLKINPUT

SDATAINPUT

LSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1 MSB–2 LSB+2 LSB+1 LSB MSB MSB–1MSB

Figure 5. 32 × FS Packed Mode

REV. A

AD1853

–7–

OPERATING FEATURESSerial Data Input PortThe AD1853’s flexible serial data input port accepts data intwos-complement, MSB-first format. The left channel data fieldalways precedes the right channel data field. The serial mode isset by using either the external mode pins (IDPM0 Pin 21 andIDPM1 Pin 20) or the mode select bits (Bits 4 and 5) in the SPIcontrol register. To control the serial mode using the externalmode pins, the SPI mode select bits should be set to zero(default at power-up). To control the serial mode using the SPImode select bits, the external mode control pins should begrounded.

In all modes except for the right-justified mode, the serial portwill accept an arbitrary number of bits up to a limit of 24 (extrabits will not cause an error, but they will be truncated inter-nally). In the right-justified mode, control register Bits 8 and 9are used to set the word length to 16, 20, or 24 bits. The defaulton power-up is 24-bit mode. When the SPI Control Port is notbeing used, the SPI pins (3, 4 and 5) should be tied LO.

Serial Data Input ModeThe AD1853 uses two multiplexed input pins to control themode configuration of the input data port mode.

Table I. Serial Data Input Modes

IDPM1 IDPM0(Pin 20) (Pin 21) Serial Data Input Format

0 0 Right Justified (24 Bits) Default0 1 I2S-Compatible1 0 Left Justified1 1 DSP

Figure 1 shows the right-justified mode. LRCLK is HI for theleft channel, LO for the right channel. Data is valid on the risingedge of BCLK.

In normal operation, there are 64-bit clocks per frame (or 32per half-frame). When the SPI word length control bits (Bits 8and 9 in the control register) are set to 24 bits (0:0), the serialport will begin to accept data starting at the 8th bit clock pulseafter the L/RCLK transition. When the word length control bitsare set to 20-bit mode, data is accepted starting at the 12th bitclock position. In 16-bit mode, data is accepted starting at the16th-bit clock position. These delays are independent of thenumber of bit clocks per frame, and therefore other data formatsare possible using the delay values described above. For detailedtiming, see Figure 6.

Figure 2 shows the I2S mode. L/RCLK is LO for the left chan-nel, and HI for the right channel. Data is valid on the risingedge of BCLK. The MSB is left-justified to an L/RCLK transi-tion but with a single BCLK period delay. The I2S mode can beused to accept any number of bits up to 24.

Figure 3 shows the left-justified mode. L/RCLK is HI for theleft channel, and LO for the right channel. Data is valid on therising edge of BCLK. The MSB is left-justified to an L/RCLKtransition, with no MSB delay. The left-justified mode canaccept any word length up to 24 bits.

Figure 4 shows the DSP serial port mode. L/RCLK must pulseHI for at least one bit clock period before the MSB of the leftchannel is valid, and L/RCLK must pulse HI again for at leastone bit clock period before the MSB of the right channel isvalid. Data is valid on the falling edge of BCLK. The DSP serialport mode can be used with any word length up to 24 bits.

tDLS

BCLK

L/RCLK

SDATALEFT-JUSTIFIED

MODE

SDATARIGHT-JUSTIFIED

MODELSB

SDATAI2S-JUSTIFIED

MODE

tDBH tDBP

tDBL

tDDS

MSB MSB-1

tDDH

tDDS

MSB

tDDH

tDDS tDDS

tDDH tDDH

MSB

8-BIT CLOCKS(24-BIT DATA)



Figure 6. Serial Data Port Timing

REV. A

AD1853

–8–

In this mode, it is the responsibility of the DSP to ensure thatthe left data is transmitted with the first LRCLK pulse, and thatsynchronism is maintained from that point forward.

Note that the AD1853 is capable of a 32 × FS BCLK frequency“packed mode” where the MSB is left-justified to an L/RCLKtransition, and the LSB is right-justified to the opposite L/RCLKtransition. L/RCLK is HI for the left channel, and LO for theright channel. Data is valid on the rising edge of BCLK. Packedmode can be used when the AD1853 is programmed in right-justified or left-justified mode. Packed mode is shown is Figure 5.

Master Clock Auto-Divide FeatureThe AD1853 has a circuit that autodetects the relationshipbetween master clock and the incoming serial data, and inter-nally sets the correct divide ratio to run the interpolator andmodulator. The allowable frequencies for each mode are shownabove.

Serial Control PortThe AD1853 serial control port is SPI-compatible. SPI (SerialPeripheral Interface) is an industry standard serial port protocol.The write-only serial control port gives the user access to: selectinput mode, soft reset, soft de-emphasis, channel specific at-tenuation and mute (both channels at once). The SPI port is a3-wire interface with serial data (CDATA), serial bit clock(CCLK), and data latch (CLATCH). The data is clockedinto an internal shift register on the rising edge of CCLK.The serial data should change on the falling edge of CCLK andbe stable on the rising edge of CCLK. The rising edge of

CLATCH is used internally to latch the parallel data from theserial-to-parallel converter. This rising edge should be alignedwith the falling edge of the last CCLK pulse in the 16-bit frame.The CCLK can run continuously between transactions.

The serial control data is 16-bit MSB first, and is unsigned. Bits0 and 1 are used to select 1 of 3 registers (control, volume left,and volume right). The remaining 14 bits (bits 15:2) are used tocarry the data for the selected register. If a volume register isselected, then the upper 14 bits are used to multiply the digitalinput signal by the control word, which is interpreted as anunsigned number (for example, 11111111111111 is 0 dB, and01111111111111 is –6 dB, etc.). The default volume controlwords on power-up are all 1s (0 dB). The control register onlyuses bits 11:2 to carry data; the upper bits (15:12) should al-ways be written with zeroes, as several test modes are decodedfrom these upper bits. The control register defaults on power-upto 8× interpolation mode, 24-bit right-justified serial mode,unmuted, and no de-emphasis filter. The intent with these resetdefaults is to enable AD1853 applications without requiring theuse of the serial control port. For those users that do not use theserial control port, it is still possible to mute the AD1853 outputby using the MUTE pin (Pin 23) signal.

Note that the serial control port timing is asynchronous to theserial data port timing. Changes made to the attenuator levelwill be updated on the next edge of the LRCLK after CLATCHwrite pulse as shown in Figure 6.

Table II.

Nominal Input Internal Sigma-DeltaChip Mode Allowable Master Clock Frequencies Sample Rate Clock Rate

INT8× Mode 256 × FS, 384 × FS, 512 × FS, 768 × FS, 1024 × FS 48 kHz 128 × FS



D15 D14 D0

tCHD

tCCH

tCSUtCCL tCLL

tCLH

CDATA

CCLK

CLATCH

Figure 7. Serial Control Port Timing

REV. A

AD1853

–9–

Table III. Digital Timing

Min Units

tCCH CCLK HI Pulsewidth 40 nstCCL CCLK LOW Pulsewidth 40 nstCSU CDATA Setup Time 10 nstCHD CDATA Hold Time 10 nstCLL CLATCH LOW Pulsewidth 10 nstCLH CLATCH HI Pulsewidth 10 ns

SPI REGISTER DEFINITIONSThe SPI port allows flexible control of many chip parameters.It is organized around three registers; a LEFT-CHANNELVOLUME register, a RIGHT-CHANNEL VOLUME registerand a CONTROL register. Each WRITE operation to theAD1853 SPI control port requires 16 bits of serial data inMSB-first format. The bottom two bits are used to select oneof three registers, and the top 14 bits are then written to thatregister. This allows a write to one of the three registers in asingle 16-bit transaction.

The SPI CCLK signal is used to clock in the data. The incom-ing data should change on the falling edge of this signal. At theend of the 16 CCLK periods, the CLATCH signal should riseto latch the data internally into the AD1853.

Register AddressesThe lowest two bits of the 16-bit input word are decoded asfollows to set the register into which the upper 14 bits will bewritten.

Bit 1 Bit 0 Register

0 0 Volume Left1 0 Volume Right0 1 Control Register

VOLUME LEFT and VOLUME RIGHT RegistersA write operation to the left or right volume registers will acti-vate the “auto-ramp” clickless volume control feature of theAD1853. This feature works as follows. The upper 10 bits ofthe volume control word will be incremented or decremented by1 at a rate equal to the input sample rate. The bottom 4 bits arenot fed into the auto-ramp circuit and thus take effect immedi-ately. This arrangement gives a worst-case ramp time of about1024/FS for step changes of more than 60 dB, which has beendetermined by listening tests to be optimal in terms of pre-venting the perception of a “click” sound on large volumechanges. See Figure 8 for a graphical description of how thevolume changes as a function of time.

The 14-bit volume control word is used to multiply the signal,and therefore the control characteristic is linear, not dB. A con-stant dB/step characteristic can be obtained by using a lookuptable in the microprocessor that is writing to the SPI port.

20ms TIME

–60

–60

0

0

LE

VE

L –

dB

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 8. Smooth Volume Control

REV. A

AD1853

–10–

Control RegisterThe following table shows the functions of the control register. The control register is addressed by having a “01” in the bottom 2 bitsof the 16-bit SPI word. The top 14 bits are then used for the control register.

Bit 11 Bit 10 Bit 9:8 Bit 7 Bit 6 Bit 5:4 Bit 3:2

INT2× Mode INT4× Mode Number of Soft Reset. Soft Mute OR’d Serial Mode OR’d De-Emphasis FilterOR’d with Pin. OR’d with Pin. Bits in Right- Default = 0 with Pin. with Mode Pins. Select.Default = 0 Default = 0 Justified Serial Default = 0 IDPMI:IDPM0 0:0 No Filter

Mode. 0:0 Right-Justified 0:1 44.1 kHz Filter0:0 = 24 0:1 I2S 1:0 32 kHz Filter0:1 = 20 1:0 Left-Justified 1:1 48 kHz Filter1:0 = 16 1:1 DSP Mode Default = 0.0Default = 0:0 Default = 0:0

MuteThe AD1853 offers two methods of muting the analog output.By asserting the MUTE (Pin 23) signal HI, both the left andright channel are muted. As an alternative, the user can assertthe mute bit in the serial control register (Bit 6) HI. The AD1853has been designed to minimize pops and clicks when mutingand unmuting the device by automatically “ramping” the gainup or down. When the device is unmuted, the volume returns tothe value set in the volume register.

Analog AttenuationThe AD1853 also offers the choice of using IREF (Pin 10) toattenuate by up to 50 dB in the analog domain. This feature canbe used as an analog volume control. It is also a convenientplace to add a compressor/limiter gain control signal.

Output Drive, Buffering and LoadingThe AD1853 analog output stage is able to drive a 1 kΩ (inseries with 2 nF) load. The analog outputs are usually accoupled with a 10 µF capacitor.

De-EmphasisThe AD1853 has a built-in de-emphasis filter that can be usedto decode CDs that have been encoded with the standard“Redbook” 50 µs/15 µs emphasis response curve. Three curvesare available; one each for 32 kHz, 44.1 kHz and 48 kHz sam-pling rates. The external “DEEMP” pin (Pin 9) turns on the44.1 kHz de-emphasis filter. The other filters may be selectedby writing to control Bits 2 and 3 in the control register. If theSPI port is used to control the de-emphasis filter, the externalDEEMP pin should be tied LO.

Control SignalsThe IDPM0 and IDPM1 control inputs are normally con-nected HI or LO to establish the operating state of the AD1853.They can be changed dynamically (and asynchronously toLRCLK and the master clock), but it is possible that a clickor pop sound may result during the transition from one serialmode to another. If possible, the AD1853 should be placed inmute before such a change is made.

Figures 9–14 show the calculated frequency response of thedigital interpolation filters. Figures 15–27 show the performanceof the AD1853 as measured by an Audio Precision System 2Cascade. For the wideband plots, the noise floor shown in the

plots is higher than the actual noise floor of the AD1853. This iscaused by the higher noise floor of the “High Bandwidth” ADCused in the Audio Precision measurement system. The two-tonetest shown in Figure 18 is per the SMPTE standard for measur-ing Intermodulation Distortion.

FREQUENCY – kHz

0.001

0

dB

2 10 12 14 16 20

0.0008

0.0006

0.0004

0.0002

0

–0.0002

–0.0004

–0.0006

–0.0008

–0.0014 6 8 18

Figure 9. Passband Response 8× Mode, 48 kHz SampleRate

FREQUENCY – kHz

0

AT

TE

NU

AT

ION

– d

B

–60

–100

–160

–20

–40

–80

–120

–140

0 150 20050 100 250 300 350

Figure 10. Complete Response, 8× Mode, 48 kHzSample Rate

REV. A

AD1853

–11–

Typical Performance Characteristics–

FREQUENCY – kHz

0.5

–10

dB

5 10 15 20 25 30 35 40

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

Figure 11. 44 kHz Passband Response 4× Mode, 96 kHzSample Rate

FREQUENCY – kHz

2.0

1.5

1.0

0

dB 0

–0.5

–1.0

–2.010 20 30 40 50 60 70 80

–1.5

0.5

Figure 12. 88 kHz Passband Response 2× Mode, 192 kHzSample Rate

FREQUENCY – Hz10

dB

r

–120100 1k 10k

–110

–100

–90

–80

–70

–60

–50

Figure 13. THD vs. Frequency Input @ –3 dBFS, SR 48 kHz

0

0

dB

150 200

–60

–100

50 100 250

–20

–40

–80

–120

–140

300FREQUENCY – kHz

–160


FREQUENCY – kHz

0

dB

–60

–120

–160

–40

–20

–80

–100

–140

0 150 20050 100 250


dBFS

dB

–80

–90

–100

–110

–70

–60

–50

–40

–30

–20

–10

0

–120 –100 –80 –60 –40 –20 0

Figure 16. THD + N Ratio vs. Amplitude Input 1 kHz,SR 48 kHz, 24-Bit

REV. A

AD1853

–12–

FREQUENCY – Hz10

dB

r

–12100 1k 10k

–10

–8

–6

–4

–2

0

2

Figure 17. Normal De-Emphasis Frequency ResponseInput @ –10 dBFS, SR 48 kHz

FREQUENCY – kHz

dB

r

–90

–110

–130

–150

–70

–50

–30

–10

0 2 4 6 8 10 12 14 16 18 20 22

Figure 18. SMPTE/DIN 4:1 IMD 60 Hz/7 kHz @ 0 dBFS

dBFS

dB

r

–80

–100

–120

–140

–60

–40

–20

0

–140 –120 –100 –60 –40 –20 0–80

Figure 19. Linearity vs. Amplitude Input 200 Hz,SR 48 kHz, 24-Bit Word

FREQUENCY – kHz

dB

r

–130

–140

–150

–120

–110

–100

–90

0 2 4 6 8 10 12 14 16 18 20 22

–80

–70

–60

–50

–40

–30

–20

–10

0

Figure 21. Input 0 dBFS @ 1 kHz, BW 10 Hz to 22 kHz,SR 48 kHz, THD+N 104 dBFS

FREQUENCY – kHz

dB

r

–130

–140

–150

–120

–110

–100

–90

0 2 4 6 8 10 12 14 16 18 20 22

–80

–70

–60

–50

–160

Figure 22. Dynamic Range for 1 kHz @ –60 dBFS,116 dB, Triangular Dithered Input

FREQUENCY – kHz

dB

r

–130

–140

–150

–160

–120

–110

–100

–90

0 2 4 6 8 10 12 14 16 18 20 22

Figure 20. Noise Floor for Zero Input, SR 48 kHz,SNR –117 dBFS A-Weighted

REV. A

AD1853

–13–

FREQUENCY – Hz10

dB

r

–100

–90

–60

100 1k 10k

–70

–80

Figure 23. Power Supply Rejection vs. FrequencyAVDD 5 V dc + 100 mV p-p ac

FREQUENCY – kHz

0

–100

12020

dB

r

40 60 80 100

–10

–40

–70

–80

–90

–20

–30

–50

–60

–110

–120

–130

–140

Figure 24. Wideband Plot, 15 kHz Input, 8× Interpolation, SR 48 kHz

FREQUENCY – kHz

0

–100

12020

dB

r

40 60 80 100

–10

–40

–70

–80

–90

–20

–30

–50

–60

–110

–120

–130

–140


FREQUENCY – kHz

0

–100

305

dB

r

10 15 20 25

–10

–40

–70–80

–90

–20

–30

–50

–60

–110

–120–130

–140

–150

–16035 40 45 50 55 60 65 70 75 80


FREQUENCY – kHz

0

–100

305

dB

r

10 15 20 25

–10

–40

–70–80

–90

–20

–30

–50

–60

–110

–120–130

–140

–150

–16035 40 45 50 55 60 65 70 75 80


REV. A

AD1853

–14–

STEREO MODE OUTPUT FILTER

HDR3 FN 1 2

44/48 0 0 96 1 0 192 0 1 NO 1 1

C3747pF

C11100nF

DVDD

C2447nF

R41k

DVDD AVDD

OUTR+

OUTR–

OUTL+

OUTL–

FILTB

DGND AGND

FCR

U5AD1853JRS

C2610F

C56100nF

SIGNALSOURCE

J1

R3750

R175

R810k

R710k

R910k

C9100nF

DVDD

C8100nF

AVDD

DVDD

DS1ZEROLEFT

C10100nF

FB3600Z

NOTE:

= DGND

= AGND

INT4

INT2

SDATA

L/RCLK

BCLK

MCLK

IDPM0

IDPM1

DEEMP

MUTE

CLATCH

CCLK

CDATA

ZEROR

ZEROL

RST

FILTR

IREFCLATCH

CCLK

CDATA

ZR

ZL

RST

+–

R282.67k

AGNDDGND

SAMPLE RATEMODER5

10kR610k

DVDD

R1910k

CLK/I0

I1

I 2

I 3

I 4

I 5

I 6

I 7

I 8

I 9

I10

I11

I /O9

I /O8

I /O7

I /O6

I /O5

I /O4

I /O3

I /O2

I /O1

I/O 0

U4PALCE22V10-J

MCLK

EXT MCLK

EXT SCLK

EXT L/RCLK

EXT SDATA

HDR3

R1810k

3

8IDPM1

DVDD

R1710k

2

9IDPM0

DVDD

S2B S2C

VREF

R23274

Q12N2222

DS4 DVDD

VERF

PREEMPH 1

23

DVDD

U3A74HC00D

C5100nF

DVDD

C6100nF

SDATA

FSYNC

SCK

MCK

M0

M1

M2

M3

C

U

CBL

VERF

ERF

C0/E0

Ca/E1

Cb/E2

Cc/F0

Cd/F1

Ce/F2

SEL

CSI2/FCKDGNDAGND

VA+ VD+

FB2600Z

R24100

R1210k

C3547pF

R25100

R1310k

C3647pF

R26100

R1410k

C3447pF

R27100

R1510k

EXT SDATA

EXT L/RCLK

EXT SCLK

EXT MCLK

DVDD

R1110k

1

10

DVDD

S2A

SPDIF/EXTSPDIF/EXT

I/FSELECT

ROUT+

ROUT–

LOUT+

LOUT–

VREF+2.7V

HDR2

EXT I/FIN

FS

64FS

256FS

U2CS8414-CS

12

1311

U3D74HC00D

SET Ib = 1mA

DS2ZERORIGHTR21

2749

108

U3C74HC00D

DS3DEEMPH

R222744

56

U3B74HC00D

DVDD

R20274

DVDD

C12100nF

ZR

ZL

FILT

C110nF

S1

C210nF

RXP

RXN

1

0

SPNIFIN

DGND

SHLD DGND

U1TORX173

OUT

DVDD

TOSLINKIN

C4100nF

R23.40k

500mVp-p

FB1600Z

DVDD

R1010k

MUTE

R1610k

4

7

DEEMPH

DVDD

S2D

ONOFF

DEEMPH

56

MUTES2E

OFFON

CDATA

CCLK

CLATCH

MCLK

DVDDHDR1

EXT CI/F

12345

1 0U2 DATA SOURCE

I2S SERIALDATA MODE

DEEMPH OFFMUTE OFF

S2AS2BS2CS2DS2E

#98107-02-3 REV. 1.1

1

1

Figure 28. Digital Receiver, MUX and AD1853 DAC

REV. A

AD1853

–15–

U8B

OP275

C38220pFNP0R29

2.94k

R41604

R342.74k

C43680pF NP0

R332.74k

C42680pF NP0

R302.94k

R352.74k

R362.74k

C39220pFNP0

C502.2nF

NP0

RIGHTOUT

J21

GAUSSIAN FILTER RESPONSE–3dB CORNER FREQUENCY: 75kHz

OUTPUT BUFFERS AND LP FILTERS

0R4349.9k

C46330pF, NP0

C52*NP

C21100nF

–AVSS

C23100nF

+AVCC

OP275U6A

R484.12k

U6B

OP275C53*NP

C47330pF, NP0

R494.12k

C57220pF

NP0

+–

C7100nF

U8AOP275

C40220pFNP0R31

2.94k

R42604

R382.74k

C45680pF NP0

R372.74k

C44680pF NP0

R322.94k

R392.74k

R402.74k

C41220pFNP0

C512.2nF

NP0

LEFTOUT

J31

0R4449.9k

C48330pF, NP0

C54*NP

C20100nF

–AVEE

C22100nF

+AVCC

OP275U7A

R504.12k

U7B

OP275C55*NP

C49330pF, NP0

R514.12k

C58220pF

NP0

C19100nF

–AVSS

C18100nF

+AVCC

R52402

R53402

C2510F

ROUT+

LOUT+

LOUT–

VREF+2.7V

AVDD

AGND

+15V dc

DS5POWER

FB4600Z

IN

IN

ERR

SD

OUT

OUT

NR

GND

+AVCC

J6

U11ADP3303-5.0

C310nF

C16100nF

+

–C3110F+

–C3010F

C15100nF

+–

C3210F

+5V REG

R47332

–AVSS

CR21SMB15AT3

0VAGND

J7

+–

C3310F

–15V dcJ8

VOLTAGE REGULATORS AND SUPPLY FILTERING

DVDD+9V dc

TO+15V dc

FB5600ZJ4

U9LM317

+–

C2910F

+–

VIN

R46715

CR11SMB15AT3

0VDGND

J5+–

C2810F

VOUT

GND R45243

+5V REG

DGND

C13100nF

C2710F

CR31N4001

C14100nF

DVDD

PFI

MR

VCC

RESET

RESET

PFOGND

RST

U10ADM707AR

S3RESET

C17100nF

RESET GENERATOR

NOTE:

= DGND

= AGND

*NOT POPULATED

ROUT–

Figure 29. DAC Output LP Filter, Power and Reset

REV. A

AD1853

–16–

C35

03a–

8–4/

99P

RIN

TE

D IN

U.S

.A.

U1

AD797

C1220pFNP0R1

2.94k

R7604

R42.74k

C4680pFNP0

R32.74k

C3680pFNP0

R22.94k

R52.74k

R62.74k

C2220pFNP0

C52.2nFNP0

GAUSSIAN FILTER RESPONSE–3dB CORNER FREQUENCY: 75kHz

I/V CONVERTERS AND LP FILTER

R849.9k

C668pF, NP0

AD797

U2

R9*2.87k

U3

C768pF, NP0

R10*2.87k+

–C8

100nF

R12100

PIN 13LOUT–

PIN 12LOUT+

VREF+2.78V

R11100

AD797

OUT6Vrms

J11

0

PIN 16ROUT–

PIN 17ROUT+

NOTES:1. R9, R10 MUST BE LOW NOISE TYPES. METAL FILM IS RECOMMENDED.2. RIGHT CHANNEL DIGITAL DATA MUST BE INVERTED.

C1510FTANT

+AVCC

–AVSS

J2

+–

C14100nF

0VAGND

J4

+–

C1710FTANT

J3

C13100nF

C1610FTANT

C12100nF

C11100nF

C10100nF

C9100nF

+16.5V dc

–16.5V dc

NOTE:

= AGND

Figure 30. Mono Application Circuit

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

28-Lead Shrink Small Outline Package (SSOP)(RS-28)

0.009 (0.229)0.005 (0.127)

0.03 (0.762)0.022 (0.558)

8°0°0.008 (0.203)

0.002 (0.050)

0.07 (1.79)0.066 (1.67)

0.078 (1.98)0.068 (1.73)

0.015 (0.38)0.010 (0.25)

SEATINGPLANE

0.0256(0.65)BSC

0.311 (7.9)0.301 (7.64)

0.212 (5.38)0.205 (5.21)

28 15

141

0.407 (10.34)0.397 (10.08)

PIN 1

Documents

Stereo, 24-Bit, 192 kHz, Multibit DAC AD1853€¦ · REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed