ELSEVIER Nuclear Physics B (Proc. Suppl.) 113 (2002) 337-343 www.elsevier.com/locatelnpe

Status Report on Front End Electronics for the EUSO Photon Detector

G. Bosson a, D. Dzahini”, D.H. Koanga, P. Music0 b, M. Pallavicinib, J. Pouxea, F. Pratolongob, J.P. Richer”

aInstitut des Sciences Nucleaires 53, Avenue des Martyrs - 38026 - GRENOBLE - France

bIstituto Nazionale di Fisica Nucleare - Genova, via Dodecaneso, 33 - 16146 - GENOVA - Italy

In this paper we’ll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalization (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions.

1. Introduction

The prototype of the DFEE chip is now under design by the Genova INFN group and its main purpose is to test all the functionalities needed in the final device, including the fast front end preamplifier/discriminator cell, and the X, Y and fast OR logic generators requested by the orig- inally proposed architecture[l,2]. In addition, a large memory buffer and a serial data communi- cation line are foreseen.

terminology to understand the following descrip tions, so bibliography reading is reccomended.

2. The DFEE design

The base functions of the DFEE are the follow- ing:

l Preamplify the photon detector signal, as- suming the charge gain of about 5 x lo5 with a signal width of about 5 ns, and about 1 ns of rise and fall time.

The AFEE is under design by the Grenoble people. Our group is developing a prototype which will be used to prove all the characteris- tic of the proposed solution.

The two approaches are complementary: the design studies and the prototyping are carried out in parallel during Phase A. A common chip de- sign which integrates both functionalities will be developed during successive phases.

The reader must be familiar with the EUSO

Discriminate these signals with a pro- grammable threshold. The threshold con- trol and stability must be good enough to allow the threshold to be set well below the single photoelectron amplitude.

Mask noisy or bad channels.

Count the photons detected by each chan- nel during an externally driven time inter- val, the GTU. When this number of photons

0920-5632/02/S - see front matter 0 2002 Elsevier Science B.V. All rights reserved. PII SO920-5632(02)01X61-3

G. Bossorz el al. /Nuclear Physics B (Proc. Suppl.) 113 (2002) 337-343 338

l

l

.

2.1.

is above a programmable digital threshold, activate asynchronously the trigger signals.

Provide the logical signals required by the triggering system, i.e. the X and Y coordi- nates of the pixel above the digital thresh- old and the fast OR.

Store in an internal buffer the number of photons detected per each GTU for a large number of GTUs (of the order of 512 for the final 64 channels design). These data can be read out through a serial line.

Accept commands, parameters and settings from a serial line.

Block diagram

The chip will contain 16 identical channels, some common logic for control and serial commu- nication and a main DAC used to set the global analog discriminators threshold.

Each channel will be equipped with two RAM buffers 2048 word x 16 bit each. In the final ver- sion this buffer can be reduced to 512 words. Each RAM can be written from the serial interface for testing purposes.

The block diagram for each channel is repre- sented in figure 1.

The common logic will generates all needed sig- nals used to the channels and will contain all the configuration registers. In addition a time stamp counter in incremented every CLOCK period and give a rough timing information to the data inside the GTU period.

A current DAC is implemented to globally set the analog discriminators threshold. This thresh- old is then adjusted with a 4 bit DAC local to the channel.

We estimate to have a grand total of about 60 pin for this prototype. The PMT anode con- nections will have a built in protection circuit to avoid high current inrush and limit the voltage swing between the supply rails.

2.2. Analog front end The PMT anode output has the following con-

figuration: Rise time = fall time = Ins. The total width is 5 ns and the peak current is 7pA (for the

single photo-electron). The PMT gain is assumed to be 5~10~.

Our choice is a current mirror amplifier. The main feature of this circuit is that it has low in- put impedance with a high speed and small power consumption. A brief description of the working principle of the amplifier is the following (see fig- ure 2): a variation of the input current change the source voltage of the MOS I2 producing a current at the drain node that is mirrored (120 and 121) to the output branch. It will be possible to add another copy of the output signal for the AFEE. Moreover there is a simple CMOS inverter at the input, working to decrease the input impedance.

The first stage of the current comparator (or discriminator), not shown, is a class B voltage buffer with positive feedback, while the other MOS form two inverting amplifiers. When the current flows into the circuit the output is high. When the current flows out of the circuit, the output is low.

The simulations for the entire analog channel (preamplifier + discriminator) show that we have the following results:

Preamp current Gain N 1.7;

Double hit resolution N 10 ns;

ZIN = 400 a;

DC quiescent amplifier output current N 0.3

PA;

Steady supply power N 426 pW;

Peak supply power N 878 pW.

These results are obtained with power supply voltage = 3.3 V, T = 27 ‘C; Discriminator thresh- old current = 4pA.

2.3. Internal registers

For every channel we need the following config- uration/setting bits:

l Channel enable: enables the front end dis- criminator output. This can be also used to test the photon counter: since the inactive state of the front end discriminator is low

G. Bossorz et al. /Nuclear Physics B (Proc. Suppl.) 113 (2002) 337-343 339

FAST MEMORY AND ASSOCIATED LOGIC

Figure 1. Single channel block diagram

(it can be forced low raising the discrimi- nators threshold current), pulsing this bit cause the increment of the photon counter.

l OR enable: enables the front end discrim- inator output gated with the digital com- parator to play with the global chip fast OR.

l DISCR OUT selecto$:O/: used to select the channel to be directly sent out. MSB is the enable bit, while bit [3:0] are the selec- tion.

l Digital threshoZd[7:0]: digital comparator threshold.

l XY enable: enables the output of the digital comparator to partecipate to the X and Y generation.

l Fine DAC[3:0]: local setting to adjust the analog threshold of the discriminator. LSB is 250 nA. LSB value depends on VBIAS DAC. LSB value and the effective number of bit used have to be defined.

l Coarse DAC[7:0]: setting of the analog dis- criminators threshold. LSB is 4 ,uA. LSB value depends on VBIAS DAC. LSB value and the effective number of bit used have to be defined.

l GTU sum period[7:0]: period for generation of the GTU SUM signal (see appropriate section).

In addition we need the following configura- a Fast RAM write address[l5:0]: used to ac- tion/setting bits, which are global to the whole cess the Fast memory buffer for test purpose chip: only.

340 G. Bosson et al. /Ntrclear Physics B (Proc. Suppl.) 113 (2002) 337-343

CURRENT MIRROR AMPLIFIER 3: 12, 120, 121;

Figure 2. Preamplifier schematic

l Slow RAM write address[l5:0]: used to ac- cess the Slow memory buffer for test pur- pose only.

a Fast RAM read address[l5:0]: used to ac- cess the Fast memory buffer for test purpose only.

l Slow RAM read address[l5:0]: used to ac- cess the Slow memory buffer for test pur- pose only.

All the indicated bits are loaded serially and they are organized as shift registers, with corre- sponding parallel registers which store the value

after the shift operation.

2.4. Serial interface The serial interface is used to load and read

back all the internal chip registers. The inter- face is also used to access all the chip memories to read out the acquired data and to test them. The rising edge of the free running CLOCK sig- nal is used to synchronize all the operations. The bi-directional DATA line is used for serial data and control informations transmission. The D C

line is used to identify the control part of the se- rial stream from the data part. Data are always transferred MSB first.

G. Bosson et al. /Nuclear Physics B (Proc. Suppl.) 113 (2002) 337-343 341

Figure 3. Serial protocol: a write operation

In figure 3 a write cycle is represented. event timing. Reading operation can be carried out in two

modes: single and block transfers. Single transfer read mode is used on both registers and memo- ries, while block transfer can be used only access- ing memories.

2.5. Working mode 2.5.1. Chip configuration

All the internal registers must be set before any data acquisition can start, after every power up and after every reset pulse. The default value of all registers after reset is 0. The memories con- tent is unknown. The configuration must be done using the serial protocol described before.

The GUT SUM signal is generated every N GTU CLOCK pulses (N is programmed in the appropriate register). Every GTU SUM pulse the accumulated value is stored in the Slow RAM, the corresponding address counters are incremented (both read and write) and the accumulator is cleared. After the GTU SUM pulse the accumu- lator is cleared and the process can restart.

2.5.3. Data read out

2.5.2. Running Once the chip has been configured the RUNsig-

nal can be activated. This generates a reset pulse for the internal RAM address counters, which are initialized with correct values for run operations. The gtu sum counter is also initialized. After that the GTU CLOCK signal can be sent to the chip. Every GTU CLOCK pulse the channel data are stored in the Fast RAM, the corresponding ad- dress counters are incremented (both read and write) and the accumulator is incremented. After the GTU CLOCK the photon counter is cleared and the counting process can restart. The signals Xb(l, Yb[l and FAST OR are generated depending on the status of every channel.

Before starting the read out process, the run mode must be disabled, deactivating the RUN signal. After that no GTU CLOCK signal must be issued. The read out of the memory is per- formed via the serial interface, addressing all the 16 + 16 channel memories. The read process will start bringing out the oldest data stored in the selected memory. The process must read out all the locations and then continue to the next mem- ory. There will be no need to set up the address counters, since they are synchronized with write and read operations.

The time needed to read out a single memory can be estimated: 14 + N x 17 clock cycles, where N is the number of memory locations. For a 512 word memory we need 8718 clock cycles. If we run with 20 MHz clock we need about 436 ps to read a single memory and about 14 ms for a complete 16 channels chip.

When the digital comparator fires the time stamp value is saved and then written into the memory. This is the number of CLOCK cy- cles after GTU CLOCK before passing the digital threshold, which gives a rough information on the

Trigger logic must be able to identify both fast and slow events and inform- the macrocell what kind of event has been identified. Macro- cell logic can then read out only the interested RAM buffers, halving the total read out time.

342 G. Bosson et al. /Nuclear Physics B (Proc. Suppl.) 113 (2002) 337-343

2.5.4. Front end testing For front end testing purposes a discriminator

output can be carried out to the DISCR OUT pin. This function must be programmed using the DISCR OUT Setting register, which select the channel with bit [3:0] and enable the output (bit

4).

3. The AFEE design

The original idea of the AFEE is to measure the charge produced by the detector (the MAPMT) during the GTU period. This charge has to be stored for several microseconds to wait the trigger and then carried out of the chip for digitalization, using a low power commercial Analog to Digital converter.

The charge is measured integrating the MAPMT current, charging a capacitor. The volt- age value on this capacitor is then saved in an analog memory circular buffer.

The dominant lines of the AFEE are essentially two:

l Extend the dynamics toward energies where DFEE is saturated

l Permit the DFEE calibration

Since the preamplifier of the AFEE will drive an integrator, it must be very precise in term of DC components. A special configuration with feedback has been designed in order to keep the DC output level very close to zero: simulations show that the preamplifier DC output current can be as low as 50-60 nA over the full parame- ters range and constant with power supply volt- age variations.

The linearity is also an issue: we use the highest available power supply voltage (3.5 V) to guaran- tee that.

There are several options for the AFEE:

l Full AFEE.

It will have 1 channel per pixel, with dy- namic range up to 400 photoelectrons per pixel every GTU. It will provide indepen- dent energy measurement, but it needs one analog memory per channel and the power

consumption will be increased about of 1.5 mW per channel.

l Reduced AFEE.

It will have only one channel connected to the last MAPMT dynode, which carry the total cathode charge, with one gain stage missing. The dynamic range will be about of 4000 p.e. per PMT per GTU; the power consumption is only 1.5 mW per PMT. It can improve the shower profile at high en- ergy, where the DFEE is saturated. It can also provide information on Cherenkov events to the trigger system.

l Intermediate AFEE.

It is the same as Reduced AFEE, with DFEE calibration capability added.

The actual idea, keeping in consideration also the total power budget, is to develop the Inter- mediate AFEE idea.

A complete analog channel (preamplifier, inte- grator, 256 cells analog memory, control circuit) will be implemented and connected to the last MAPMT dynode. An analog multiplexer is then used to directly carry out the charge information coming from each anode, without storing it. This feature can be used in dedicated calibration runs, to directly measure each anode signal and tune the DFEE discriminator threshold.

The dynode integrator output can also be used to generate logic signals (using one or more com- parators, with different thresholds) which can be used by the trigger logic to identify fast high en- ergy events, like Cherenkov ligth effects.

4. Prototyping in 2002

The protoype of the DFEE chip which is now under development, will be submitted for fab- rication during 2002 using AMS CSI (or CSD) 0.35 pm technology. This prototype will be used to characterize all the functionalities for the fi- nal chip design and will be connected to the MAPMTs of the focal surface prototype we have in our lab.

Also the AFEE will be submitted for prototyp ing during this year. It will include several config-

G. Bosson et al. /Nuclear Physics B (Proc. Suppl.) 113 (2002) 337-343 343

urations of preamplifier/integrator pairs and few analog memory chains. The technology used will be the same as for DFEE, using power supply voltage of 3.5 V, to have large dynamic range.

5. Conclusions

For the final development a more robust RAD tolerant technology needs to be selected; the num- ber of channels in the final device may differ from the prototype according with the PMT choice and the microcell design. The AFEE circuit will also be included, developing a common final device.

A possible technology candidate to be evalu- ated and eventually start the space qualification process is a Si-Ge 0.35 pm from AMS and AL- CATEL.

Once the chioce of the technology has been made, the design must be completely reviewed, specially for analog parts in order to obtain the performances needed.

REFERENCES

1.

2.

3.

4.

5.

0. Catalano, Air Watch from Space, IFCAI- CNR Internal note, Sep 24, 1999. 0. Catalano, Extreme Universe Space Obser- vatory - EUSO: an innovative project for de- tection of extreme energy cosmic rays and neuttinos, 11 Nuovo Cimento, vol. 24 C, n. 3, pp.445-470, May-June 2001. M. Ameri et al, Study report on the EUSO photo-detector design, INFN note INFN/AE 01/04, Apr 6, 2001 M. Ameri et al, EUSO (Extreme Universe Space Observatory): the focal surface photo detector, Proc. 27th ICRC, vol. HE, pp. 856- 859, Aug 2001 P. Music0 et al, Development of the photon detector for a space based observatory of very high energy cosmic rays, Advanced Technol- ogy and Particle Physics Conference, Como, October 15-19, 2001