Status of mTCA Stripline BPM Development

Status of mTCAStripline

BPM DevelopmentJune 4-5, 2012

Dan Van Winkle for BPM team:Sonya Hoobler, Tom Himel, Jeff Olsen, Steve Smith, Till Straumann, Ernest Williams, Chuck Yee, Andrew Young

2

Outline• Background

– Motivation• System Description

– Physics Requirements– Proposed new design– Cost comparisons– Technical Overview

• Current Status• Schedule• Risks

– mTCA– Pizza Box– VME/AFE

• Next Steps

mTCA BPM DevelopmentJune 4-5, 2012

3

Background


4

Background4 Flavors of BPMs


LCLS Pizza Box

FACET – LINAC CAMAC

FACET – Sector 20

XTA

5

Background

• Assumptions– LCLS II will use existing BPMs whenever possible

(CAMAC)– 91 new BPMs will be necessary for LCLS II. These will

be some type of “new” electronics.– The existing linac BPMs will eventually need to be

upgraded to something more sensitive (exactly like LCLS I).

– This development is targeted at both the new BPMs for LCLS II and the upgrading of the existing BPM electronics throughout the linac.


6

Why not just clone the LINAC (CAMAC) BPM electronics? (Motivation)

• CAMAC technology is obsolete and becoming more difficult to maintain– Obsolete Parts– PDR Specs can not be met (this was demonstrated in

LCLS I)– Technical expertise is disappearing– EPICS incompatibility


7

Why not just clone the LCLS-I stripline BPM electronics? (more Motivation)

• Pizza Box solution was a quickly thrown together solution used to replace a COTS solution that did not work out.

• It worked so well that it is now used throughout LCLS I.Unfortunately:• Coldfire CPU in pizza box is too wimpy to do full job of IOC. Hence

special private network link to a VME IOC to transfer data for processing.– Requires VME crate/CPU/EVR per 4 BPMs

• Takes multiple people each with special expertise to put in a new BPM or even to repair an existing one.

• Requires a lot of network equipment and cables.


8

System Description


9

Physics Requirements


2 Differences from LCLS I

• 10pC Charge• 2 Bunches

10

Design Proposal• A new designed based upon the emerging

technology of mTCA was proposed.– New design can be used for rest of LCLS-II (even the

injector if we get the design done in time)– New Design at 250 Msamp/sec (300 MHz center

frequency) means existing cable plant can be used (for existing LINAC BPMs. (~500k$ savings)

– Allows for mix and match of systems (LLRF/BPMs) in same shelf (theoretically sharing infrastructure costs)


11

Deliverables• Design build and install one crate of 3 BPMs in a sector (1st

20 sectors)– We expect to use new 250 Msamp/sec ADC or potential

undersample at 125 Msamp/sec using Struck Board– The analog front end electronics will be a new design,

same topology as pizza box front end (but higher in frequency)

– The necessary software will be done to integrate the BPMs into the EPICS control system

• Mass production for 10 sectors (LCLS II) will be a separate AIP funded outside LCLS II core project.


12

Cost Comparisons


Cost Comparisons Between Systems

Micro TCA LCLS - I XTA Hardware Labor Estimate 960 Hardware Labor Estimate 2880 Hardware Labor Estimate 1920

Digitizer 4250 Pizza Box 3598 Digitizer 2200 RTM (AFE) 1500 AFE 2100

Total 6710 Total 6478 Total 6220

Crate 9 BPMs 1BPM 9 BPMs 1BPM

Shelf 5300 Crate (21 SLOT) 8495 Crate (21 SLOT) 8495 Crate (4-slot) 3885 3885

MCH 2300 CPU 4125 CPU 4125 CPU 2125 EVR 2700 EVR 2700

Power Module 1000 EVR Fanout 550 EVR Fanout 550 EVR 3300 Network Switch (x2) 360 Network Switch(x2) 360

Power Switch 600 Power Switch 600

Total 14025 Total 16830 12220 Total 16830 12220

Max Number of BPM/Shelf 9 9 9 Max Cost per BPM (1BPM) $20,735.00 $18,698.00 $18,440.00

Min Cost per BPM (9 BPM) $8,268.33 $8,348.00 $8,090.00

13

Requirements

• Similar Analog Front end at new frequency (300 MHz) (next slide)

• Expect slightly better dynamic range to accommodate new 10 pC charge limit for LCLS II

• Initial operation will use internal clock.• For multi-bunch operation, phase synchronous

ADC clock will be required to extract bunch phase information (238 MHz).


14

300 MHz vs. 140 MHz


0 50 100 150 200 250 300-20.00

-18.00

-16.00

-14.00

-12.00

-10.00

-8.00

-6.00

-4.00

-2.00

0.00

BPM Response

BPM Response

Frequency (MHz)

Am

plitu

de (d

B)

• By using 300 MHz instead of 140 MHz gain 4.6 dB of signal level• This allows us to potentially save large sums of cabling costs when we

eventually upgrade the LINAC BPMs. (New LCLS II BPMs will not see this cost advantage due to pulling of new cables anyway.

15

System Description


BPM

Crate

Analog Front End and Calibrator ADC IOC

(CPU)EVR

(Timing)

Channel Access Network

Calibrator Trigger

ADC Trigger

Timing Network

Crate Controller

(MCH)

ADC Clock

Utility Network (crate management)

Fast Feedback (coming later; to be connected to MCH or CPU or network

card)

Up to 9 BPM processors per crate

16

RTM Signal Flow Block Diagram


R=50 Ohm

R=50 Ohm

R=50 Ohm Freq=300 MHz

T=1.00 T=1.00

T=1.00 T=1.00

T=1.00 T=1.00

T=1.00T=1.00

BWpass=30 MHzFcenter=300 MHz








R3

R2

R1

SWITCH5

SWITCH4

SWITCH3 16dB_9 VAR_ATTEN9 SRC1

CLin4TF8 TF7

CLin3TF6 TF5

CLin2

TF4 TF3

CLin1TF2TF1

VAR_ATTEN8 VAR_ATTEN716dB_8 16dB_7 BPF8BPF7


SWITCH2


SWITCH1 BPF2VAR_ATTEN2VAR_ATTEN1 16dB_216dB_1BPF1

R

R

R

SPDT_Static

SPDT_Static

SPDT_Static Amplifier2 Attenuator VtSine

PCLIN2TF TF

PCLIN2TF TF

PCLIN2TF TF

PCLIN2

TFTF

Attenuator AttenuatorAmplifier2 Amplifier2 BPF_ButterworthBPF_Butterworth


SPDT_Static


SPDT_Static BPF_ButterworthAttenuatorAttenuator Amplifier2Amplifier2BPF_Butterworth

Calibrator

4 Channels of Analog Processing

17

Current Status


18

• 3 RTM Boards Loaded– Initial RF testing complete– Initial Data acquisition complete

• RTM CPLD Programmed and verified• FPGA on AMC card started

– Code for driving and control of CPLD• 250 Msamp digitizer spec started (90%

complete).


19

Prototype Board Complete (in test)

BPM AIP ReviewApril 11, 2012

Analog Front End RTM Struck 125 MHz digitizer

20

Modifications of 125 MS/s Board


0 50 100 150 200 250 300 350-14

-12

-10

-8

-6

-4

-2

0

2

Original

no AMC filter

No Filters

No Filters and New tranformer

Frequency (MHz)

dBc

(5 M

Hz

Valu

e)

Maximum Bandwidth achieved with SIS8300 is approximately 130 MHz.

21

Initial Results


1.8307 1.8308 1.8309 1.8311.5

2

2.5

3

3.5

4

4.5

5

5.5x 10

4

time (ms)

AD

C C

ount

s

Measured BPM signal (125 MSamp/sec) - simulated signal

Ch1Ch2Ch3Ch4

1.8307 1.8308 1.8309 1.8311.5

2

2.5

3

3.5

4

4.5

5

5.5x 10

4

time (ms)

AD

C C

ount

s

Measured BPM signal (125 MSamp/sec) - simulated signal

Ch1Ch2Ch3Ch4Oscope - Ch4

Measured Results from mTCA system on “simulated” Beam Signal

22

Schedule


23

Current Schedule

BPM AIP ReviewApril 11, 2012

24

Schedule Comments

• Tight Schedule to make LCLS II Injector• FDR’s for Injector occurring in July/August

time frame. • Hardware installed in racks not required till

late 2013.• There is some belief that we can still get the

design into the LCLS II injector.


25

Risks


26

Risks (mTCA)• mTCA Infrastructure

– New standard - interoperability is a potential issue – we are diligently working on this

• Digitizer– Counting on vendor which is currently struggling with 10

channel design. However vendor seems solid and recent vendor visit put most fears to rest.

– Potential delays due to vendor• Manpower availability/Priority Setting• Backup Plan for injector is VME digitizer with AFE in

small pizza box.


27

Risks (Pizza box)• Obsolete Parts• Unsupportable PADs with “wimpy” coldfire CPU’s• Redesign necessary on PAD for continued use• Custom electronics which must be supported for the

indefinite future.


28

Risks (VME Digitizer/AFE) (Backup Plan)

• Custom Boards (ADC and AFE) (not COTS)• Could be obsolete parts on digitizer• Custom electronics which must be supported for the

indefinite future.• May not be able to do multi-bunch operation


29

Next Steps

• Calibrator needs to be tested• Finish FPGA code in Struck 10ch digitizer• Order new digitizer (250 Msamp/sec version)• System software and integration


Documents

Status of mTCA Stripline BPM Development