Static Timing Analysis

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STATIC TIMING ANALYSISSTATIC TIMING ANALYSIS

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IntroductionIntroduction

Effective methodology for verifying the timing characteristics of a design Effective methodology for verifying the timing characteristics of a design without the use of test vectorswithout the use of test vectors

Conventional verification techniques are inadequate for complex Conventional verification techniques are inadequate for complex designsdesigns Simulation time using conventional simulatorsSimulation time using conventional simulators

Thousands of test vectors are required to test all timing paths Thousands of test vectors are required to test all timing paths using logic simulation using logic simulation

Increasing design complexity & smaller process technologiesIncreasing design complexity & smaller process technologies Increases the number of iterations for STAIncreases the number of iterations for STA

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Simulation vs. Static timingSimulation vs. Static timing

0%0% 100%100%

Timing Simulation (adding vectors)

Static timing analysis(eliminating false paths)

True timing pathsTrue timing paths False timing pathsFalse timing paths

STA approach typically takes a fraction of the time it takes to run logic simulation on a large design and guarantees 100% coverage of all true timing paths in the design without having to generate testvectors

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OVERVIEWOVERVIEW

Previous Verification Flow

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• Requires extensive vector creation

• Valid for FPGAs and smaller ASICs

• Falls apart on multi-million gate ASICs

OVERVIEWOVERVIEW

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What is Static Timing Analysis?

Static Timing Analysis is a method for determining if a circuit meets timing constraints without having to simulate

Much faster than timing-driven, gate-level simulation

Proper circuit functionality is not checked

Vector generation NOT required

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STA in ASIC Design Flow – Pre STA in ASIC Design Flow – Pre layoutlayout

Logic Synthesis

Design For test

Floor planning

Constraints(clocks, input drive,

output load)

Static Timing Analysis

Static Timing Analysis(estimated parasitics)

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STA in ASIC Design Flow – STA in ASIC Design Flow – Post LayoutPost Layout

Floor planning

Clock Tree Synthesis

Place and Route

Parasitic Extraction

SDF(extracted parasitics)

Constraints(clocks, input drive,

output load)

Static Timing Analysis(estimated parasitics)

Static Timing Analysis(extracted parasitics)

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2 Types of Timing Verification

Dynamic Timing Simulation

Advantages

Can be very accurate (spice-level)

Disadvantages

Analysis quality depends on stimulus vectors

Non-exhaustive, slow

Examples:

VCS,Spice,ACE

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Static Timing Analysis (STA)

Advantages

Fast, exhaustive

Better analysis checks against timing requirements

Disadvantage

Less accurate

Must define timing requirements/exceptions

Difficulty handling asynchronous designs, false paths

2 Types of Timing Verification

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Three Steps in Static Timing Analysis

Circuit is broken down into sets of timing paths

Delay of each path is calculated

Path delays are checked to see if timing constraints

have been met

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What is a Timing Path?

A Timing Path is a point-to-point path in a design which

can propagate data from one flip-flop to another

Each path has a start point and an endpoint

Start point:

Input ports Clock pins of flip-flops

Endpoints:

Output ports Data input pins of flip-flops

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Organizing Timing Paths Into Groups

Timing paths are grouped into path groups by the

clocks controlling their endpoints

Synthesis tools like PrimeTime and Design Compiler organize timing reports by path groups

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Net and Cell Timing Arcs

The actual path delay is the sum of net and cell delays along the timing path

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Net and Cell Delay“Net Delay” refers to the total time needed to charge or discharge all of the parasitics of a given net

Total net parasitics are affected by

net length

net fanout

Net delay and parasitics are typically

Back-Annotated (Post-Layout) from data obtained from

an extraction tool

Estimated (Pre-Layout)

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Cell Delay

In ASICs, the delay of a cell is affected by:

The input transition time (or slew rate)

The total load “seen” by the output transistors

Net capacitance and “downstream” pin capacitances

These will affect how quickly the input and output transistors can “switch”

Inherent transistor delays and “internal” net delays

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Transparent Latch, Level Sensitive

– data passes through when clock high, latched when clock low

Clocked Storage Elements

D-Type Register or Flip-Flop, Edge-Triggered

– data captured on rising edge of clock, held for rest of cycle

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Flip-Flops

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Basic terminologiesBasic terminologies

Pulse WidthPulse Width Setup & Hold timesSetup & Hold times Signal slewSignal slew Clock latencyClock latency Clock SkewClock Skew Input arrival timeInput arrival time Output required timeOutput required time Slack and Critical pathSlack and Critical path

Recovery & Removal timeRecovery & Removal timess

False pathsFalse paths Multi-cycle pathsMulti-cycle paths

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Pulse WidthPulse Width

Pulse widthPulse width It is the time between the active and inactive states of the same It is the time between the active and inactive states of the same

signalsignal

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Setup and Hold timeSetup and Hold time

Setup time Setup time For an edge triggered sequential element, the setup time is the time For an edge triggered sequential element, the setup time is the time

interval before the active clock edge during which the data should interval before the active clock edge during which the data should remain unchangedremain unchanged

Hold timeHold time Time interval after the active clock edge during which the data Time interval after the active clock edge during which the data

should remain unchangedshould remain unchanged

Both the above 2 timing violations can occur in a design whenBoth the above 2 timing violations can occur in a design whenclock path delay > data path delayclock path delay > data path delay

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Signal SlewSignal Slew

Signal (Clock/Data) slewSignal (Clock/Data) slew Amount of time it takes for a signal transition to occurAmount of time it takes for a signal transition to occur Accounts for uncertainty in Rise and fall times of the signal Accounts for uncertainty in Rise and fall times of the signal Slew rate is measured in volts/secSlew rate is measured in volts/sec

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Clock LatencyClock Latency

Clock LatencyClock Latency Difference between the reference (source) clock slew to the clock Difference between the reference (source) clock slew to the clock

tree endpoint signal slew valuestree endpoint signal slew values Rise latency and fall latency are specifiedRise latency and fall latency are specified

INV

Rise=7Rise=7Fall=4Fall=4







CLKCLK

CLKACLKA

CLKBCLKB

CLKCCLKC

INVINV

INVINV

INVINVINVINVINVINV

BUFBUF

BUFBUF

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Clock LatencyClock Latency

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Clock SkewClock Skew

Clock Skew is a measure of the difference in latency between any two Clock Skew is a measure of the difference in latency between any two leaf pins in a clock tree.leaf pins in a clock tree. between CLKA and CLKBbetween CLKA and CLKB

rise = 22-8 = 14rise = 22-8 = 14fall = 22-14 = 8fall = 22-14 = 8

between CLKB and CLKCbetween CLKB and CLKC rise = 8-7 = 1rise = 8-7 = 1

fall = 14-4 = 10fall = 14-4 = 10 between CLKA and CLKC between CLKA and CLKC

rise = 22-7 = 15rise = 22-7 = 15fall = 22-4 = 18fall = 22-4 = 18

It is also defined as the difference in time that a single clock signal It is also defined as the difference in time that a single clock signal takes to reach two different registerstakes to reach two different registers

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Input Arrival timeInput Arrival time

Input Arrival timeInput Arrival time An arrival time defines the time interval during which a data signal An arrival time defines the time interval during which a data signal

can arrive at an input pin in relation to the nearest edge of the clock can arrive at an input pin in relation to the nearest edge of the clock signal that triggers the data transitionsignal that triggers the data transition

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Output required timeOutput required time

Output required timeOutput required time Specifies the data required time on output ports.Specifies the data required time on output ports.

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Slack and Critical pathSlack and Critical path

SlackSlack It is the difference between the required (constraint) time and the It is the difference between the required (constraint) time and the

arrival time (inputs and delays).arrival time (inputs and delays). Negative slack indicates that constraints have not been met, while Negative slack indicates that constraints have not been met, while

positive slack indicates that constraints have been met.positive slack indicates that constraints have been met. Slack analysis is used to identify timing critical paths in a design by Slack analysis is used to identify timing critical paths in a design by

the static timing analysis toolthe static timing analysis tool

Critical pathCritical path Any logical path in the design that violates the timing constraintsAny logical path in the design that violates the timing constraints Path with a negative slackPath with a negative slack

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Slack Analysis – Data Path Slack Analysis – Data Path typestypes

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Slack analysis – data path Slack analysis – data path typestypes

Primary input-to-register paths Primary input-to-register paths Delays off-chip + Combinational logic delays up to the first Delays off-chip + Combinational logic delays up to the first

sequential device.sequential device. Register-to-primary output paths Register-to-primary output paths

Start at a sequential device Start at a sequential device CLK-to-Q transition delay + the combinational logic delay + external CLK-to-Q transition delay + the combinational logic delay + external

delay requirements delay requirements Register-to-register paths Register-to-register paths

Delay and timing constraint (Setup and Hold) times between Delay and timing constraint (Setup and Hold) times between sequential devices for synchronous clocks + source and destination sequential devices for synchronous clocks + source and destination clock propagation times.clock propagation times.

Primary input-to-primary output paths Primary input-to-primary output paths Delays off-chip + combinational logic delays + external delay Delays off-chip + combinational logic delays + external delay

requirements.requirements.

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Hold Slack calculationHold Slack calculation

Actual data arrival time definitionActual data arrival time definitionData Input Arrival Timemin + Data path delayminData Input Arrival Timemin + Data path delaymin

If the data path starts in a primary input,If the data path starts in a primary input,Data Input arrivalmin = Input arrival timeminData Input arrivalmin = Input arrival timemin

If the data path starts at a register,If the data path starts at a register,(Source Clock Edgemin + Source Clock Path Delaymin) = (Source Clock Edgemin + Source Clock Path Delaymin) =

Data Input ArrivalminData Input Arrivalmin

Required Stability time definition Required Stability time definition (Destination Clock Edgemax + Destination Clock Path Delaymax) + (Destination Clock Edgemax + Destination Clock Path Delaymax) +

Hold = Required Stability TimemaxHold = Required Stability Timemax

Hold Slack definitionHold Slack definitionActual Data Arrivalmin - Required Stability TimemaxActual Data Arrivalmin - Required Stability Timemax

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Calculate the hold slackCalculate the hold slack

Source Clock signal timing parameters:Min Edge = 8.002 nsMin clock path delay = 0.002 ns

Destination Clock signal timing parameters:Max Edge = 2.020 nsMax clock path delay = 0.500 ns

Min Data path delay = 0.802 nsHold time constraint = 1.046 ns

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Hold slack calculationHold slack calculation

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Setup Slack calculationSetup Slack calculation

Actual data arrival time definitionActual data arrival time definitionData Input Arrival Timemax + Data path delaymaxData Input Arrival Timemax + Data path delaymax

If the data path starts in a primary input,If the data path starts in a primary input,Data Input arrivalmax = Input arrival timemaxData Input arrivalmax = Input arrival timemax

If the data path starts at a register,If the data path starts at a register,(Source Clock Edgemax + Source Clock Path Delaymax) = (Source Clock Edgemax + Source Clock Path Delaymax) =

Data Input ArrivalmaxData Input Arrivalmax

Required Stability time definition Required Stability time definition (Destination Clock Edgemin + Destination Clock Path Delaymin) - (Destination Clock Edgemin + Destination Clock Path Delaymin) -

Setup = Required Stability TimeminSetup = Required Stability Timemin

Setup slack definitionSetup slack definitionRequired Stability Timemin - Actual Data ArrivalmaxRequired Stability Timemin - Actual Data Arrivalmax

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Calculate the setup slackCalculate the setup slack

Source Clock signal timing parameters:Max Edge = 2.002 nsMax clock path delay = 0.002 ns

Destination Clock signal timing parameters:Min Edge = 20.02 nsMin clock path delay = 0.500 ns

Min Data path delay = 13.002 nsSetup time constraint = 0.046 ns

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Setup slack calculationSetup slack calculation

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Recovery and Removal timeRecovery and Removal time

Recovery timeRecovery time

Like setup time for asynchronous port (set, reset)Like setup time for asynchronous port (set, reset) Removal timeRemoval time

Like hold time for asynchronous port (set, reset)Like hold time for asynchronous port (set, reset)

Recovery timeRecovery time

It is the time available between the asynchronous signal going inactive It is the time available between the asynchronous signal going inactive to the active clock edgeto the active clock edge

Removal timeRemoval time

It is the time between active clock edge and asynchronous signal It is the time between active clock edge and asynchronous signal going inactivegoing inactive

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False PathsFalse Paths

False pathsFalse paths Paths that physically exist in a design but are not logic/functional Paths that physically exist in a design but are not logic/functional

paths paths These paths never get sensitized under any input conditionsThese paths never get sensitized under any input conditions

Mux 1

C C1 C2A

B

Mux 2

S

B1 B2

OUT

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Multi-cycle pathsMulti-cycle paths

Multi-cycle pathsMulti-cycle paths Data Paths that require more than one clock period for executionData Paths that require more than one clock period for execution

2 clock period delay

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Sequential Circuit TimingSequential Circuit Timing

ObjectivesObjectives

This section covers several timing considerations encountered in the design This section covers several timing considerations encountered in the design of synchronous sequential circuits. It has the following objectives:of synchronous sequential circuits. It has the following objectives: Define the following global timing parameters and show how they can be Define the following global timing parameters and show how they can be

derived from the basic timing parameters of flip-flops and gates.derived from the basic timing parameters of flip-flops and gates.

• Maximum Clock FrequencyMaximum Clock Frequency

• Maximum allowable clock skewMaximum allowable clock skew

• Global Setup and Hold TimesGlobal Setup and Hold Times Discuss ways to control the loading of data into registers and show why Discuss ways to control the loading of data into registers and show why

gating the clock signal to do this is a poor design practice.gating the clock signal to do this is a poor design practice.

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Maximum Clock FrequencyMaximum Clock Frequency

The clock frequency for a synchronous sequential circuit is limited by The clock frequency for a synchronous sequential circuit is limited by the timing parameters of its flip-flops and gates. This limit is called the timing parameters of its flip-flops and gates. This limit is called the the maximum clock frequencymaximum clock frequency for the circuit. The for the circuit. The minimum clock periodminimum clock period is is the reciprocal of this frequency.the reciprocal of this frequency.

Relevant timing parametersRelevant timing parameters Gates: Gates:

• Propagation delays: min tPropagation delays: min tPLHPLH, min t, min tPHLPHL, max t, max tPLHPLH, max t, max tPHLPHL

Flip-Flops:Flip-Flops:

• Propagation delays: min tPropagation delays: min tPLHPLH, min t, min tPHLPHL, max t, max tPLHPLH, max t, max tPHLPHL

• Setup time: tSetup time: tsusu

• Hold time: tHold time: thh

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ExampleExample

TW ≥ max tPFF + tsu

For the 7474, max tPLH = 25ns, max tPHL = 40ns, tsu = 20ns

TW ≥ max (max tPLH + tsu, max tPHL + tsu)

TW ≥ max (25+20, 40+20) = 60

D Q

QCK

Q

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ExampleExample

D Q

CK

Q

TW ≥ max tPFF + max tPINV + tsu

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ExampleExample

D Q

Q

D Q

Q

MUX0

1

Q0 Q1

CK

TW ≥ max tPFF + max tPMUX + tsu

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ExampleExample

Paths from Q1 to Q1:




None

TW ≥ max tPDFF +tJKsu = 20 +10 = 30 ns

TW ≥ max tPDFF + max tAND + tJKsu = 20 + 12 + 10 = 42 ns

TW ≥ max tPJKFF + tOR + TDsu = 25 + 10 + 5 = 40 ns

TW ≥ max tPJKFF + max tAND + tJKsu = 25 + 12 + 10 = 47 ns

TW ≥ 47 ns

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If a clock edge does not arrive at different flip-flops at exactly the same If a clock edge does not arrive at different flip-flops at exactly the same time, then the clock is said to be time, then the clock is said to be skewedskewed between these flip-flops. The between these flip-flops. The difference between the times of arrival at the flip-flops is said to be the difference between the times of arrival at the flip-flops is said to be the amount ofamount of clock skew clock skew..

Clock skew is due to different delays on different paths from the clock Clock skew is due to different delays on different paths from the clock generator to the various flip-flops.generator to the various flip-flops.

• Different length wires (wires have delay)Different length wires (wires have delay)

• Gates (buffers) on the pathsGates (buffers) on the paths

• Flip-Flops that clock on different edges (need to invert clock for Flip-Flops that clock on different edges (need to invert clock for some flip-flops)some flip-flops)

• Gating the clock to control loading of registers (a very bad idea)Gating the clock to control loading of registers (a very bad idea)

Clock SkewClock Skew

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• Example (Effect of clock skew on clock rate)Example (Effect of clock skew on clock rate) Clock C2 skewed after C1Clock C2 skewed after C1

Q1Q2

D Q

Q

D Q

Q

CK

C1C2

D2

TW ≥ max TPFF + max tOR + tsu

(if clock not skewed, i.e., tINV = 0)TW ≥ max TPFF + max tOR + tsu - min tINV

(if clock skewed, i.e., tINV > 0)

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Clock C1 skewed after C2Clock C1 skewed after C2

Q1Q2

D Q

Q

D Q

Q

CK

C1C2

D2

TW ≥ max TPFF + max tOR + tsu

(if clock not skewed, i.e., tINV = 0)

TW ≥ max TPFF + max tOR + tsu + max tINV

(if clock skewed, i.e., tINV > 0)

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Summary of maximum clock frequency calculationsSummary of maximum clock frequency calculations

D Q

Logic Network

D Q

C1 C2

Q1 D2

C1

Q1

D2

C2

TW

tPFF tOR tsu

tSK = tINV

C1

Q1

D2

C2

TW

tPFF tOR

tsu

tSK = tINV

C2 skewed after C1: TW ≥ max TPFF + max tNET + tsu - min tINV

C2 skewed before C1: TW ≥ max TPFF + max tNET + tsu + max tINV

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Maximum Allowable Clock SkewMaximum Allowable Clock Skew

How much skew between C1 and C2 can be tolerated in the following How much skew between C1 and C2 can be tolerated in the following circuit?circuit?

– Case 1: C2 delayed after C1Case 1: C2 delayed after C1

D Q

Q

D Q

Q

C2

Q1 D2

C1

tPFF > th + tSK

tSK < min tPFF - th

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Case 2: C1 delayed from C2Case 2: C1 delayed from C2

D Q

Q

D Q

Q

C2

Q1 D2

C1

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How does additional delay between the flip-flops affect the skew How does additional delay between the flip-flops affect the skew calculations?calculations?

tSK ≤ min tPFF - th

tsk ≤ min tPFF + min tMUX - th

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Summary of allowable clock skew calculationsSummary of allowable clock skew calculations

tSK + th ≤ tPFF + tNET

tSK ≤ min tPFF + min tNET - th

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Example: What is the minimum clock period for the following circuit under Example: What is the minimum clock period for the following circuit under the assumption that the clock C2 is skewed after C1 (i.e., C2 is delayed the assumption that the clock C2 is skewed after C1 (i.e., C2 is delayed from C1)?from C1)?

N1

N2

C1 C2

Q1 D2 Q2D1D Q

Q

D Q

Q

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First calculate the maximum allowable clock skew.First calculate the maximum allowable clock skew.

Next calculate the minimum clock period due to the path from Q1 to D2.Next calculate the minimum clock period due to the path from Q1 to D2.

Finally calculate the minimum clock period due to the path from Q2 to Finally calculate the minimum clock period due to the path from Q2 to D1D1

N1

N2

C1 C2

Q1 D2 Q2D1D Q

Q

D Q

Q

tSK < min tPFF + min tN1 - th

TW > max tPFF + max tN1 + tsu - min tSK

TW > max tPFF + max tN1 + tsu + max tSK

TW > max tPFF + max tN2 + tsu + (min tPFF + min tN1 - th)

TW > max tPFF + min tPFF + max tN2 + min tN1 + tsu - th

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Global Setup Time, Hold Time Global Setup Time, Hold Time and Propagation Delayand Propagation Delay

Global setup and hold times (data delayed)Global setup and hold times (data delayed)

TSU = tsu + max tNETTH = th - min tNET

D Q

Q

X

CK

NET D

CLK

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Global setup & hold time (clock delayed)Global setup & hold time (clock delayed)

D Q

QCK

D

CLK

TSU = tsu - min tC TH = th + max tC

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Global setup & hold time (data & clock delayed)Global setup & hold time (data & clock delayed)

D Q

Q

X

CK

NET D

CLK

TSU = + max =-0987654321\ - min . TH = th - min tNET + max tC

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Global propagation delayGlobal propagation delay

D Q

QCK

NETCLK

YQ

TP = tC + tFF + tNET

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Summary of global timing parametersSummary of global timing parameters

TSU = tsu + max tPN - min tPC ≤ tsu + max tPN

TH = th + max tPC - min tPN ≤ th + max tPC

TP = tPFF + tPN + tPC

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ExampleExample

Find TFind TSUSU and T and THH for input signal LD relative to CLK. for input signal LD relative to CLK.

LD

DCLK

CK

QD Q

Q

TSU = tsu +max tNET - min tC

TH = th - min tNET + max tC

= tsu + max tINV + max tNAND + max tNAND - min tINV

= th - min tNAND - min tNAND + max TINV

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Register load control (gating the clock)Register load control (gating the clock)

• A very bad way to add a load control signal LD to a register that does not A very bad way to add a load control signal LD to a register that does not have one is shown belowhave one is shown below

• The reason this is such a bad idea is illustrated by the following timing The reason this is such a bad idea is illustrated by the following timing diagram.diagram.

• The flip-flop sees two rising edges and will trigger twice. The only one we The flip-flop sees two rising edges and will trigger twice. The only one we want is the second one. want is the second one.

D

LD

CLK

CK

D Q

Q

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If LD was constrained to only change when the clock was low, then the only If LD was constrained to only change when the clock was low, then the only problem would be the clock skew.problem would be the clock skew.

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If gating the clock is the only way to control the loading of registers, then If gating the clock is the only way to control the loading of registers, then use the following approach:use the following approach:

There is still clock skew, but at least we only have one triggering edge.There is still clock skew, but at least we only have one triggering edge.

D

LD

CLK

D Q

Q

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The best way to add a LD control signal is as follows:The best way to add a LD control signal is as follows:

LD

DCLK

D Q

Q

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Tips & TricksTips & Tricks

Use timing diagrams to determine the timing properties of sequential circuitsUse timing diagrams to determine the timing properties of sequential circuits Using typical timing values from the data sheet (use only max and/or min Using typical timing values from the data sheet (use only max and/or min

values)values) Gating the clockGating the clock

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Detecting timing violations – Detecting timing violations – CASE 1CASE 1

clk10Mhtzclk10Mhtzclk20Mhtzrefclk20Mhtzref

Delay (min) = 5 nsDelay (min) = 5 nsDFF 2DFF 2DFF 1DFF 1

DataData

(a) Hold time for clocks is 1.5 ns

Determine if there are any timing violations in this designDetermine if there are any timing violations in this design

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Delay (min) = 5 nsDelay (min) = 5 ns


DFF 2DFF 2DFF 1DFF 1

DataData

(a) Hold time for clocks is 1.5 ns(b) Clock skew of 3.72 ns between clk20mref and clk10mz

Determine if there are any timing violations in this designDetermine if there are any timing violations in this design

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(a) Hold time for clocks is 1.5 ns(b) Clock skew of 3.72 ns between clk20mref and clk10mz



DataData


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Consider(a) Clock skew of 3.72 ns between clk20mref and clk10mz(b) Clock network delays



DataData


Propagation delay = 2 nsPropagation delay = 2 ns(thru clock tree buffers)(thru clock tree buffers)

Propagation delay = 4 nsPropagation delay = 4 ns(thru clock tree buffers)(thru clock tree buffers)

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Thank youThank you

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Static Timing Analysis