Tezzaron Semiconductor

Tezzaron Semiconductor

Stacking Process

< Optical MicrographOptical Micrograph > < Scanning Electron MicrographScanning Electron Micrograph >

“Super Via” 4um in diameter and 12um in height

3rd Si thinned to 5.5um

2nd Si thinned to 5.5um

1st Si bottom supporting wafer

SiO2

Three wafers successfully aligned and stacked

Tezzaron Semiconductor

3rd Si2nd Si

1st Si

Tezzaron Semiconductor

1.2 um1.2 um

Profiler View

Microscope View

Wet Etch: 1.2 µm Copper Via protruding

CuCu

SiSi

SiO2SiO2

SiSi4.8 um4.8 um

2 um2 um

2 um2 um

11stst wafer wafer

22ndnd wafer wafer

Exposed Bottoms of Super Vias

Tezzaron Semiconductor

11stst Wafer Blanket Cu Wafer Blanket Cu

33rdrd Wafer Blanket Cu Wafer Blanket Cu

2nd Wafer pattern Cu2nd Wafer pattern Cu

Super ViaSuper Via

Top MetalTop MetalPadPad

Three Cu Wafer Stacking

Three wafers stacking using an alternative stacking architecture “stacking process without backside process” invented during this project time, has been successfully demonstrated.

FIB micrograph showing 3 stacked wafer using newly designed process flow

Tezzaron Semiconductor

Tezzaron Semiconductor

Reg. File / Mixed Signal ASIC

• Byte per layer dual port memory• Bandgap on each layer• Heater Resistor to induce stress • 133MHz DLL (DDRI/II)• 4 Stage charge pump (cross layer)• POR

Tezzaron Semiconductor

Register File

Tezzaron Semiconductor

CPU/Memory Stack

• R8051 CPU – 80MHz operation; 140MHz Lab test (VDD High)– 220MHz Memory interface

• IEEE 754 Floating point coprocessor• 32 bit Integer coprocessor• 2 UARTs, Int. Cont., 3 Timers, …• Crypto functions• 128KBytes/layer main memory

• Completely synthesized, placed and routed in 3D with standard Cadence tools. Runs slightly better than predicted by models and tools.

Tezzaron Semiconductor

R8051/Memory