SSEI Senior Design Project

Mark Steddom 1

SSEI Senior Design ProjectFPGA to USB Integration

Group Members:

Douglas Pace (CSE)

Norman Heath (CSE)

Mark Steddom (EE)

Nathan Ball (EE)

David Penick (EE)

Sponsor:

Kevin Daily of SSEI

Mark Steddom 2

Project OverviewDesign and Build a USB Interface Adaptor for the FPGA-eb1

P.C.

FPGA-eb1

USB

SSEI Bus [0:7]Power &Ground

Mark Steddom 3

Project OverviewDemonstrate the Power and Usefulness of the Product

P.C.

FPGA-eb1

USB


L.C.D.

G.P.S.GPS Bus [0:2]

LCD Bus [0:10]

Mark Steddom 4

Project OverviewDemonstrate the Power and Usefulness of the Product

P.C.

FPGA-eb1

USB


L.C.D.

G.P.S.GPS Bus [0:2]

LCD Bus [0:10]

Byte Blaster Parallel Interface

David Penick 5

Project Schedule

Firmware28 days 01/22/01 02/28/01

Device Driver33 days 01/22/01 03/07/01

FPGA_EB1 Development38 days 01/22/01 03/14/01

USB Hardware Device23 days 02/12/01 03/14/01

David Penick 6

Project Schedule cont.

Toy Development7 days 02/12/01 02/20/01

Application43 days 01/15/01 03/14/01

Integration8 days 03/15/01 03/26/01

Full Complete Systems Test10 days 03/27/01 04/09/01

David Penick 7

Integration Plan

USB chipsetFPGA codeFPGA to USBGPSLCD display

David Penick 8

Critical Path

Application

Integration & Test

VHDL

Device Driver

Firmware

Hardware

GPS

LCD

Capstone Conference

David Penick 9

Critical Path cont.

Firmware 2/28/01Device Driver 3/7/01

Tested with USB Interconnect

Hardware 3/14/01USB interconnect

David Penick 10

Critical Path cont.

VHDL 3/14/01FPGA_eb1 connected to USB interconnect

Toy 2/20/01GPS 2/20/01LCD 2/15/01

Application 3/14/01Map Display 3/2/01NMEA Decoder 2/2/01USB Driver Interface 2/27/01

David Penick 11

The “Toy”

GPS

LCD

USB CHIPEZ-USB

USB Host Controller

Device Driver

ApplicationPort

Portfpga_eb1

Demonstration Devices

David Penick 12

Toy

Motorola GT Plus OncoreOEMwill utilize 3 connections on the SPI connector of FPGA_eb1The GPS will support the NMEA (National Marine Electronics Association) protocol at 4800 baudMotorola binary protocol at 9600 baudSoftware selectable output rate (cont. or poll)

David Penick 13

NMEA

standard protocol used by GPS receivers to transmit dataoutput is EIA-422A, can consider it RS-232 compatible4800 bps, 8 data bits, no parity and one stop bit (8N1)sentences are all ASCII

David Penick 14

NMEA cont.

Each sentence begins with a dollar sign ($) and ends with a carriage return linefeed Data is comma delimitedAll commas must be included as they act as markersSome GPS do not send some of the fields

David Penick 15

Toy cont.

LCD Displaywill utilize 11 connections on the fpga_eb1 board The LCD screen will be black pixels on white background It will have a resolution of 640 by 480 pixels It allows for independent pixel drawing

David Penick 16

Toy cont.

Display data transferred in the form of two 4-bit parallel data through shift registersWhen the data of one line (640 pixels) has been inputted, it will be held automatically by the built-in LCD driver.

Nathan Ball 17

FPGA and VHDL

GPS

LCD

USB CHIPEZ-USB

USB Host Controller

Device Driver

ApplicationPort

Portfpga_eb1


Nathan Ball 18

VHDL• Max Plus II Baseline

– Graphical Editor– Text Editor (VHDL)– Floor-plan Editor– Wave-form Editor– Simulator

Nathan Ball 19

VHDL

Implements functions on an FPGAMakes use of subroutinesMakes use of previously defined functionsExtensive librariesParallel functionality

Nathan Ball 20

Graphical Implementation

Nathan Ball 21

VHDL CODE--vhdl code for AND2 gate

library IEEE;use IEEE.STD_LOGIC_1164.all;

entity AND2 isport ( Input_1, Input_2: in STD_LOGIC; Output_1 : out STD_LOGIC;);end AND2;

architecture V1 of AND2 isbegin Output_1 <= (Input_1 and Input_2);end V1;

Nathan Ball 22

Requirements

USB Interface –8 I/O lines GPS –Serial Data: 2 linesLCD –Parallel Data: 2 lines4 lines Unused

Toy InterfaceOut to GPS: 3 Lines - 2 Data, 1 GNDOut to LCD: 11 Lines - 2 CLK, 8 Data, 1 GND

Nathan Ball 23

Structure

Pipe Data

Parallelize Data

USBInterface

GPS Unit

FPGA

LCD Display

Nathan Ball 24

Paralellizing the Data

First Bit placed in lowest order bit of upper registerSecond Bit placed in lowest order bit of lower register

1 Data Line In => 8 Data Lines OutSent in on a Clock SignalSent out with 2 Clock Signals

Mark Steddom 25

The USB Interface

GPS

LCD

USB CHIPEZ-USB

USB Host Controller

Device Driver

ApplicationPort

Portfpga_eb1


Mark Steddom 26

USB Interface Adaptor

AN21XX

Mark Steddom 27


AN21XX

USB-B

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AN21XX

USB-B MAX882

Mark Steddom 29


AN21XX

USB-B MAX882

24LC00

Mark Steddom 30


AN21XX

USB-B MAX882

24LC00SN75240

Mark Steddom 31

Douglas Pace 32

Firmware and Device Driver

GPS

LCD

USB CHIPEZ-USB

USB Host Controller

Device Driver

ApplicationPort

Portfpga_eb1


Douglas Pace 33

Firmware and Driver Requirements

Must be compliant with the USB 1.1 Specification Document.Allow for bi-directional communication between a host computer and the fpga_eb1.

Douglas Pace 34

New Non-functional Requirements

Should be easy for the end user to develop applications and lab experiments.Provide the most versatile interface as possible.

Douglas Pace 35

Firmware and Device Driver

Must allow for bi-directional support between any application and the fpga_eb1.Must be easy to design applications and VHDL for the fpga_eb1.Should have the ability to utilize as many or as few of the I/O pins on the EZ-USB chipset as needed.

Douglas Pace 36

USB Basics

USB Communication all occurs between endpoints.These endpoints are device defined. The EZ-USB supports up to endpoint 15.There are 4 types of transfer types:

ISOBulkInterruptControl

Douglas Pace 37

USB Transfer Types

ISO or isochronous transfersData integrity not guaranteed.Data speed is always guaranteed.Packet sizes of up to 1023 bytes during each frame.

Bulk transfersData speed is not guaranteed.Utilizes all integrity checks available.Packet sizes are limited to 8,16,32,64 bytes.

Douglas Pace 38

Driver->Firmware Protocols

Utilize 5 endpoints other than the system defined endpoint 0.Endpoint 1 will be a bulk configuration endpoint.Endpoint 2 & 3 are bulk endpoints. 2 will be input, 3 output.Endpoint 8 & 9 will be ISO endpoints. 8 will be input, 9 output.

Douglas Pace 39

Packet Identifier

1 byte

I/O PinNumber

1 byte

Input / Output1 byte

Serial (0) orParallel (1)

1 byte

Extra Info: Interrupt line to link for Parallel or timer length for Serial

4 bytes

Endpoint 1 will accept 8 byte long packets.

Firmware Protocol Cont.

Douglas Pace 40

Firmware Protocol Cont.Endpoints 2,3,8,9 will utilize 64 byte packets.

I/O Line1 byte

Number ofBytes1 byte

Data62 bytes

Douglas Pace 41

Firmware->FPGA Protocol

As we have already seen, the firmware will allow both serial and parallel data loads to the fpga.This will be done using strictly timed data reads or dumps, or using an external interrupt line as the clock for parallel data.This will allow a versatile system that allows for multiple styles of data transfer.

Douglas Pace 42

Driver

Driver will attempt to maintain data integrity by only allowing a single application access to the USB device at a time.Driver will format packets using specific functions, allowing simple and rapid application development.

Norman Heath 43

The Application

GPS

LCD

USB CHIPEZ-USB

USB Host Controller

Device Driver

ApplicationPort

Portfpga_eb1


Norman Heath 44

Application Requirements

It must communicate with the fpga via the USB driver and interconnect.It will display a topographical map and relevant information from the GPS unit.

Norman Heath 45

Design Methodology

We are using an incremental model approach in the design and implementation of the application.We will add features to the application during the rest of design and implementation.

Norman Heath 46

Why use an Incremental approach

A thorough set of requirements was never specified for the application.This will allow us to have a functioning program for the rest of the project.We can show what we have to anyone and they can make suggestions at anytime.It almost guarantees a functioning application when the project is over.

Norman Heath 47

Application Design

The design of the application centers around the follow:It will gather information from a GPS unit through the USB driver and device interconnect.It will display this information to the user by using a topographical map and textual/graphical feedback.

Norman Heath 48

Application Design

One of its capabilites is:It allows the user to import a compressed or uncompressed .bmp file representing a map.

It then allows the user to configure a settings file for that map. These settings are persistent (they remain after the application is terminated).

Norman Heath 49

Configuring a map

Norman Heath 50

Application Design

Other capabilitiesAt any time it allows users to display any maps they have previously loaded and setup. As GPS location coordinates transition off a map, it will prompt the user to select another map that has coordinates that are in range of the current latitude and longitude.

Norman Heath 51

Application DesignKey Components of the Application

Simulator GPS - USB

Interface

Model ViewObservable Observer

Norman Heath 52

Questions?

Team SSEI_FPGA2USB

Documents

SSEI Senior Design Project