SOC Introduction - 國立臺灣大學

SoCIntroduction2020/7/23

Outline

• Introduce to SoC

• SoC design methodologies

• SoC components

• ARM SoC platform

Media IC & System Lab 2

Reference

簡韶逸老師 MSoC Course:

http://media.ee.ntu.edu.tw/courses/msoc/slide.html


http://media.ee.ntu.edu.tw/courses/msoc/slide.html

Outline



• SoC components



What is SoC ?

• System-on-a-Chip


Why System-on-a-Chip ?

Yesterday

• HW only

• Perfect interconnection

Today

• Heterogeneous

• CPU + dedicated HW

• Multiple SW stacks

• Non perfect interconnect


SoC Example - Smartphone Processor

• Snapdradon 845


Outline



• SoC component

• ARM SoC Platform


Design and Verification Step

Actually, the

major problem

is Verivication


Typical SOC design flow

• Overlap in specification/architecture phase and RTL-design phase; multiple design changes

• Architecture design done informally

• SW development starting late in the project


Verification at the Backend


Top-Down Design Flow (RMM)


Platform Based Design

• Platform

• An integrated and managed set of common features, upon which a set of products or product family can be built. A platform is a virtual component (VC).

• Platform-based design

• An integration oriented design approach emphasizing systematic reuse, for developing complex products based upon platforms and compatible hardware and software VCs, intended to reduce development risks, costs, and time to market.


Platform Based Design


Electronic System-Level (ESL) Design

• A set of methodologies that enables SoC engineers to efficiently develop, optimize and verify complex system architectures and embedded software

• The foundation for the continuously verifying downstream register-transfer level (RTL) implementation and subsequent software development


Emerging SoC Design Flow


ESL: New SOC Design Flow

• Architecture closure

• Achieve a reduction # of RTL iterations

• Can perform concurrent HW and SW design

• Shorten the time it takes to get to golden RTL


Outline



• SoC component

• ARM SoC Platform


Processors

• The architecture of the computation engine used to implement a system’s desired functionality

• Processor does not have to be programmable


Processors - example

• Processors vary in their customization for the problem at hand


Why General-Purpose Processorsin SoCs?

• Using microprocessors is a very efficient way to implement digital systems

• Microprocessors make it easier to design families of products that can be built to provide various feature sets and can be extended to provide new features

Datapath is general

Control unit configures the

datapath perations

Control unit doesn’t store

the algorithm, the algorithm

is “programmed” into the

memory


Memory

• Stores large number of bits• m x n: m words of n bits each

• k = Log2(m) address input signals

• m = 2^k words

• e.g., 4,096 x 8 memory:

• 32,768 bits

• 12 address input signals

• 8 input/output data signals

• Memory access• r/w: selects read or write

• Enable: read or write only when asserted

• Multiport: multiple accesses to different locations simultaneously


Peripherals and I/O Devices

• Peripherals are often single-purpose processors

• Custom single-purpose processors

• Standard single-purpose processors

• serial transmission

• analog/digital conversions

• I/O peripherals are the communication channels between the SoC and the real-world

• The functions of an SoC determines the requirements of peripherals


Various Kinds of Peripherals

• System• Timers

• Counters

• Watchdog timers

• Real-time clocks

• Serial I/F• UART

• I2C

• I2S

• SPI

• FireWire

• USB

• Thunderbolt

• A/D and D/A converters

• GPIO

• Functional • Display I/F

• Image sensor I/F

• Keypad controllers

• Pulse width modulators (PWM)

• Stepper motor controllers

• Communication peripherals

• ……

• MIPI


GPIO

• GPIO (General-Purpose Input/Output)

• Very useful for

• Debugging

• Extend the I/O function of the system

• Can be used for multiple purposes


The Block Diagram of GPIO


More Complex GPIO


Interfacing

• In a system, various subsystems must have interfaces to one another.

• The bus serves as a shared communication link between subsystems.

• Advantages

• Low cost

• Versatility

• Disadvantage

• Performance bottleneck


Bus

• Wire• Uni-directional or bi-directional

• One line may represent multiple wires

• Bus

• Set of wires with a single functionAddress bus, data bus …

• Or, entire collection of wiresAddress, data and control

• Associated protocol• rules for communication


Outline



• SoC components



ARM SoC Platform

• Platform based design

• Hardware

• ARM

• AMBA

• Software

• OS and RTOS

• Software development model (SDM)

• Instruction set simulator (ISS)

• Development tools

• RealView developer suite

• RealView ICE and Trace

• Hardware platform


AMBAARM SoC platform


AMBA

• Advanced Microcontroller Bus Architecture

• An on-chip communication standard

• Three buses defined

• AHB (Advanced High-performance Bus)

• ASB (Advanced System Bus)

• APB (Advanced Peripheral Bus)


AHB Components

• AHB master• Initiate a read/write operation

• Only one master is allowed to use the bus

• uP, DMA, DSP, …

• AHB slave• Respond to a read/write operation

• Address mapping

• External memory I/F, APB bridge, internal memory, …

• AHB arbiter• Ensure that which master is active

• Arbitration algorithm is not defined in ABMA spec.

• AHB decoder• Decode the address and generate select signal to slaves


AHB Bus InterconnectionInitiate a request

to arbiter

Drives address

and control signal

Grants the bus

ownership to the master

Address & control broadcasted to all slaves,

only the selected slave response

Drive the HREADY signal

high for completion


AHB Signals Name Source Description

HCLK Clock source Bus clock

HRESETn Reset controller Reset

HADDR[31:0] Master Address bus

TRANS[1:0] Master Transfer type

HWRITE Master Transfer direction

HSIZE[2:0] Master Transfer size

HBURST[2:0] Master Burst type

HPROT[3:0] Master Protection control

HWDATA[31:0] Master Write data bus

HSELx Decoder Slave select

HRDATA[31:0] Slave Read data bus

HREADY Slave Transfer done

HRESP[1:0] Slave Transfer response (status)Media IC & System Lab 37

Basic AHB Transfers

• Two distinct sections

• The address phase, only one cycle

• The data phase, may require several cycles, achieved by HREADY signals

• Pipeline transaction

• Address phase is before the data phase


Basic AHB Transfers - Example 1

• A simple transfer with two wait states


Basic AHB Transfers - Example 2

• Multiple transfers


Burst Operation

• AHB burst operations

• 4-beat, 8-beat, 16-beat, single transfer, and undefined-length transfer

• Both incrementing & wrapping burst

• Incrementing burst

• Sequential, the address is just the increment of the previous one

• Wrapping burst

• If the start address is not aligned (size x beats), the address will wrap when the boundary is reached

• Ex: 4-beat wrapping burst of word (4-byte):0x34→0x38 → 0x3C → 0x30


Address Calculation Example

• The address calculation is according to HSIZE and HBURST

• Example: HSIZE = 010 (32 bits) with starting address = 0x48

HBURST Type Address

000 SINGLE 0x48

001 INCR 0x48, 0x4C, 0x50,…

010 WRAP4 0x48, 0x4C, 0x40, 0x44

011 INCR4 0x48, 0x4C, 0x50, 0x54

100 WRAP8 0x48, 0x4C, 0x50, 0x54, 0x58, 0x5c, 0x40, 0x44

101 INCR8 0x48, 0x4C, 0x50, 0x54, 0x58, 0x5c, 0x60, 0x64

110 WRAP16 0x48, 0x4C,…, 0x7c, 0x40, 0x44

111 INCR16 0x48, 0x4C,…, 0x7c, 0x80, 0x84

The most useful


Important!!

• Burst transfer can’t cross the 1K boundary• Because the minimal address range for a slave is 1 KB

• NONSEQ → SEQ → 1KB Boundary → NONSEQ → SEQ…

• The master should not attempt to start a fixed-length incrementing burst which would cause this boundary to be crossed


AXI

• Advanced eXtensible Interface

• Burst-based transactions

• Each transaction has address and controlinformation on address channel that describes the nature of the data to be transferred

• Five channels

• read address channels

• write address channels

• read data channel

• write data channel

• write response channel


Channel architecture of reads


Channel architecture of writes


Example: Read Burst


Example: Overlapping Read Burst


Example: Write Burst


Transaction Ordering

• Enables out-of-order transaction completion

• Give an ID tag to every transaction

• Transaction with the same ID → in-order

• Transaction with different ID → can be completed out-of-order

• The ID tag is similar to a master number, but each master can implement multiple virtual masters by supplying different ID tags (virtual master number)


Communications between Different IPsARM SoC platform


Memory Mapped I/O

• Each slave occupies a range of (>1KB) address space in the system

• All the slaves are addressable

• Memory mapped register/memory

• CPU/IP and read/write data to other IP as read/write data from/to memory


Communications between IPs

• After the master is granted by the arbiter, it can access all the slaves on the bus


Communication between CPU and IP

• CPU is always the master

• The IP is always the slave

• The IP can initiate the feedback with interrupt

• After interrupt, the CPU enters interrupt mode, and the interrupt is handled with interrupt service routine (ISR)


Example: DMA


Example: DMA

• Step 0: CPU check the status of DMA to make sure it is ready to be used

While(1)

{

Read(0x30004, &status)

if(status == 0)

break;

}


Example: DMA

• Step 1: CPU sets the (source address), (destination address), and (size) with the slave I/F

Write(0x30008, 0x10000)

Write(0x3000C, 0x20000)

Write(0x30010, 0x100)

• Step 2: starts DMA

Write(0x30000, 0x1)


Example: DMA

• Step 3: DMA moves data from memory 1 to memory 2 with the two master I/F


Example: DMA

• Step 4: DMA interrupts CPU

• Step 5: CPU checks the status of DMA

Read(0x30004, &status)


Example:


• big.LITTLE Processing Architecture

Documents

SOC Introduction - 國立臺灣大學