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SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC. 1. System and Irradiation Tests on the GOL chip. 2. LoC (link on chip) development based on SoS technology.

SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

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SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC. System and Irradiation Tests on the GOL chip. LoC (link on chip) development based on SoS technology. GOL chip. - PowerPoint PPT Presentation

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Page 1: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

SMU ActivitiesJingbo Ye

May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC.

1. System and Irradiation Tests on the GOL chip.

2. LoC (link on chip) development based on SoS technology.

Page 2: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

GOL chip

• GOL: 1.6 Gbps serializer + laser driver in one chip, 0.5m CMOS technology with radiation tolerant layout. Works with HDMP-1024 and TLK2501 as deserializer.

• System tests carried out by CERN and experiments that plan to use this chip.

• Irradiation tests so far: 10 Mrad(SiO2) with 10KeV X-rays, 3.14×1012p/cm2, 60MeV proton, no SEU observed.

Page 3: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

• System test:– GOL clock jitter tolerance with HDMP-1024 or

TLK2501 as deserializer. – GOL clock jitter conversion from the reference clock

to the serial data stream.– GOL driving characteristics with a VCSEL and with an

Edge Emitting Laser.• Irradiation test:

– 200 MeV proton with fluences up to 1015 – 1016 p/cm2.– Co-60 gamma, if necessary to 50 Mrads.

• We plan to carry out these tests in year 05 and 06.

System and Irradiation tests of the GOL chip planned at SMU

Page 4: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Optical Data Links using CMOS Silicon-on-Sapphire (SoS)

Technology

Ping Gui, Jingbo Ye, Ryszard Stroynowski

Southern Methodist University

March 07, 2005

For the LoC development, let me borrow a presentation we made at Nevis.

Page 5: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Outline

• Silicon-on-Sapphire technology

• CMOS Transceiver IC Design Experience

• Proposed single-chip approach

Page 6: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

N-channel FETP-channel FET

Insulating sapphire substrate

Bulk CMOS Process

UTSi Process

(a)

(b)

sio2

N-channel FETP-channel FET

Insulating sapphire substrate

Bulk CMOS Process

UTSi Process

(a)

(b)

sio2

200 m

100 nm

Peregrine’s Silicon-on-Sapphire (SoS) Ultra-Thin-Silicon-on-insulator (UTSi) Technology

• Considered to be radiation hard– No latch-up

• Reduced Parasitic capacitance

• High performance• Low Power consumption• Minimum crosstalk• Higher level integration• Allow for compact and

simple integration with optical devices– Substrate is transparent

• Widely used in RF and space products

Page 7: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Flipped OE devices on UTSi substrate

transparent sapphire substrate(UTSi)

active CMOS layer

quad PIN array

flip chip attachment

quad VCSEL array

UTSi integrated photo detector

MMF ribbon fiber

VCSEL driver circuitry receiver circuitry

UTSi integrated circuitry

200 um

• Flip-chip bonding of OE devices to CMOS on sapphire– No wire-bonds – package performance scales to higher data rates

– Rugged and compact package

Page 8: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Peregrine Space Product 4+4 Transceiver

15 mm height Berg MegArray PCB socket

MTP Connector Module • 0.5-um UTSi SoS

• Single 4+4 transceiver component with variable data rates (CML interface)

– Minimum data rate – 10 Mbps– Maximum data rate – 2.7 Gbps per channel

• Radiation– Total Ionizing Dose: 100 kRad(Si)– SEU: > 20 MeV-cm2/mg

• 15 year operational lifetime

• 125 mW per channel power consumption (dissipated to panel mount)

• Vibration– 15.33 gRMS for 3 minutes total

Page 9: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

SoS CMOS v.s. Bulk CMOS0.25 m SoS (UTSi) 0.13 m Bulk CMOS

Performance 10 GHz 10 GHz

Leakage Current Substrate as an insulator (1014

ohm/m at room temperature). Reduced substrate junction capacitance leads to lower leakage current.

High Leakage current

Power Dissipation Reduced parasitic capacitance also leads to a lower power dissipation

Crosstalk Minimum crosstalk due to reduced substrate capacitance

Substrate noise causes crosstalk between channels

Cost $100k for wafer mask set;

$1000 per wafer

$800k for wafer mask set;

$800 per wafer

Page 10: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

CMOS IC design experience

Page 11: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

IC Design using UTSi technology

IC 1 (2001) IC 2 (2002) IC 3 (2003)

Performance:4-channel optoelectronic transceiver 0.6Gb/s

Performance:4-channel optoelectronic transceiver 2-3Gb/s

Performance:4-channel optoelectronic transceiver 3-4Gb/s

Innovation:Double Data Rate transceiver

Innovation:Instant power-up/down

Innovation:Dual-rate(power-performance trade off)

0.5 m CMOS Silicon-on-Sapphire Technology

DARPA OE-center DARPA PCA/RATS DARPA C2OI

Page 12: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

ASIC 1:Source Synchronous Double Data Rate Transceiver

(a) Chip microphotography

1*4 PD array& receiver ckt

1*4 VCSEL array& driver circuit.

Transmitter digital circuits

Receiver digital circuits

Dout(15:8)

Din(7:0)8:1

serializer

8:1serializer

1:8deserializer

1:8deserializer

VCSELdriver

Photo Detectdata1

data2clock2

clock1Din(15:8)

transmitter receiver

Dout(7:0)

ClkOut (78MHz)ClkIn (78MHz)

clk4x (311MHz)

4 optical linkeach at 622Mbp/s

(b) chip architecture

Features:

•Source synchronous design; clock is sent along with data over the optical channels•No-PLL based clock recovery

circuits are needed. •Efficient channel use by Double Data Rate(DDR) •Scalable to multiple channels•Adjustable transmitter power and receiver gain•Fully tested at 0.6Gbps per channel•Data rate limited by CMOS I/O

Page 13: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

ASIC2: Parallel Optical Links with instant power-up/down capability

•Channel is able to power-down/up within 3 nanoseconds•Individual power-down control for every channel •adjustable bias and modulation current controlled by on-chip digital registers•Data rate at 2.5Gbps

CML IN CMLOUT

Ch 1

Ch 2

Ch 3

Ch 4

Ch 1

Ch 2

Ch 3

Ch 4

Drv

Drv

Drv

Drv

Driver ckt. & VCSELs PD & Receiver

TX Power on RX Power on

Page 14: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

System Integration

Xilinx FGPAcontroller

Free-space optical Link

4 x1 TX ICHybrid COB

FR4 mother-board

4 x 1 RX ICHybrid COB

GHz bypassconnectors

Gigabit test-bed

front view of the CMOS chip with PIN Back view of the CMOS chip with VCSEL

Page 15: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Measurement Results

2-Gb/s

2.5-Gb/s 3-Gb/s

Page 16: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Instant On/off optical link demonstration

2-Gbps VCSEL power-on/off eye 2-Gbps link (tx+rx) power-on/off eye

PWR_ON_SIGNAL

PWR_OFF_SIGNAL

500ps

Page 17: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Link Performance for Continuous Operation

(a) Normal operation (b) At worst case scenario

Eye diagrams:Link eye diagram measured after 11 hours of operation @ 2-Gbps

BER measurement:No errors after running for 11 hours continuously.Bit Error Rate < 1E-14

Page 18: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Recent Design submission using 0.25um Technology

• Free fabrication and flip-chip bonding service– Sponsored by OIDA/PTAP

program

• Two types of Driver circuits designed– VCSEL driver circuit– GSE driver circuit

• GDS submitted on 02/08/05• Non-gold bumped die shipped on 05/31/05• Gold bumped die shipped on 06/20/05• Flip-chip bonded OE devices shipped on 07/15/05

Page 19: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Simulation Results• GSE driver

– 6.25-Gbps/channel– Bias: up to 40mA– Modulation current: 40 mA

• VCSEL driver – 15-Gb/s/channel– Bias: ~ 1mA– Modulation:~ 5mA

160ps

60ps

• Data rate can be pushed higher by using– inductors peaking

Page 20: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Proposed Single-chip Approach--

integrating SerDes, Transceiver and OE Devices

Photonic

PIN

VCSEL Driver seriliazer encoder

Flip-chipbonding

10G Transceiver Module

TX

TIA/LADe-

seriliazerDecoder

RXParallel Data

RXREGclock

Parallel Data

REFclock

clock is embedded in the serial data stream

Optical data

• Improve performance– No off-chip high speed lines– Flip-chip bonding reduce capacitance and inductance

• Reduce power consumption– No 50-Ohm transmission lines between chips

Clock/Data recovery

PLL

Page 21: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Support from Peregrine

• Peregrine is highly interested in collaboration

• We have access to their advanced fabrication technology– $30k for 3mmx3mm MPR– $15k for Flip-chip bonding service

• Technical Support

Page 22: SMU Activities Jingbo Ye May 9, 2005, CERN, for Opto-Electronics Readout Systems for SLHC

Q & A

Thank you !