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F. MalobertiDATA CONVERTERS Springer2007
Chapter 2
DATA CONVERTER SPECIFICATIONSF. MalobertiDATA CONVERTERS Springer2007
Chapter 2
DATA CONVERTER SPECIFICATIONS0
Slide Set
Data Converters
—————————
Data Converter Specifications
F. MalobertiDATA CONVERTERS Springer2007
Chapter 2
DATA CONVERTER SPECIFICATIONSF. MalobertiDATA CONVERTERS Springer2007
Chapter 2
DATA CONVERTER SPECIFICATIONSF. MalobertiDATA CONVERTERS Springer2007
Chapter 2
DATA CONVERTER SPECIFICATIONS
F. MalobertiDATA CONVERTERS Springer2007
Chapter 2
DATA CONVERTER SPECIFICATIONSF. MalobertiDATA CONVERTERS Springer2007
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DATA CONVERTER SPECIFICATIONS1
SummaryType of Converter
Conditions of Operation
Converter Specifications
Static Specifications
Dynamic Specifications
Digital and Switching Specifications
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DATA CONVERTER SPECIFICATIONS
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Type of Converter
The conversion algorithm normally provides this kind of information. Forexample, we have flash, sub-ranging, or sigma-delta converters.
Converters are divided in: Nyquist-rate and Oversampling.? Using an input that occupies a large fraction of the available bandwidth.? Using an input-band that only occupies a small part of the Nyquist range
The ratio between the Nyquist limit and the signal band, fs/(2fB), is calledoversampling ratio (OSR). Converters with a large OSR are called over-sampling converter, whereas Nyquist-rate converters have a small OSR,typically less than 8.
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Nyquist-rate and Oversampling
Anti-aliasingtransition band Anti-aliasing
transition band
fs/2 fs fs/2 fs
fs/2 fs fs/2 fs
fB
D2/12D2/b12
fB
f'B
b=fs/2 fB
D2/12
b'=fs/2 f'B
b'D2/ 12vn2 vn
2
vin vin
(a) (b)
f
f
f
f
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Conditions of Operation
The behavior of a data converter strongly depends on the experimentalset-upand the operational environment that influence the performance.
? Supply voltage: should be allowed to fluctuate by 5% or even more
? Temperature: should be from−20◦C to 85◦C (consumer applications) or−55◦C
to 125◦C (military applications)
Maintaining performance over a wide range of supply voltage or temper-ature is difficult especially for high resolution devices. For example, a 14-bit converter requires accuracies as good as 600ppm/V (5V supply) or0.3ppm/◦C (consumer applications).
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For the testing and characterization ....
Keep Note
The operational conditionsof data converters are keyfor achieving (or measuring)specifications. Inaccurateset-up or PCB limits can to-tally mask the excellent per-formances of a device.
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PCB Design
The printed circuit board (PCB) is an important element for not hamperingthe results.
Hints
? Connect the separate pins for analog and digital supplies to the singlewell filtered supply generator on the PCB.
? Obtain good VDD or ground terminations by minimizing the length ofthe connecting leads and PCB paths.
? Avoid ground loops between two sides of the PCB, especially for RFfrequencies.
? Ensure high-level signal integrity with multi-layer boards with separateground and power planes.
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PCB Design (ii)? Carefully control the routing of master clock and reference voltages
through the PCB.
? Use signal generators with low jitter but also preserve the feature inthe phase generator.
? The PCB traces leading the clock must be short with a solid groundplane underneath for forming a microstrip transmission line and en-ables impedance matching.
? When low-speed data converters use external references utilize a cleanvoltage generator whose output impedance is low enough to avoid in-ternal fluctuations greater than 1 LSB.
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Converter Specifications
Specifications are used to interpret and understand the material in Cata-logues and to facilitate the use and characterization of products.
The specifications are divided into the following classes:
? General features.
? Static specifications.
? Dynamic specifications.
? Digital and switching specifications.
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General Features
Type of Analog Signals
Resolution
Dynamic range
Absolute maximum ratings
ESD (electrostatic discharge) notice
Pin function descriptions and pin configuration
Warm-up time
Drift
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Static Specifications: input-output characteristics
0.....000
0.....001
0.....010
0.....011
0.....100
0.....101
Digital Output
Analog Input
0 D 2 D 3 D 4 D 5 D
Step width (1 LSB=D)
3.5 - 4.5
Midstep
01 2 3 4 5
QuantizationError
Quantization interval (± 1/2 LSB)
+1/2LSB
-1/2LSB
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Static Specifications: Possible non-idealities
000
001
010
011
100
101
1 2 3 4 50 6
110
111
7
000
001
010
011
100
101
1 2 3 4 50 6
110
111
7
(a) (b)
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Static Specifications
Analog Resolution
Analog Input Range
Offset
Zero Scale Offset
Common-mode Error
Full-scale Error
Bipolar Zero Offset
Gain error
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Static Specifications: Measuring offset
0...0010
Digital Output
Analog Input
0 2 4 6 8 10
0...0001
0...0100
0...0011
0...0110
0...0101
0...1000
0...0111
0...1010
0...1001
IdealTransfer
characterisitc
Transfercharacteristic
with Offset
Offset
01
00...
0
10
00...
0
00
10...
0
11
00...
0
01
10...
0
10
10...
0
00
01...
0
11
10...
0
10
01...
0
IdealDAC
Response
RealDAC
Response
OffsetDigital Input
Analog Output
00
00...
0
(a) (b)
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Static Specifications: Measuring the gain error
0...0010
Digital Output
Analog Input
0 2 4 6 8 10
0...0001
0...0100
0...0011
0...0110
0...0101
0...1000
0...0111
0...1010
0...1001
IdealTransfer
characterisitc
Transfercharacteristic
with Gain Error
01
00...
0
10
00...
0
00
10...
0
11
00...
0
01
10...
0
10
10...
0
00
01...
0
11
10...
0
10
01...
0
RealDAC
Response
Digital Input
Analog Output
00
00...
0
(a) (b)
DACinterpolating
line
Differentslopes
Differentslopes
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Differential non-linearity error (DNL)
DNL(k) =∆r(k)−∆
∆(1)
1
0.8
0.6
0.4
0.3
0
–0.2
–0.4
–0.6
–0.8
–1
Code
0 1024 2048 3072 4096
)B
SL(
LN
D
DNLRMS ={
1
2N − 2
2N−2∑1
[DNL(k)]2}1/2
(2)
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Static Specifications (cont.)
Monotonicity
Hysteresis
Missing code
Integral non-linearity (INL): is a measure of the deviation of the trans-fer function from the ideal interpolating line. Another definition of theintegral non-linearity measures the deviation from the endpoint-fit linefor correcting the gain and offset error. The second definition is cho-sen as standard since it is more informative for estimating harmonicdistortion.
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Static Specifications (cont.)
3
2
1
0
–1
–2
–3
)BSL( LNI
Code0 1024 2048 3072 4096
3
2
1
0
–1
–2
–3
)BSL( LNI
Code0 1024 2048 3072 4096
INL plot according to the two different definitions
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Static Specifications: endpoint-fit line INL
An iterative use of (2) gives the transition point between codes after cor-rection, X ′(k)
X ′(k) = ∆′{kos +
k∑1
DNL(i)}
(3)
Where ∆′ = ∆(1 + G); G gain error; kos is the offset measured in LSB.The offset compensated for the endpoint-fit line is kos∆′. The INL inLSB becomes
INL(k) =X ′(k)− k∆′
∆= (1 + G)
k∑i=1
DNL(i) (4)
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Static Specifications: Modeling INL and DNL
Sy=f(x)
Correlated INLS
eQ eINL,uncorr
XinDigitalOutput
ADC
y
Observe
ADCs with large integral non-linearity show harmonic distortion. Largedifferential non-linearities lead to INL with large random components.The resulting noise is added to the quantization and degrades theSNR.
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Static Specifications Example: INL and harmonic distortionRandom variation of the INL is within ±0.45. Correlated variation described by
y = x + ax2 + bx3 + cx4; x = (n− 2N−1)/2N (5)
a = −0.01, b = 0.01 and c = 0.02
0 500 1000 1500 2000 2500 3000 3500 4000 4500−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4INL
0 500 1000 1500 2000 2500 3000 3500 4000 4500−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5DNL
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0 100 200 300 400 500 600 700 800 900 1000−120
−100
−80
−60
−40
−20
0Reference Spectrum [DB]
0 100 200 300 400 500 600 700 800 900 1000−120
−100
−80
−60
−40
−20
0Spectrum of Signal with INL [dB]
Signal used: 12-bit quantized, 61 periods sine wave (sequence of 212
samples). Average noise floor: −107.1 dB = SNR = 74 dB + pro-cessing gain, 33.1 dB.
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Static Specifications (cont.)
Power Dissipation
Temperature ranges
Thermal Resistance
Lead Temperature
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Dynamic Specifications
Frequency response and speed of the analog components of a data con-verter determine the dynamic performance.
The specifications either correspond to defined dynamic conditions or aregiven as a function of frequency, time, or conversion data-rate.
Analog Input Bandwidth
Load Regulation or Output Impedance
Settling-time
Cross-talk
Aperture uncertainty (Clock Jitter)
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Digital to Analog Glitch Impulse
Equivalent input referred noise
Vin= ·VFS
x x+1 x+2 x+3x-1x-3 x-2
0.63 LSB
DigitalCode
2N
x
Estimation of the input referred noise: histogram method with dc input.
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SNR
INPUT FREQUENCY – Hz
70
65
30100K 100M1M 10M
60
55
35
50
45
40
Bd
–R
NS
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
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Typical SNR versus the input amplitude (sigma-delta converters).
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Signal-to-Noise-and-Distortion Ratio (SINAD or SNDR)
INPUT FREQUENCY – Hz
70
65
30100K 100M1M 10M
60
55
35
50
45
40
Bd
–S
INA
D
–0.5 AMPLITUDE
–6.0 AMPLITUDE
–20.0 AMPLITUDE
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(DR)
Equivalent input referred noise
(Effective-Number-of-Bits (ENOB))
ENOB =SINADdB − 1.76
6.02(6)
(Harmonic Distortion (HD))
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fin – MHz
–60
0 50
cB
d
100 150 200 250
–65
–70
–75
–80
–85
–90
–95
2-ND HARMONIC
3-RD HARMONIC
WORST OTHER
1-st 2-nd 3-rd 4-th 5-th
Vin= -1 dBFS
Harmonic components as a function of the input frequency.
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Example: Harmonic tones
0 1000 2000 3000 4000 5000 6000 7000 8000 9000−180
−160
−140
−120
−100
−80
−60
−40
−20
0
23
45
67 8
910
Input
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0 1000 2000 3000 4000 5000 6000 7000 8000 9000−180
−160
−140
−120
−100
−80
−60
−40
−20
0
23
78
6 45
109
Input
Input frequency at 1.711 kHz (sampling frequency 16.38 kHz)
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Dynamic Specifications (cont.)
Total Spurious Distortion (TSD): is the the root-sum-square of thespurious components in the spectral output of the ADC. The input is apure sine wave input of specified amplitude and frequency.
Spurious Free Dynamic Range (SFDR): is the ratio of the root-mean-square signal amplitude to the root-mean-square value of the highestspurious spectral component in the first Nyquist zone. The SFDR fo-cuses on the worst tone.
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0 2M 4M 6M 8M−160
−140
−120
−100
−80
−60
−40
−20
0
Signal
Spur
SFDR=85 dBBig Channel0 dB
Small Channel-90 dB
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INPUT – dBFS
0–90
RDFS
–Bd
10
20
30
40
50
60
70
fS = 80 MSPSfIN = 60.2MHz
SFDR – dBc
SFDR – dBFS
80
90
100
110
–80 –70 –60 –50 –40 –30 –20 –10 0
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Intermodulation Distortion (IMD): accounts for spur tones caused bynon-linearity when the input is a complex signal. This non-linearity ofa data converter causes the mixing of the spectral components thusgenerating spurs at sum and difference frequencies for all possibleinteger multiples of the input frequency tones.
Two tone Intermodulation Distortion (IMD2): is the ratio of the rmsvalue of either input tone to the rms value of the worst third orderintermodulation product reported in dBc. The input is made by twoclosely spaced tonesf1 and f2. Often the specification accounts forthe third order spurs only, which occur at (2f1− f2), (2f2− f1). Thereason for considering third order terms only is that they are close tothe input frequencies f1
∼= f2. Other intermodulation terms are faraway from the input and can be filtered out in the digital domain.
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Example: IMD
The distortion is described by a non-linear block before the quantizationy = x + 10− 4x3.
0
-20
-40
-60
-80
-100
-1201k 2k 3k 4k
f1
2f1-f2
f2
2f2-f13f1 3f2
2f1+f2 2f2+f1
Frequency
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Dynamic Specifications (cont.)
Multi-Tone Power Ratio (MTPR): is specific for data converters usedin communication systems. It defines the distortion of multi-tone trans-mission systems.
Noise-power ratio (NPR): similar to the MTPR it describes the linearperformances of an ADC used in frequency division multiplexed (FDM)links. NPR is a parameter which is usually used to describe poweramplifiers but the same concept is also used for data converters.
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0
-20
-40
-60
-80
-100
-120
NPR = 58 dB
Frequency [MHz]0 2 4 6 8 10
Inpu
t Pow
er/F
ull s
cale
[dB
] 12-bit ADCfck=40 MHz
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70
60
50
40
30
0-10-20-30-40-50RMS Input/ VFS [dB]
NP
R [d
B]
12-b
it
11-b
it10
-bit
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Effective Resolution Bandwidth (ERBW): is defined as the analoginput frequency at which the SINAD drops by 3 dB compared to its lowfrequency value.
Figure of Merit (FoM): is a parameter used to measure the powereffectiveness of an ADC.
FoM =PTot
2ENB2 ·BW(7)
In some cases the number of bits replaces the ENB or the ERBW isused instead of BW. Other definitions use the clock frequency and notthe signal band (for Nyquist-rate converters.)
Effective solutions show an FoM well below 1pJ/conv-step.
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About the power figure of merit ...
Remember that
The figure of merit is not asolid parameter as it dependson the technology line-width,signal bandwidth and numberof bits. Nevertheless, useit anyway for assessing thethe power effectiveness of theconverter.
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Digital and Switching Specifications
Logic levels: are the set of non overlapping ranges of amplitudesused to represent the logic state.
Encode or clock rate: is the range of possible encode rates that en-sures the performances of the specifications. It is best to operate adata converter using a maximum clock rate of about 25% of the maxi-mum guaranteed by the specification.
Clock timing: specifies the features of the clock. The information isnormally given using a diagram. The external clock is normally regen-erated at the input with edge-triggered flip-flops that latch the input onthe rising or the falling edge. The clock duty cycle can be chosen arbi-trarily under some constraints. A 50% duty cycle is normally the bestfor optimum dynamic performances.
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Clock Source
Circuits requiring a very low jitter generate the clock using a differen-tial input sine wave. A crystal clock oscillator (with or without externalfilters) obtains the input sine wave. This ensures sine wave purity andprovides accurate zero-crossing times. Internal amplifiers, under sat-uration, are used to square the input sine wave and thus generate theinternal clock.
Sleep Mode
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Wrap-up
Using or designing a data converter requires a proper understanding of itsspecifications.
We have seen how specifications describe the features and limits of thestatic and dynamic operation of data converters.
In this chapter we have also studied the basic elements for evaluating andcomparing existing devices. Furthermore, the given elements help in thechoice of the appropriate data converters for a given mixed system.
The technical terms used in manufacturer-supplied specifications shouldbe now clear.
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