Sistemi Elettronici Programmabili

Sistemi Elettronici Programmabili 9-1

Sistemi Elettronici Programmabili

ST7

Generalità e core


THE ST7 VISION

FLASH MEMORY

EMC/LOW POWER

ANALOG DIGITAL

SUPPORT

STMDEVELOPMENT

TOOLS

3rd PARTYDEVELOPMENT

TOOLS

SERVICE

ST7Core


Well-known Industry Standard 8-bit CISC architecture (Von Neuman)

compatible with most popular cores200 ns minimum instruction time

with 1.375µs 8x8 multiplication

64 KBytes linear addressing memoryIndirect and Y index memory accessDirect STACK management

And many powerful added features ...

THE ST7 CORE

ROM/EPROMup to 60 KBytes

INTERRUPTS& RESETVECTORS

$FFE0

$FFFF

RESERVED

STACK

PERIPHERALS HARDWARE REGISTERS

$00

RAM

$80

$0200

$1000


FLASH eFLASH Data EEPROM capable Flash

STM A KEY PLAYER INFLASH MEMORY

A VOLUME SUPPLIERMicros with embedded non-volatile memory have been in high volume production

since 1998Non-volatile memory products : 1 Billion units sold in 1998

MASTERING EMBEDDED FLASH SOLUTIONS Very high reliability with 20 year retention

Two solutions for cost vs. feature optimization


ST7 FLASH : IN SITU PROGRAMMING WITH HIGH PROTECTION

Patented high protection level on Flash, OTP and ROM versions

Piracy protectionUnexpected writing protection

In-situ programming for Flash and EEPROM

from any pins / peripheral interfaces (software configurable)

Remote mode (at production level) Standalone mode (application running)

Flexible production manufacturing and test flow

On-the-fly application reprogramming


ST7 ANALOG PERIPHERALS MORE FLEXIBILITY & LESS COMPONENTS

8- & 10-bit ADC... and more to come

Low Voltage Detector Op Amp

-

+

Up to 16 channelsFast conversion time 3 sHigh resolution (5 mV)

Simple PCBNo interruptLess external components

Embedded supply monitoring Low power consumptionLess external components


LOW VOLTAGE DETECTOR CHARACTERISTICS

LVD (IT) : interrupt generation before entering resetLVD (reset) : flag activationSelectable reset levels for

5 V applications : [4.5 V - 5.5 V]3.3 V applications : [3 V - 3.6 V]...

Context saving in EEPROMOrigin of reset localizableSaves external supply monitoring circuitry

VCC supply

Internal RESET

hysteresis

VDD Min

VLVDf(reset)

VLVDr (reset) hysteresis

interrupt generation

fixed V

VLVDr(IT)VLVDf(IT)

interrupt generation

hysteresis


LOW VOLTAGE DETECTOR

External components saved2 Clamping diodes4 Resistors1 Transistor1 Zener diode1 Filter capacitor

Integrated 3-level range on Low Voltage DetectorReset automatically activates when 0.8V < VDD < Safe Level External reset generation (30 µs)Internal interrupt & reset generation

Reset of other devices of the applicationCost savings of 10 to 15 centsEnhanced reliabilitySafe micro behavior

Resetcircuit

ST7VDD


INTEGRATED OPERATIONAL AMPLIFIER

Rail-to-rail programmable op-ampBand gapFixed voltage referenceProgrammable voltage reference6.5 MHz bandwidthAuto-zero modeOn/off capabilityInternal connection to ADC

Can be used for ADC zoomingComparator / voltage threshold detectorPeak voltage detector

ADC error suppressionLow power consumptionCost saving

Op-Amp

ST7

PROGRAMMABLE VREF

PROGRAMMABLE GAIN OP-AMP

ADCOUTPUT

+-

ANALOG / DIGITAL OUTPUT


ST7 LOW POWER SOLUTIONS

Low power modes

RUN

SLOW

WAIT

SLOW-WAIT

ACTIVE-HALT

HALT0.2 A

2 mA

Oscillator

< 700 A / 16 MHz

INTERNAL SAFE OSCILLATOR

EMC by design

1 KV

3 KV

99 00

2 KV

98

Industry Acceptance

ST7 PRODUCTRANGE

Low emissionHigh robustness

Low power and safe Low power consumption


ST7 MULTI-OSCILLATOR SYSTEM

Low frequency backup safety oscillator Automatic switch from main clock to safe clock Dedicated flag & Interrupt generation Watchdog always operational

External source Up to 16 MHz

Quartz / ceramic Up to 16 MHz

Internal RC 1 MHz +/- 1% 4 MHz +/- 20%

External RC 1 to 14 MHz

Internal safe oscillator 250 KHz +/- 15% Power optimization

Safe microcontroller behavior

osc1 osc2 osc1 osc2 osc1 osc2 osc1 osc2

osc1 osc2


ST7 LOW POWER MODES

RUN

SLOW

WAIT

SLOW-WAIT

ACTIVE-HALT

HALT

Real T

ime C

lock

Consumption

5V4MHz typical

ST7 LOW POWER MODE FIT ALL YOUR APPLICATION REQUIREMENTS

1.8mA Core and peripherals run at max. frequency

Selected peripheral can be switched off

600µA Core and peripherals run at Fosc2n

1mA Core frozen

Peripherals run at max. frequency

350µA Core frozen

Peripherals run at Fosc2n

300µA

0.2µA


EMC APPROACH : SECURE & ROBUST

Low power design Protected and robust macrocells Factual measurements through comprehensive testing Operation in noise sensitive environments can be evaluated

from the information available in datasheet

High protectionCost savings

Fewer components on the board


ST7 PROGRAMMABLE I/OsPIN-BY-PIN FLEXIBLE CONFIGURATION

High flexibility in I/Os and software configuration Fewer external components and less expensive PCB

One microcontroller for different design versionsLower development and inventory costLower pin count and better pricing through economy of scale

Input I/O port configuration example Output I/O port configuration example

ANALOG INPUT

INTERRUPT

EXTERNALINTERRUPT

ALTERNATE INPUT

DATA BUSR

WREGISTER

REGISTER

DATA BUS

R/W

ALTERNATE OUTPUT


ST7 : A SET OF AVAILABLE PERIPHERALS

ADC

FLASH

TIMERS

ROM

EEPROM

SPI I2C

CAN

SCI(UART)

OpAmp

I/Os

SMART CARD INT.

MOTORCONTROL

LCDDRIVER

SRAM

USB

ST7Core



ST7 TECHNICAL TRAINING1 - INTRODUCTION

2 - CORE

3 - ADRESSING MODES

4 - PERIPHERALS

5 - ST7 SOFTWARE TOOLS

6 - ST7 HARDWARE TOOLS

7 - STVD7


ST7 CORE

WATCHDOG

LOW

POWER

MODES

INTERNAL

REGISTERS

ST7

STACK

CLOCK

CONTROLLER

INTERRUPTS

MEMORY

SPACE

RESET

SYSTEM

LVD


ST7 CORE General Description

• THE ST7 CORE (Von Neuman Architecture) IS BUILT AROUND :

– an 8-bit Arithmetic and Logic Unit (ALU)

– 6 internal registers : Accumulator (A), X and Y index registers, Program Counter (PC), the Stack Pointer (SP) and the Code Condition register (CC)

– a controller block

• IT INTERFACES WITH :

– an on-chip oscillator

– a reset block

– address and data buses to access memories and peripherals

– an interrupt controller


SP

PCHPCL

CONTROL

AD

DR

ES

S B

US

DA

TA

BU

S

8 -BIT ALU

RAM

Program memory

WatchdogLVDEnhancedReset

Internal CLOCK

AccuIndex XIndex Y

CC

Mutli oscillatorClock controller

OSCin

OSCout

ISPSEL/ Vpp

RESET

ST7 COREBlock Diagram


ST7 COREInternal Registers (1)

• The ACCUMULATOR is an 8-bit general purpose register used to hold:

– Operands

– Results of arithmetic and logic operation• The X and Y REGISTERS are two 8-bit registers used to :

– Create effective addresses

– Store temporary data

Y is not automatically stacked. If needed, it must be done using the PUSH and POP instructions

Instructions using X are faster than the ones using Y



• The PROGRAM COUNTER PC is a 16-bit register used to store the address of the next instruction to be executed by the CPU. As a result, the ST7 can address up to 64k of program memory

• The STACK POINTER SP is a 16-bit register. The msb is fixed by hardware

• The CODE CONDITION CC is a 5-bit register

BIT NAME DESCRIPTION

H Half Carry BitH=1 when a carry occurs during ADD and ADC instructions

I Interrupt mask I=1 disabled the interrupt

N Negative bit N=1 if the result of the last operation is negative

Z Zero bit Z=1 if the result of the last operation is zero

CCarry/Borrow bit

Affected when carry or borrow out occur and some inst. are executed


ACCUMULATOR :

X INDEX REGISTER :

Y INDEX REGISTER :

PROGRAM COUNTER :

STACK POINTER :

CONDITION CODE REGISTER :

7 0

RESET VALUES : X X X X X X X X

0

XXXXXXXXRESET VALUES :

7 0

RESET VALUES : XX X X X X X X

RESET VALUES : RESET VECTOR @ FFFEh-FFFFh

0715

07

RESET VALUES :

1 1 1 H I N Z C

6 5 4 3 2 1

0101X111

15 7 0

xxx

Fixed By HW

x x x x x


77


ST7 COREStack manipulation (1)

• PURPOSE :

– Save the CPU context during subroutine calls or interrupts

– Save temporary user's data (PUSH and POP instructions)

• IN CASE OF OVERFLOW (LOWER LIMIT EXCEEDED) :

– SP rolls over to the higher address

– Previous value is overwritten so lost

– Stack overflow is not indicated

Lower Address

Higher Address

Push YCall subroutines or interrupt

Pop YReturn from subroutines or interrupt


RETRSP

IRETPOP YPUSH YInterrupt event

CALL subroutine

$017F

SPPCHPCL

SP

PCHPCL

SP

PCHPCL

SP

PCHPCL

SPPCHPCL SP

PCHPCL

AX

CC

PCHPCL

AX

CC

PCHPCL

AX

CCY

$0100

Stack size and position is device dependent :ST72254 : 128 bytes ($0100 to $017F)ST72334 : 256 bytes ($0100 to $01FF)

ST7 COREStack manipulation (2)


ST7 COREThe memory space

• THE MEMORY CAN BE MADE OF 6 DIFFERENT BLOCKS :

• Peripherals hardware registerI/O Ports, TIM, ADC, WDG,SPI, I2C, EEPROM etc

• Ram 0 : ram in first page

• Stack : from 128 to 256 bytes (device dependent)

• EEPROM Data (up to 256 bytes)

• Program memory

• Interrupt and Reset vectors

$00

$80

ROM/EPROM8KBytes

INTERRUPTS& RESETVECTORS

$FFE0

$FFFF

PERIPHERALS HARDWARE REGISTERS

RAM 0128 Bytes

STACK128 Bytes

$0100

RESERVED

$0180

$E000

Short Addressing

Mode Location


ST7 IN-SITU PROGRAMINGRemote ISP

• What is it for ?– To PROGRAM or REPROGRAM (flash devices) the Program

Memory when the micro is soldered on the application board.

• Main features:– Only 6 wires are used (including VDD & VSS).– Do not need double voltage on the application board.– Supported by the ST window eepromer tools.

• Performances:– ~ 5 s to program 8Kbytes.


ST7 IN-SITU PROGRAMING (ISP)Remote mode

1

Boot-ROM allows an executable software to be dowloaded in RAM through ISPCLK & ISPDATA

Software executed in RAM programs the prog memory

Boot-ROM

RAM

ISPCLK

ISPDATA

RESET/ISPSELVCC/VSS

4

PROGMEMORY

I/Os

RAM

Periphs

PROGMEMORY

2

Software executed in RAM runs any applicative software with I/Os and peripherals accessIn-Situ Programming uses 6 wires only

ISPCLK

ISPDATA

RESET/ISPSELVCC/VSS

4


Memory & CPU registerSummary

• How Many CPU registers belong to the ST7 Core?

• Is it possible to place and read data in ROM (program memory)?

• Is it possible to execute code located in RAM ?

• Is the Stack handle automatically by the ST7 core ?


ST7 INTERRUPTSOverview

• EXCEPT FOR THE SOFTWARE INTERRUPT (TRAP Instruction), ALL INTERRUPTS CAN BE MASKED BY SETTING THE I BIT IN CC

• WHEN AN INTERRUPT OCCURS :

– The context is saved on the stack (CC, A, X, PC)

– All other interrupts are masked (the I bit is set By H/W

– The interrupt vector is loaded in the Program Counter

• WHEN RETURN FROM INTERRUPT IS EXECUTED :

– The original context is automatically restored (CC, A, X, PC)

– Interrupts are enabled (I bit reset)

• PRIORITY BETWEEN INTERRUPTS IS GIVEN BY THE INTERRUPT ADDRESS VECTOR


ST7 INTERRUPTSST72254 Interrupt mappingCPU INTERRUPT INTERRUPTS REGISTER FLAG

NAMEINTERRUPT SOURCE

VECTOR ADDRESS

Reset Reset N/A N/A - FFFEh-FFFFh

Trap (instruction) Software N/A N/A I0 FFFCh-FFFDh

External Interrupt 0 Port A N/A N/A I1 FFFAh-FFFBh

External Interrupt 1 Port B and Port C N/A N/A I2 FFF8h-FFF9h

CSS Clock Filter Interrupt CRSR CCSD I3 FFF6h-FFF7h

SPI Transfer CompleteMode Fault

SPI Status SPIF

MODF

I4 FFF4h-FFF5h

Timer A Input Capture 1Output Compare 1Input Capture 2Output Compare 2Timer Overflow

Timer A Status

ICF1

OCF1

ICF2

OCF2

TOF

I5 FFF2h-FFF3h

Timer B Input Capture 1Output Compare 1Input Capture 2Output Compare 2Timer Overflow

Timer B Status

ICF1

OCF1

ICF2

OCF2

TOF

I7 FFEEh-FFEFh

I2C Byte Transfer finishedBus ErrorSTOP Detection

I2C Status BTFBERRSSTOP

I12 FFE4h-FFE5h


Periph Status Register

XX X X 1 X X X

Periph Control Register

XX X X 1 X X X

Condition Code Register

C1 1 1 H 0 N Z

Interrupt flag set by H/W

Interrupt Enable bit set by S/W

Interrupt generation

Context switch takes 10 CPU clock cycles

Interrupt Mask bit set by S/W

ST7 INTERRUPTSPeripheral Int management


ST7 INTERRUPTPeripheral Int management

SOFTWARE EXAMPLE.Main...BSET Control_reg, #IT_enable ; Enable Periph interruptRIM ; Clear I bit in CC regis

... ; ie interrupt enabled

.Int_routine

...BRES Status_reg, #IT_flag ; Avoid to process the ; same interrupt foreverIRET ; Return from interrupt...


Software levels allows the ST7 nested interrupt process (only in the ST72511R & subsets)At least one Interrupt Vector per Peripheral

ST7 Interrupt Summary

• Interrupt Vectors:• Number:• S/W Priority * :• Interrupt Reaction

Time:

• Automatic register pushed:

• up 16 Vectors

• 16 levels hardwired

• 4 levels user configurable

• 1.250µs to 2.750 µs (end of the current instruction +10 cpu cycles)

• Program Counter, Accumulator, CC, X


main

IT2

IT1

NMI

IT1

IT0

IT3

IT4

main

3

3

3

3

3

3

3/0

RIM

Har

dwar

e P

riorit

y

Software Priority

Concurrent Interrupt Management

• An interrupt can not be interrupted by another one

• Except by the NMI (Non Maskable Interrupt)

IT0

IT1

IT4

IT3

NM

I

IT2


Interrupt Software Priority Level I1 I0

Level 0 (main) Low 1 0

Level 1 0 1

Level 2 0 0

Level 3 (=interrupt disable) High 1 1

Nested Interrupt• The 4 interrupt S/W levels are set thanks to the pair of bits

I0, I1.

• 1 pair of bits by interrupt vector stored in the ISPR registers

• The pair of bits is copied in the CC register when the corresponding IT is activated (software level greater than the current one).


Nested Interrupt Management• An interrupt can be interrupted by:

– The NMI (Non Maskable Interrupt)

– An interrupt request having an highest software Priority

main

IT2

IT1

NMI

IT1

IT0

IT3

IT4

main

3

3

2

1

3

3

3/0

RIM

Har

dwar

e P

riorit

y

Software Priority

IT4

IT2

IT0

IT1

IT4

IT3

NM

I

IT2


Interrupt Roadmap

ST72532R4ST72311R6/7/9ST72512R4ST72511R6/7/9

ST72104G1ST72215G2ST72216G1ST72254G1/2

ST72314J2/4ST72314N2/4ST72334J2/4ST72334N2/4

Concurent Interrupts

Nested Interrupts

Concurent Interrupts

GP 28,32 pins GP 42,44,56,64 pins

Auto 42,44,56,64 pins Dedicated Solutions

ST72171K2ST72411R1

ST72141K2 Concurent Interrupts


Interrupts Summary

• How many interrupt vectors can be used in the ST7 ?

• Are the software interrupt levels able to be modified during the application?

• What are the instructions that enable & disable the Interrupts?


Multi oscillator (1)

• ADVANCED ST7 CLOCK SYSTEM

• Low frequency backup safety oscillator• Implemented on Reprogrammable devices only

EXTERNAL SOURCE

OSC1 OSC2

QUARTZ/CERAMIC EXTERNAL RC INTERNAL # 4Mhz

OSC1 OSC2 OSC1 OSC2 OSC1 OSC2


• Frequency range

• 1 to 4 MHz

• 2 to 4 MHz

• 4 to 8 MHZ

• 8 to 16 MHz

• 1 to 14 MHz• # 4 MHz

• # 250KHz

Multi Oscillator (2)• 4 Crystal / Ceramic

Oscillators

– Designed to reduce EMI & consumption

• Low speed

• Mid low speed

• Mid high speed

• High speed

• 1 External RC Oscillator

• 1 Internal RC Oscillator

• 1 Internal Safe Oscillator

Oscillator selected by option byte


Clock Security System (CSS)

Multi Oscillator(MO)

ClockFilter

SafeOscillator

AlternateFunction

Main Clock Controller (MCC)

Clock DividerMCCSR Register

CORE & PERIPHERALS

fCPU

fOSC

Clock divider Values:2,4,8,16,32

OSC1

OSC2

CLKOUT

Main Clock Controller


Clock Security System

• Clock Filter Function

• Safe Oscillator (# 250KHz)

Main OscillatorClock

Internal ST7Clock

Internal ST7Clock

Main OscillatorClock

Safe OscillatorClock

CSSD bit is set by H/W if one of the safety function is activated and can generate a maskable interrupt request


ST7 CLOCK IN LOW POWER MODES

• RUN MODES: Fcpu=Fosc/2

– Core & periph. running except if WAIT (Core stopped) selected

• SLOW MODES: Division ratio from 4 to 32 by software

– Core & periph. running except if WAIT (Core stopped) selected

• ACTIVE HALT: Division ratio from 32000 to 400000 by software

– Core & periph. stopped but periodic wake-up through interrupts

• HALT MODE: Oscillator stopped

– Core & periph. stopped


ST7 Clock System Roadmap

ST72532R4ST72311R6/7/9ST72512R4ST72511R6/7/9

ST72104G1ST72215G2ST72216G1ST72254G1/2

ST72314J2/4ST72314N2/4ST72334J2/4ST72334N2/4

Multi oscillatorRC ext.4Mhz int. 20%Safety oscillatorSLOW: 4/8/16/32

Quartz/Ceramic/Ext.clock4Mhz minSLOW:4/8/16/32ACTIVE HALT

Multi oscillatorRC ext.4Mhz int. 20%Safety oscillatorSLOW: 4/8/16/32ACTIVE HALT

GP 28,32 pins GP 42,44,56,64 pins

Auto 42,44,56,64 pins Dedicated SolutionsST72171K2

ST72411R1

ST72141K2Quartz/Ceramic/Ext.clockSLOW:4/8/16/32

Idem as GP 28,32 pins7.16Mhz int / Ext.ClockSLOW:/32


ST7 COREReset diagram (1)

• EXTERNAL RESET USING RESET PIN– Purpose : allow to generate an external reset– Condition : reset pin pull low

• POWER SUPPLY DEPENDEND RESET USING LVD– Purpose : ensure the MCU is in a known state whatever Vcc– Condition : internal reset when Vcc reaches Vcc min

• WATCHDOG RESET USING THE WATCHDOG TIMER– Purpose : guarantee the safety in case of software trouble– Condition : internal reset when the WD register is not refreshed


ST7 ENHANCED RESET SYSTEM

• 3 RESET SOURCES– Watchdog

– Low Voltage Detection (LVD)

– External RESET pin

• COMPLETE RESET MANAGEMENT

– Flags on Reset sources

– Internal Reset externally issued to reset the whole application

From internal Watchdog Reset: Phase # 30µsFrom internal LVD Reset: 30µs<Phase<Low voltage duration From external RESET pin: 30µs<Phase<Ext RESET pulse width

COMPLETE RESET SEQUENCE

Internal Reset4096 clock cycles

Fetch Reset Vector

Phase with RESET pin grounded


Internal Reset

TO ST7

RESET

OSCILLATOR

SIGNAL

COUNTER

NRESET(ACTIVE LOW)

CK

WATCHDOG RESETLVD RESET

Ron

VCC

30µs Delay

ST7 COREReset diagram (3)


NEW ST7 LVD GENERATION

3 Selectable levels

Activation Flag

Low consumption

RESET pin tied to GND

Safe behaviour despite starting current sunkVCC supply

RESET

250mV hysteresis

Min working VDD

VLVDf

VLVDr


3 LVD LEVELS TO OPTIMIZE THE SAFE AREA

Freq.

Vsupply

3.0V 3.5V

8Mhz

16Mhz

4.0V

LVD high LVD med. LVD low Absolute working

window

Safe 16Mhz area

3.8V Reset issued

Safe 16MHzarea.

3.5V Reset issued

Safe 8Mhzarea


LVD PART OF COMPLETE RESET MANAGEMENT

LVD Reset ensures a

stable cleared state of the

WDGRFwhen CPU

starts

Vdd supply

LVDRF

LVD LVD

Software clearance

LVD

WDGRF

WDG

If LVDRF is not cleared

upon another Reset, the

flag remains SET to keep

trace of original failure.

External

Original RESET source

LVDRF WDGRF

External RESET pin 0 0

Watchdog Reset Flag 0 1

Low Voltage Reset Flag

1 X

WDG


ST7 WATCHDOGOverview (1)

• ITS PURPOSE IS TO DETECT THE OCCURENCE OF A SOFTWARE FAULT. IT MUST BE REGULARLY REFRESHED BY THE PROGRAM :

– ld WDCR, #$FF ; Reload WD

• 2 DIFFERENT WATCHDOG CAN BE SELECTED BY OPTION MASK :

– Hardware Watchdog : WD automatically activated upon reset

– Software watchdog : it is activated by software (bit 7 = 1). Once activated, it cannot be disabled


ST7 WATCHDOGOverview (2)

• RESET AND WATCHDOG :

– HALT instruction can generate a reset if watchdog activated and if the option byte allows it

– The Watchdog can be used to generate a software reset (bit 7 = 1, bit 6 = 0)ld WDCR, #$80 ; Reset !

Min : WDCR = C0h= 2^0 × 12288 = 12288 clock cycles

= 1.54 ms for Fcpu = 8MHz Max : WDCR = FFh

= 2^6 × 12288 = 786432 clock cycles= 98.30 ms for Fcpu = 8MHz


ST7 WATCHDOGBlock diagram

ST7 WATCHDOGBlock diagram

Clock Divider ÷12288

WDGA

Reset

Fcpu

MSB LSB

WDGF

Watchdog Control Register

Watchdog Status RegisterActivation bit

(WD active if set)

- - - - - - -

7-bit Down Counter


LVD ROADMAP

ST72532R4ST72311R6/7/9ST72512R4ST72511R6/7/9

ST72104G1ST72215G2ST72216G1ST72254G1/2

ST72314J2/4ST72314N2/4ST72334J2/4ST72334N2/4

3 LVD levels:4.00V/4.25V3.60V/3.85V3.10V/3.35VReset Flags

LVD by device reference

4.25V/4.50V

3 LVD levels:4.00V/4.25V3.60V/3.85V3.10V/3.35VReset Flags

GP 28,32 pins GP 42,44,56,64 pins

Auto 42,44,56,64 pins Dedicated SolutionsST72171K2

ST72411R1

ST72141K2

Idem as GP 28,32 pins

1 level LVD


Clock & Reset systemSummary

• What are the maximun oscillator frequency and the maximun CPU frequency ?

• How many internal RC oscillator are implemented on the ST7 ?

• What are the internal reset sources?

• Are these internal resets can detected externally?


ST7 LOW CONSUMPTION MODESOverview

• MAXIMUM CONSUMPTION : 20 mA WITH FOSC = 16 MHZ AND VDD = 5V

• TO REACH LOWEST POWER CONSUMPTION– Switch off unused peripherals– Configure I/Os as output low level and connect them to GND– Use the lowest oscillator frequency possible– Use the Slow mode, Wait mode or better the Halt mode

• DATA RETENTION VOLTAGE IN HALT MODE : 2V


ST7 LOW CONSUMPTION MODES

Slow mode• GOAL : reduce the comsumption by reducing the

clock speed keeping the same Oscillator frequency

• ENTER BY : configuring the miscellaneous register

• CAUSES : the CPU clock slows down– the Fosc can be divided by 4, 8 ,16 or 32 rather than 2

• EXIT BY : configuring the miscellaneous register



Wait mode• GOAL : Reduce the consumption while monitoring external events

• ENTER BY : execution of the WFI instruction

• CAUSES : the micro is software frozen– Program execution stopped– Memory and registers remain unchanged– The oscillator still provides a clock to the peripherals

• EXIT BY– Reset (Watchdog, reset pin)– Internal interrupts (timer A, timer B, A/D, SPI etc)– External interrupts (I/O ports)



Active Halt mode• GOAL : Reduce the consumption to the lowest value while monitoring a real time

clock.

• ENTER BY : execution of the HALT instruction while the OIE (Oscillator Interrupt Enable) bit is set.

• CAUSES : the micro is SW frozen, all the peripherals are stopped, only the Oscillator & the Main Oscillator Counter are running.

• EXIT BY

– External Reset

– Interrupts with exit from halt capability (External IT,..)

– Time Base Interrupt (32000,64000,160000,400000 *Tcpu

– From 2ms to 25ms with fOSC=16MHZ



Halt mode• GOAL : Reduce the consumption to the lowest value

• ENTER BY : execution of the HALT instruction

• CAUSES : the micro is SW and HW frozen

– Program execution stopped

– Memory and registers remain unchanged

– The oscillator stopped

• EXIT BY

– External Reset

– External interrupts (I/O ports)


PROGRAMMING TIPSLow Consumption Modes (1)

• DURING WAIT MODE or HALT MODE, BIT I (INTERRUPT BIT) OF CC REGISTER IS AUTOMATICALLY RESET TO ENABLE INTERRUPT

• TYPICAL CONSUMPTION ST72254 ST72334

Run mode (Vdd=5V, Fcpu=8MHz) 5.5 mA 7.1 mA

Slow mode (Vdd=5V, Fcpu=500KHz) 0.7 mA 1 mA

Wait mode (Vdd=5V, Fcpu=8MHz) 2 mA

Wait minimun mode (Vdd=5V,Fcpu=500KHz)

0.4 mA 0.5 mA

Active Halt mode (Vdd=5V,Fosc=16MHz) - 20µA

Halt mode (Vdd=5V) 0.5 µA 0.5 µA


PROGRAMMING TIPSLow Consumption Modes (2)

• AFTER EXITING FROM HALT MODE OR WAIT MODE AFTER RESET, THE MICRO WAITS 4096 CPU CLOCK CYCLE (STABILIZATION TIME) BEFORE BEING OPERATIONAL

• SOURCE THAT ALLOWS TO EXIT FROM WFI OR HALT MODE– Internal Interrupts => Wait and Halt modes– External Interrupts => Halt mode

Documents

Sistemi Elettronici Programmabili