SISO MIMO (1)

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

VLSI Implementation of a Soft-Output SignalDetector for Multimode Adaptive Multiple-Input

Multiple-Output SystemsLiang Liu, Member, IEEE, Johan Löfgren, Student Member, IEEE, Peter Nilsson, Senior Member, IEEE,

and Viktor Öwall, Member, IEEE

Abstract— This paper presents a multimode soft-outputmultiple-input multiple-output (MIMO) signal detector thatis efficient in hardware cost and energy consumption. Thedetector is capable of dealing with spatial-multiplexing (SM),space-division-multiple-access (SDMA), and spatial-diversity(SD) signals of 4 × 4 antenna and 64-QAM modulation.Implementation-friendly algorithms, which reuse most of themathematical operations in these three MIMO modes, areproposed to provide accurate soft detection information, i.e.,log-likelihood ratio, with much reduced complexity. A unifiedreconfigurable VLSI architecture has been developed to eliminatethe implementation of multiple detector modules. In addition,several block level technologies, such as parallel metric updateand fast bit-flipping, are adopted to enable a more efficientdesign. To evaluate the proposed techniques, we implementedthe triple-mode MIMO detector in a 65-nm CMOS technology.The core area is 0.25 mm2 with 83.7 K gates. The maximumdetecting throughput is 1 Gb/s at 167-MHz clock frequencyand 1.2-V supply, which archives the data rate envisioned bythe emerging long-term evolution advanced standard. Underfrequency-selective channels, the detector consumes 59.3-, 10.5-,and 169.6-pJ energy per bit detection in SM, SD, and SDMAmodes, respectively.

Index Terms— Multiple-input multiple-output (MIMO),signal detector, soft-output, space-division-multiple-access(SDMA), spatial-diversity (SD), spatial-multiplexing (SM), VLSI.

I. INTRODUCTION

TO MEET the growing demands for better user experience,the International Telecommunication Union has released

its requirements for next-generation wireless networks, wheremuch higher spectral efficiency, higher coverage, and lowerlatencies are expected [1]. It has been a broad agreement thatenhanced multiple-input multiple-output (MIMO) technologiesplay an essential role in emerging wireless standards, e.g.,IEEE 802.16m (WiMAX Profile 2.0) [2] and 3GPP long-term evolution advanced (3GPP LTE-A) (Release 10) [3], toachieve or exceed the International Mobile Telecommunica-tions Advanced target.

Manuscript received May 17, 2012; revised October 17, 2012; acceptedNovember 25, 2012.

The authors are with the Department of Electrical and Information Tech-nology, Lund University, Lund 222 29, Sweden (e-mail: [email protected];[email protected]; [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TVLSI.2012.2231706

Cellular systems experience highly dynamic channelconditions, where the signal-to-noise ratio (SNR) and fadingproperties vary within huge ranges. To guarantee the qualityof service for users with a specified error rate and datathroughput, it is necessary that the system is equipped withmultiple MIMO technologies, which are dynamically adaptedto the fluctuating channels. This is because single-modeMIMO schemes have shown their limitations in satisfyingsuch requirements. For example, the widely-used spatial mul-tiplexing (SM) technique [4] suffers from huge performanceloss when the spatial channel becomes highly correlated [5].Currently, extensive discussions are ongoing about the multi-mode adaptive MIMO schemes in 3GPP-LTE and WiMAX [6].MIMO transmission techniques to be switched include SM [7],space-division-multiple-access (SDMA) [5], [8], and spatialdiversity (SD) [9]. For such an adaptive system, multiplesignal detectors are needed at the receiver side with eachone corresponding to the respective mode. A straightforwardimplementation strategy will incur considerable silicon areaoverhead and be immensely inefficient since most of themodules would remain in an idle state for a large part ofthe time. As a consequence, an efficient implementation isexpected to integrate multiple MIMO detectors into a singlemodule, which can be reconfigured for the respective modeat run-time. Moreover, in real-life wireless systems, signaldetectors are usually attached with channel decoders to providerobustness against noise and fading. Therefore, a detectorshould be capable of not only providing the binary estimationof each bit but also its reliability measurement, e.g., log-likelihood ratio (LLR) [7], to achieve further performanceenhancement. Finally, the chip area and power consumptionshould be low enough to be adopted in practical systems,especially for hand-held devices where the high performanceand flexibility need to be combined with energy efficiency. Tothe best of our knowledge, VLSI implementation of such areconfigurable multimode soft-output MIMO detector remainsmissing in open literatures.

In an attempt to fill this gap, this paper proposes asoft-output signal detector that supports 64-QAM modulatedSM/SDMA/SD triple-mode signals for up to 4 × 4 MIMOtransmission. Furthermore, it achieves near maximuma posteriori probability (MAP) detection performance andprovides gigabit-per-second throughput. The unification ofmultimode processing is mainly realized by algorithm-level

1063–8210/$31.00 © 2012 IEEE


2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

exploitation, where the algorithms for each mode consist ofsimilar mathematical operations to enable substantial hardwarereuse. First, we develop soft-output detection algorithms forSM and SDMA modes based on an efficient extension andmodification of the hard-output fixed-complexity spheredecoder (FSD) [10]. More specifically, we introduce asymbol-level bit-flipping scheme, which generates accurateLLR values with marginal hardware increment. Additionally,a polygon-shaped constraint technique is adopted to facilitatethe reduction of unnecessary node extensions in the treesearch procedure. For SD signal detecting, e.g., Alamoutispace-frequency block codes (SFBC) [11], [12], we proposea low complexity MAP algorithm owning a unified detectionprocedure that is independent of antenna number. It allowsfor parallel detection of the real and imaginary parts ofeach transmitted symbol with the help of QR decompositionto the orthogonal real-valued channel matrix. Takingadvantage of these implementation-oriented algorithms,a unified VLSI architecture is subsequently developed,capable of being reconfigured to support different MIMOmodes at run-time. To further improve the implementationefficiency, e.g., reduce the detection latency, we introducea parallel metric update strategy, which processes multiplecandidate vectors simultaneously for soft-value computationand a fast bit-flipping scheme to select the bit-flipped symbolwith simple boundary-check operations. To validate theeffectiveness of foregoing design solutions, we designedthe proposed triple-mode soft-output signal detector usingSynopsys tools with a 65-nm CMOS standard cell library.Occupying only 0.25 mm2 core area (83.7 K equivalent gatecount), the detector achieves 1-Gb/s throughput in SM and SDmodes with 4 × 4 64-QAM configuration, representing a 44%saving to state-of-the-art in terms of hardware efficiency. Thethroughput for detecting SDMA signal is 250 Mb/s. Workingat frequency-selective channels, e.g., the extended vehicularA (EVA) channel specified in LTE standard [13], the detectorconsumes 59.3-mW power in SM mode, resulting in a59.3-pJ/b energy consumption. The energy needed to detect abit in SD and SDMA modes is 10.5 and 169.6 pJ, respectively.

The remainder of this paper is organized as follows.Section II briefly introduces the system model and soft-outputMIMO signal detection. Section III describes and evaluatesthe proposed detection algorithms. Section IV shows the VLSIarchitecture and module circuit design. The implementationresults and performance comparison are presented inSection V, and conclusions are drawn in Section VI.

II. BACKGROUND

A. System Model

As illustrated in Fig. 1, we consider a downlink switchingSM/SDMA/SD MIMO system with one base station (BS) andK user equipments (UEs). Both the BS and UEs are equippedwith N transmit and receive antennas. The received N × 1complex signal vector at the kth UE is given by

rk = Hck

K∑

k=1

Pk sk + nk (1)

1 . . . N

UEK

HK~ c

1 . . . N

source b1 MappingEncodes1 Pre-code

(P1)...

Channelestimate

r1

H1Soft

detectorllr

Decode

Ante.1

Ante. N

1

N...

1

N...

source bKMappingEncode

sK Pre-code(PK)

~

~

~

~BS

~

~

UE1 1 . . . N

H1~ c

UE2

H2~ c

. . .

Fig. 1. LTE downlink multimode MIMO transmission.

where sk = [s(0)k , . . . , s(L−1)

k ]T is the L-layer transmittedvector for user k, in which each component is taken inde-pendently from a set of Grey-labeled M-QAM constellationpoints. Each symbol vector sk is associated with a bit-levelvector bk (i.e., sk = MAP(bk)), which is obtained by errorcorrection coding to the original binary source. In (1), nk isthe vector of independent Gaussian noise samples with meanzero and variance N0/2, Hc

k is the N × N complex channelmatrix between the BS and the kth UE, and Pk is the N × Lpre-coding matrix, which is selected from a pre-defined code-book and is assumed to be known to both BS and UE [14]. Theswitch between different MIMO transmissions is realized bychanging the matrix Pk . Throughout this paper, we set Pk to bean N×N identity matrix (IN ) in SM mode. While in SD mode,Pk is an Alamouti coding matrix [12]. For SDMA system,Pk is a unitary pre-coding matrix such that P H

k Pk = 1 andP H

k Pl,l �=k = 0, where (·)H means Hermitian transposition.Moreover, we assume point-to-point transmission in SM andSD modes, i.e., K = 1 and L = N . Finally, L is set to 1 inSDMA mode, because the number of layers per UE is limitedto one in LTE [14].

The complex system can be transformed to its real-valuedrepresentation rk = H[s1, . . . , sK ]T + nk , where

rk = [�(rk,1), �(rk,1), . . . ,�(rk,N ),�(rk,N )]T

sk = [�(sk,1), �(sk,1), . . . ,�(sk,L ),�(sk,L)]nk = [�(nk,1), �(nk,1), . . . ,�(nk,N ),�(nk,N )]T (2)

and

H=

⎡

⎢⎢⎢⎢⎢⎣

�(H1,1) −�(H1,1) . . . �(H1,N ) −�(H1,N)

�(H1,1) �(H1,1) . . . �(H1,N ) �(H1,N)...

.... . .

......

�(HN,1) −�(HN,1) . . . �(HN,N ) −�(HN,N )

�(HN,1) �(HN,1) . . . �(HN,N ) �(HN,N )

⎤

⎥⎥⎥⎥⎥⎦. (3)

In (2) and (3), H = Hck [ P1, . . . , PK ] is the equivalent chan-

nel, [·]T means vector transposition, �(·) and �(·) representthe real and imaginary parts of a complex number, respectively.

B. Soft-Output MIMO Signal Detection

Hard-output signal detectors tries to recover the originalvector sk , given rk and H . While the objective of soft-output


LIU et al.: VLSI IMPLEMENTATION OF A SOFT-OUTPUT SIGNAL DETECTOR 3

detectors is to provide reliability information by computingthe LLRs for each bit of bk , e.g., for the lth bit, we have

L(bk,l | rk)= lnP(bk,l =1 | rk)

P(bk,l = 0 | rk)= L E (bk,l | rk)+L A(bk,l).

(4)

In (4), L A(bk,l) is the a priori probability and L E (bk,l | rk) isthe extrinsic information. For simplification, we will omit theuser index k in the following. According to [7], L E (bl | r)can be rewritten as

L E (bl | r) = ln

∑b∈χ1

lP(r | bl) exp(1/2bT[l] L A[l])

∑b∈χ0

lP(r | bl) exp(1/2bT[l] L A[l])

(5)

where χ1l and χ0

l are the sets of bit-level vectors hav-ing the lth bit equal to 1 and 0, respectively, b[l] denotesthe sub-vector of b with the lth bit bl being omitted,L A[l] is the sub-vector of the a priori information vectorL A = [L A(b1), L A(b2), . . . , L A(bN logM

2)]T omitting L A(bl).

The computation of (5) is usually simplified with max-logapproximation, yielding the MAP algorithm as

L(bl | r) ≈ minb∈χ0

l

1

N0|r − Hs|2 − min

b∈χ1l

1

N0|r − Hs|2. (6)

Note that the a priori information is not considered in (6),meaning that we do not take into account the turbo receiverscheme where the inner detector and the outer decoderexchange extrinsic information iteratively [7].

From a hardware design perspective, tree-search algorithms[15]–[21] are promising alternatives to the direct implementa-tion of (6) due to their effectiveness in confining the detectionprocedure within a much smaller search space. A tree-searchalgorithm formulates the detection as a 2N-depth

√M-ary

tree search problem by rewriting the Euclidean distance as| y − Rs|2, where R is an upper triangular matrix obtained byH = Q R, y = QH r , and Q is a unitary matrix. Startingfrom the top (2N th) layer, the calculation of the Euclideandistance T is carried out in a recursive way as

Ti = Ti+1 + inci

inci =∣∣∣∣∣∣yi −

2N∑

j=i+1

Rij s j − Rii si

∣∣∣∣∣∣

2

= |y ′i − Rii si |2 (7)

where Ti is the partial Euclidean distance (PED) at the i thlayer. The soft-output tree-search algorithm generates a list Lof candidate vectors by going through the tree and finds thetwo elements of (6) within the list

L(bl | r) ≈ minb∈L∩χ0

l

1

N0|r − Hs|2 − min

b∈L∩χ1l

1

N0|r − Hs|2.

(8)

In tree-search detection, L ∩ χ1/0l can be empty. Under such

circumstance, a constant value is usually adopted to demon-strate that bl equals to 1 or 0 with a large probability [16].Specified in this paper, the breadth-first FSD [10], [19] willbe explored, because of its low computational complexity,completely regular and feed-forward-only dataflow, and near-optimal performance.

III. SOFT-OUTPUT DETECTION ALGORITHMS

In this section, we will develop detection algorithms for SM,SDMA, and SD MIMO modes, respectively. These proposedalgorithms feature low computational complexity and demon-strate similar mathematical operations that can be convenientlyintegrated into a single VLSI architecture. In particular, wefocus on the modification of FSD for SM and SDMA modes.For SD mode, we propose an extensively simplified MAPalgorithm by leveraging the orthogonality of Alamouti signalsand the matrix-decomposition operations.

A. Low-Complexity LLR Generation Based on FSD

FSD divides the real-valued search tree into two uniqueparts using a parameter D. A full-search is performed in thefirst D layers, exhaustively expanding all

√M branches per

node, while in the remaining (2N-D) layers, a single-search isadopted, expanding only one best branch per node. It has beenanalyzed in [22] that FSD achieves close-to-ML performanceif (D + 1)2 ≥ 2N . For example, D = 2 allows the FSD topresent an asymptotical ML performance for MIMO systemwith N = 4. However, FSD is more efficient in finding the MLsolution in a hard-output scenario instead of generating a listof vectors around the ML result, resulting in poor performancefrom a soft-output perspective [19]. In this section, we extendthe original FSD to provide accurate soft values while main-taining its low computational complexity. With this purpose,we utilize a symbol-level bit-flipping scheme for performanceimprovement and a polygon-shaped constraint technique toreduce unnecessary node extensions.

1) LLR Accuracy Improvement by Modified Bit-Flipping:Compared to the hard-output ML detection

sML = arg mins∈2N

√M

1

N0|r − Hs|2 (9)

the soft-output detection consists of two minima searchprocedures, as demonstrated in (6). One of them is obtainedby (9), which is then referred as T ML = 1/N0|r − HsML|2.The other can then be formulated as

T MLl = min

b∈χMLl

1

N0

∣∣∣r − HsMLl

∣∣∣2

(10)

in which χMLl is the binary complement to the lth bit in the

ML bit vector bML. Basically, there are two major reasonsthat FSD tends to generate poor-quality LLRs. One is theoccurrence of vacant bits in the candidate list L correspondingto χML

l (i.e., L∩χMLl = ∅), existing in most tree search

algorithms. Even for those existing bits, FSD cannot ensure theminimization of (10). This is because unlike K-Best detection,where strict sorting is performed at every layer, FSD simplyextends all nodes at the first D layers while only one at theremaining. Such a tree travel scheme does not guarantee theinclusion of best vectors (i.e., vectors with smallest Euclideandistances) in the candidate list.

To tackle these two issues with reasonable complexity over-head, we suggest a modified bit-flipping scheme by replacingthe whole vector re-calculation [23] with a per symbol re-calculation scheme. Its basic idea is described as follows: when



calculating the LLR L(bi,l ) for the lth bit in the i th scalarsymbol si , the strategy is to first find the locally best symbolwith the lth bit value different to bML

i

sBFi,l = arg min

bi,l =bMLi,l

|y ′i − Ri,i si |2 (11)

and then compute the bit-flipped LLR by

LBF(bi,l | y ′i ) = |y ′

i − Ri,i sMLi |2 − |y ′

i − Ri,i sBFi,l |2

= incMLi − incBF

i,l . (12)

In (11) and (12), y ′i is the received symbol at the i th layer

with the interference from previously detected signals beingcanceled and bML

i is the bit-level vector corresponding tosML

i , which is denoted as the i th scalar symbol of the MLvector. It should be pointed out that although the ML resultis obtained by minimizing | y − Rs|2, it does not promise alocally best result, i.e., incML

i is not necessarily smaller thanincBF

i,l . Therefore, the sign of LBF(bi,l | y ′i ) should be adjusted

to positive or negative according to the corresponding bit valueof bML

i,l . It should also be mentioned that incMLi in (12) has

already been calculated during tree search, which can thus bereused in bit-flipping for hardware saving.

So far, we may have two possible LLRs for each bit, whichare acquired by FSD tree search (LFSD

bl) and the bit-flipping

scheme presented above (LBFbl

). The final result is selectedaccording to the magnitude of these two candidates

L(bl) =

⎧⎪⎨

⎪⎩

LBFbl

, if |LBFbl

| ≤ |LFSDbl

| or L ∩ χMLl = ∅

LFSDbl

, otherwise.(13)

The selection criteria in (13) finds the minimum of |LBFbl

| and|LFSD

bl|, which is efficient in relieving the problem of getting

the pseudo-minimum of (10), leading to a more accurateapproximation of the MAP result.

2) Complexity Reduction With Polygon-Shaped Constraint:According to the analysis in Section III-A1, the exhaustiveexpansion at upper layers of the FSD tree introduces a lot ofcomputational waste by including vectors with large Euclideandistances in the candidate list. To reduce such unnecessaryvisits to some nodes, we adopt the imbalanced-expansiontechnique proposed in [24] to find the list of vectors closerto the ML result. This technique is briefly repeated here forconvenience of presentation.

The concept of imbalanced-expansion is to approximatethe circular-shaped constraint in a sphere decoder [17] witha polygon-shaped constraint, as illustrated in Fig. 2. Thepolygon constraint is realized by introducing an extensionnumber limitation Lm

i , by which only the Lmi best nodes are

extended from the mth father node at the i th (i > 2N − D)layer. The detailed explanation can be found in [24], wherea smaller Lm

i is set for the node with larger PED to expandmore/fewer branches from more/less reliable nodes. Moreover,considering that the FSD performs full extension only at thefirst two real-valued tree-search layers for a 4 × 4 system, Lm

iis applied only for the (2N − 1)th layers, i.e., i = 2N − 1(the constraint to the top layer is accomplished by setting thecorresponding Lm

2N−1 to 0).

received signal

r2

Fig. 2. Polygon-shaped constraint with L2N−1 = [5, 5, 3, 3, 1, 1, 0, 0].

Compared to the radius constraint, the polygon-shapedconstraint is more efficient from a hardware implementationperspective. First, with a radius constraint r2, a node dissatis-fying the constraint will not be pruned until its PED is com-pletely calculated and compared with r2. On the other side, thepolygon-shaped constraint with extension number limitationearly prunes less reliable paths before PED calculations byusing the well-known zigzag enumeration technology [25].Moreover, the number of nodes to be extended is fixed witha given constraint L2N−1 = [L1

2N−1, . . . , L√

M2N−1], which is

not the case for radius-constrained algorithms where the nodeextension number is variable depending on the channel andthe noise. Therefore, the polygon-constraint algorithm has avery regular data flow and the corresponding control circuitrycan be significantly simplified. Finally, the proposed schemeis convenient in tuning the complexity-performance tradeoffby setting L total = ∑

L2N−1 to a smaller/larger number.3) Application to SDMA Mode: The aforementioned FSD

detection is originally developed for SM signal. In the follow-ing, the algorithm is modified to be adopted for the SDMAmode. Detecting downlink SDMA signals is unique in thatonly signals dedicated to the kth user (i.e., sk) are reserved,while the signals intended for other users (i.e., sl,l =k ) are dis-carded after detection [26]. To take full utilization of this fea-ture, we add a layer-reordering step to the pre-processing stageof FSD such that the desired signal sk is moved to the top layerof the FSD search tree where multiple candidates are extended.The reordering is accomplished by a permutation matrix Wk,which moves the kth column of the channel matrix Hk to thelast position, i.e., Wk = [w1, . . . wk−1, wk+1, . . . , wK , wk],where wi denotes an N × 1 vector whose i th element isone and zeros elsewhere. Therefore, the system model canbe rewritten as

rk = Hk Wk sPk + nk = H P

k sPk + nk (14)

where s Pk = [s1, . . . sk−1, sk+1, . . . , sK , sk ]T is the transmit

vector with sk being moved to the last position. Taking thereordered channel matrix H P

k as an input, the imbalanced-FSD



tree search in Section III-A2 is then conducted to get a list ofcandidate vectors, based on which the LLRs corresponding tosk are computed.

Since multiple candidates of sk are extended at upper layers,it can be expected in the final list that sk has a good diversity inits bit values. Moreover, the single-extension at the remaininglayers attaches only the best node of sl,l =k to the candidatesof sk . Hence, it is highly likely that the final list contains theactual minimum of (10) for the bits corresponding to sk . Inview of the above analysis, the candidate list obtained by thelayer-reordered FSD tree search is good enough to generatehigh-quality soft values for sk . Thereby, we can turn off thebit-flipping operation in SDMA mode in order to reduce powerconsumption.

B. Linear-Complexity MAP Detection for SD Mode

Both the IEEE 802.16m and 3GPP-LTE standards adoptthe frequency domain version of Alamouti code as the trans-mission diversity scheme, where pairs of adjacent sub-carriersare coded together to keep the orthogonality in fast-changingchannels. In addition, in order to provide robustness againstantenna correlations, the application of SFBC in both standardsis limited to two physical antennas [6]. For example, in LTEthe signals with four transmit antennas are coded as

⎡⎢⎢⎣

s11 s1

2 s13 s1

4s2

1 s22 s2

3 s24

s31 s3

2 s33 s3

4s4

1 s42 s4

3 s44

⎤⎥⎥⎦ =

⎡⎢⎢⎣

x1 x2 0 00 0 x3 x4

−x∗2 x∗

1 0 00 0 −x∗

4 x∗3

⎤⎥⎥⎦ (15)

where s ji is the complex signal transmitted from the j th

antenna at the i th subcarrier. By leveraging these properties,we demonstrate a linear-complexity MAP detection basedon QR decomposition to the orthogonal real-valued channelmatrix. In addition, the introduced detection unifies the pro-cedures for both 2 × 2 and 4 × 4 MIMO. That is, the receivercan use identical processing to detect Alamouti signals, whichis independent of the antenna number N .

Without loss in generality, we take the detection of x1 andx2 as an example to illustrate the algorithm. For decodingAlamouti signals, we process the signals in a per antennamanner instead of the per subcarrier vector detection in SMand SDMA modes. With the assumption that the channel isfrequency flat, at least over two sub-carriers, the receivedsignals at the j th antenna are formulated as

[r j

1

(r j2 )∗

]=

[H j,1 −H j,3

H ∗j,3 H ∗

j,1

][x1x∗

2

](16)

where r jn (n = 1, 2) is the signal received at the j th antenna

of subcarrier n and H j,i (i = 1, 3) is the channel between thei th transmit antenna and j th receive antenna. To simplify theexpression, the noise is ignored in the derivation. By adoptingthe orthogonal real-value decomposition shown in (2) and (3),the complex Alamouti system model in (16) is rewritten asr j = H j x, where

r j = [�(r j1 ),�(r j

1 ),�(r j2 ),−�(r j

2 )]T

x = [�(x1),�(x1),�(x2),−�(x2)]T (17)

and

H j=

⎡⎢⎢⎣

�(H j,1) −�(H j,1) −�(H j,3) �(H j,3)

�(H j,1) �(H j,1) −�(H j,3) −�(H j,3)

�(H j,3) �(H j,3) �(H j,1) �(H j,1)

−�(H j,3) �(H j,3) −�(H j,1) �(H j,1)

⎤⎥⎥⎦. (18)

The real-valued matrix H j owns two very important proper-ties: 1) all columns of H j are orthogonal to each other, and2) H j has the same element, i.e., �(H j,1), at its diagonalpositions. With these two features, the QR-decompositionof H j (i.e., H j = Q j R j ) results in a diagonal matrixR j = d j I4. Multiplied by QH

j , the system model for thej th antenna becomes y j = R j x, where y j = QH

j r j .Utilizing the diagonal matrix R j , a low-complexity maximal-ratio combining (MRC) of the signals received at each antennais conducted to produce the final system model as y = Rx,in which

y = [y1, y2, y3, y4]T =N∑

j=1

y j

R =N∑

j=1

R j =N∑

j=1

d j I4 = d I4. (19)

The soft values are obtained by performing the MAP detectionfor each real-valued component in y independently as

L(bi,l | yi ) = minbi ∈χ0

l

1

N0|yi − dxi |2 − min

bi ∈χ1l

1

N0|yi − dxi |2.

(20)

Compared to the original MAP detection in (6), the complexityof (20) is significantly lower, which is linear to the real-valued constellation size (i.e.,

√M) by decoding the real

and imaginary parts of x1 and x2 separately. It is worthreemphasizing that the presented algorithm is conducted usingalmost the same operations for different antenna configurationswith a minor difference in the parameter N of (19).

C. Performance Simulation

The performance of the presented detection algorithms isevaluated using simulations. The simulation setup is based ona simplified LTE downlink system with 64-QAM modulationand 4 × 4 antenna configuration. The system bandwidth is5 MHz and the number of sub-carriers is 512, of which300 sub-carriers are used for the information transmission.For multipath fading propagation, we apply the EVA channelmodel described in [13]. There are nine paths in the channelwith a largest delay of 2510 ns. In addition, we assume that thereceiver has perfect channel knowledge. The error correctingcode is the rate Rc = 1/3 parallel concatenated turbo codespecified in the LTE standard [14]. The generator polynomialsg0(D) = 1+ D2 + D3 and g1(D) = 1+ D + D3 are employedtogether with an internal interleaver of size 6144. The numberof turbo decoder iterations is set to six. Since the proposedalgorithm for SD mode is theoretically an MAP detection, itsperformance will not be presented in this section.



9 9.5 10 10.5 11 11.5

10-4

10-3

10-2

10-1

100

SNR (dB)

BER

Early-pruned FSD with bit-flip(L2N-1=[33322111])Early-pruned FSD with bit-flip(L2N-1=[55330000])Early-pruned FSD with bit-flip(L2N-1=[54322000])

Fig. 3. Simulated BER performance in SM transmission with L total = 16but different L2N−1 distributions.

received signal

L2N-1=[55330000]L2N-1=[54322000] L2N-1=[33322111]

Fig. 4. Constraint shapes of different L2N−1 distributions.

1) Effects of L2N−1 Distribution: Fig. 3 shows thesimulated bit-error rate (BER) of the proposed SM detectionalgorithm with a same L total (e.g., L total = ∑

L2N−1 = 16)but different L2N−1 distributions. The best detection per-formance is attained when L2N−1 = [5, 4, 3, 2, 2, 0, 0, 0].Associated with the corresponding constraint shapes plottedin Fig. 4, we observe that the early-pruned FSD algorithm(with bit-flipping scheme) performs better when the pruningparameter L2N−1 leads to a constraint that better approximatesthe circular-shaped admissible region.

2) Performance With Different Ltotal: Fig. 5 shows theBER of the early-pruned FSD with different L total values.It can be seen that the complexity-performance tradeoffscan be tuned by adjusting L total and a better performance isobtained with a larger L total. We also compared the proposedalgorithm with other fixed-complexity soft-output detections,e.g., MMSE [27], K-Best (K = 64) [16], and list FSD(LFSD) [19]. LLR values of ±8 are adopted for non-existingbits in these algorithms. Our algorithm offers better

9 10 11 12 13 1410-6

10-5

10-4

10-3

10-2

10-1

100

SNR (dB)

BER

Our algorithm with Ltotal=20Our algorithm with Ltotal=16Our algorithm with Ltotal=12K-best detection with K=64List FSD with NS

e/NL=256/64

MMSE

Fig. 5. Simulated BER performance in SM transmission with different L total.

9 9.5 10 10.5 11 11.510-6

10-5

10-4

10-3

10-2

10-1

100

SNR (dB)

BER

Early-pruned FSD with bit-flip (top layer)Early-pruned FSD without bit-flip (top layer)Early-pruned FSD with bit-flip (other layers)Early-pruned FSD without bit-flip (other layers)

Fig. 6. Simulated BER performance in SDMA transmission with thedemonstration of how the bit-flip affects different layers.

performance than other fixed-complexity tree-searchdetections with a much smaller candidate list size(e.g., L total = 16 in our algorithm comparing to K = 64 inK-Best detection and NL in LFSD). This is mainly achievedby the bit-flipping technique, which not only provides fullbit-value diversity for LLR computation but also improvesits reliability by outputting the final LLR with the minimaof LBF and LFSD.

3) Performance of SDMA Detection: Fig. 6 shows the BERof the SDMA detection. To demonstrate the effectiveness ofthe layer-reordering scheme described in Section III-A3, wecompared the performance when the signals are detected at thetop layer and other layers (both with and without bit-flipping).Due to the multinode extension, the performance degradationis minor without bit-flipping when signals are detected atthe top layer. On the other hand, huge performance loss ispresented for the detection at the remaining layers. Therefore,the layer-reordering strategy provides us the opportunity to



turn off the bit-flipping operation in SDMA mode to savepower at the price of small performance degradation.

IV. VLSI ARCHITECTURE FOR MULTIMODE

MIMO DETECTION

In this section, we describe the unified VLSI architecturefor implementing the soft-output MIMO detection algorithms.As shown in Fig. 7, the detector consists of three major partsto support the detection of SM, SDMA, and SD signals ofup to 64-QAM modulation with 4 × 4 MIMO configuration.First, a tree search block (TSB) conducts the real-valued treesearch using the early-pruned FSD algorithm and generatesa list of candidate vectors L. Then, a list LLR calculationblock (LLCB) calculates soft values based on these vectors andtheir corresponding Euclidean distances [i.e., the computationof (8)]. Finally, a bit-flip block (BFB) computes LLRs withthe symbol-level bit-flipping method and selects the final softoutput according to (13).

A. Tree Search Block

The TSB is basically a hard-output MIMO detector [24].It has four stages of process elements (PEs), correspondingto the eight layers of the real-valued search tree in the caseof 4 × 4 MIMO configuration. Each stage computes twoadjacent tree layers independently and concurrently. Thisis due to the fact that Ri,i+1 = 0 (i = 1, 3, . . . , 2N − 1)when QR-decomposition is performed to the orthogonalreal-valued representation of the channel matrix [24], [28],[29]. There are three function blocks involved in each PE:1) an interference cancelation unit (ICU), which suppressesinter-antenna interference introduced by previously detectedsignals [i.e., the computation of y ′ in (7)]; 2) a node selectionunit (NSU) that selects the to-be-detected nodes using thereal-value zigzag enumeration method [25]; and 3) a PEDcalculation unit (PCU), which computes the accumulatedPED according to (7). In TSB, PEs are grouped into twotypes: 1) PE-A conducts the imbalanced-extension at theseventh and eighth layer with ICU excluded, and 2) PE-Bperforms single-node extension for the remaining layers.In our design, node computations at each stage are carriedout in a partial-parallel time-multiplexing fashion, i.e., thePE processes four nodes simultaneously per iteration andcompletes the computation of all L total nodes in C = 1/4L total

cycles. This architecture supports different L total values byadjusting the iteration time C . For example, when a largerL total is required for better performance, the number ofiteration cycles is increased to include more candidate vectorsin L at the price of throughput reduction. In addition, theintermediate results (e.g., y ′ and inci ) of TSB are depositedinto registers to be reused in the bit-flipping operation, leadingto further hardware savings. It should be reemphasized thatTSB takes 1/4L total cycles to generate the candidate list Lby outputting a size-four candidate vector list Li per clockcycle.

B. List LLCB

Accepting the candidate vector list (L) and their Euclideandistances (T ) as inputs, the LLCB first translates the symbol

Fig. 7. Proposed VLSI architecture for the multimode MIMO detector.

vector to its corresponding bit vector (b) with the Demap unit,which are then sorted according to the ascending order of T .Given these sorted results, the metric update unit (MUU) findssML and T ML in (9) and the corresponding T ML in (10) foreach bit of the transmitted N log2(M)-length binary vector.As illustrated in Fig. 8, the MUU is basically a metric table,where each cell maintains the best path metric (i.e., Euclideandistance) among the candidates that may have the value 1 or 0on the specified positions. More specifically, the metric tablein our design is divided into two groups: one ML componentand N log2(M) ML components. The ML cell contains the MLbit vector (i.e., bML) and its Euclidean distance (i.e., T ML).The lth ML cell stores the best path metric (T ML

l ) with itscorresponding binary vector having the lth bit value differentto bML, e.g., bML

l satisfying (10).In most reported soft-output MIMO detectors [15]–[17],

the metric table processes only one candidate symbol perclock cycle, which destroys the parallelism of the detectorarchitecture and decreases the detection throughput. Makinguse of the fact that the incoming candidate vectors are strictlysorted, we design a parallel MUU, capable of handling multi-ple vectors simultaneously using simple and implementation-friendly operations. Specified in our detector, the metric tableprocesses four vectors per clock cycle compatible with theparallel strategy adopted in the TSB. The proposed parallelmetric update algorithm is initialed with T ML = T ML = ∞.Whenever the sorted candidate vectors (i.e., [b1, b2, b3, b4]with T 1 ≤ T 2 ≤ T 3 ≤ T 4) are available, the ML tablecompares T ML with the best metric T 1 and refreshes the cor-responding registers with min(T ML, T 1). The ML bit vectorbML is updated accordingly. The structure of the lth ML metrictable is shown in Fig. 8. The first step of ML metric update isto find among [T 2, T 3, T 4] the best metric (denoted by T 1)whose binary vector has the lth bit value different to b1

l . Incase that b1, b2, b3, and b4 have the same value on the lthbit, T 1 is set to ∞. The remaining procedure for updatingML table is divided into following three cases by using theproperties that T ML is always smaller than T ML and T 1 is nolarger than T 1.



ML

bit

ML3 ML2 ML1

ML6 ML5 ML4

ML9 ML8 ML7

ML21 ML20 ML19

ML24 ML23 ML22

layer

Tml bml<

T1 b1

T1

. . .

T2 T3 T4

b1^b2b1^b3b1^b4T1 T1 Tml

a1=b1^bmla2=T1>Tml

a1a2

< Tml

(a) (b)

Fig. 8. MUU. (a) Overall structure, including one ML component and 24 ML components. (b) Detailed circuit for each ML component.

-7 -5 -3 -1 1 3 5 7

111 110 100 101 001 000 010 011

-7 -5 -3 -1 1 3 5 7

111 110 100 101 001 000 010 011

-7 -5 -3 -1 1 3 5 7

111 110 100 101 001 000 010 011

b1

b2

b3

Fig. 9. Examples of gray-coded 64-QAM points (real-valued) and the flipping schemes of different bits.

1) If bML agrees with b1 on the lth bit value, i.e.,bML

l ˆb1l = 0, T ML is updated with min(T ML, T 1).

2) If bML disagrees with b1 on the lth bit value, i.e.,bML

l ˆb1l = 1 and T ML has been updated with T 1, i.e.,

T ML > T 1, T ML is replaced by min(T ML, T 1).3) If bML

l ˆb1l = 1 but T ML remains unchanged in the ML

metric update process, i.e., T ML ≤ T 1, T ML is updatedwith min(T ML, T 1).

The throughput can be effectively enhanced by the pro-posed parallel metric update scheme. More importantly, theoperations involved in this MUU contain only exclusive OR,comparison, and multiplex selection, which are suitable forlow-cost hardware implementation. The MUU obtains the finalT ML, bML, and T ML within 1/4L total clock cycles and sendsthem to the LLR calculation unit (LCU) to finish the LLRcomputation.

C. Bit-Flip Block

The BFB includes a bit-flipping LLR calculation unit(BFLCU) and an LLR selection unit (LSU). For the lth bitof the ML vector bML, BFLCU executes the symbol-level bit-flipping scheme according to (12). The objective is to findthe best bit-flipped symbol, denoted by sML

l , which ownsthe smallest Euclidean distance among the symbols havingthe lth bit value opposite to bML. Instead of calculating the

Euclidean distances of all M/2 possible bit-flipped symbolsand finding the minimum with extensive comparison, wepropose to observe the location of sML in the constellationplane and then select sML

l with simple boundary check. Here,we take the gray-coded modulation scheme adopted in LTEsystem [30] as an example, where a specific bit changes onlyI or Q branch of the modulated signal. More specifically,among the logM

2 bits, the logM2 /2 odd bits determine the

position of the modulated signal on the I-axis, and the even bitsdetermine the position on the Q-axis. Hence, the bit-flippingcan be conducted for the real and imaginary signals separately,compatible with the real-value decomposed system in thispaper. The real-valued 64-QAM constellation (or equivalently,the eight-PAM modulation) adopted in 3GPP-LET is shownFig. 9, where the boundaries (dashed lines) for flipping the bitb1, b2, and b3 are illustrated. Exploiting the above regularity,the selection of sML

l can be accomplished conveniently withboundary and sign-bit check. For example, the best bit-flippedsymbol corresponding to the first bit (i.e., b1) is obtainedby only checking the sign-bit of sML and setting sML

1 to−sign(sML) × 1. In Fig. 10, the detailed circuit diagramsof the bit-flipped symbol selection for b1, b2, and b3 aredemonstrated, respectively.

LSU receives two possible LLR values, which, respectively,are obtained by the LLCB (LFSD) and the BFLCU (LBF) andselects the final LLR based on the criteria shown in (13).



sign

<4R

35

SML

S2ML

sign

+1-1

SML

S1ML

(a) (b)

(c)

sign

<2R 1S3ML

SML

4R

6R<<

LUT

357

Fig. 10. Circuit diagram for bit-flipped symbol selection with for (a) firstbit b1, (b) second bit b2, and (c) third bit b3.

y

NSU

PCU

y

T

y

s

T

y

T

PE-A

RR R

s

RTSB

SortT

Dem

ap

b

LC

U

bML

TML

TML

LLCB

BFL

CU

LSU

Llist

Rs y’ inc

bML

Llist

Lbf

L

BFB

NSU

ICU

PCU

PE-B

sML

PE-B

PE-B

MLbML TML

MUU

ML

ss

sML

Fig. 11. Date path when the detector is configured to SD mode.

D. Data-Path to Other Detection Modes

In this section, we present how the proposed architectureis reconfigured to realize the detection of SD and SDMAsignals. The operations for SDMA mode are similar to SMwith the minor difference that the LLRs are only calculatedfor the symbol dedicated to the kth user (i.e., sk). Therefore,we simply by-pass parts of the units in the LLCB for SDMAsignal detection, such as the ML cells ML7 − ML24 in Fig. 8.The TSB is completely reused in these two modes. Moreover,as mentioned in Section III-A3, the computation of LLRfor SDMA signals is based only on the candidate vectorsgenerated by the tree search process. Therefore, the BFB isalso turned off, using clock gating, in SDMA mode to savepower.

According to the description in Section III-B, the proceduresinvolved with the SD signal detection can be decomposed intotwo parts: the MRC shown in (19) and the LLR calculationshown in (20). Thanks to the diagonal property of matrixR in (19), the MRC in our algorithm has been substantially

Fig. 12. Layout of the detector core.

TABLE I

AREA PARTITION BY FUNCTION BLOCKS

Function Blocks Gate Count Percentage

TSB 46.4 KG 55.4%

List LLCB 11.7 KG 14%

BFB 12.6 KG 15.1%

Other Logic 13 KG 15.5%

TABLE II

DETECTION THROUGHPUT AND POWER/ENERGY

CONSUMPTION OF DIFFERENT MIMO MODES

MIMO Mode ThroughputPower Energy

Consumption Consumption

SM 1 Gb/s 59.3 mW 59.3 pJ/b

SDMA 250 Mb/s 42.4 mW 169.6 pJ/b

SD 1 Gb/s 10.5 mW 10.5 pJ/b

simplified to contain only real additions. As a consequence,we use the ICU in the last stage of PE, mainly composedof accumulations, to conduct the MRC operation. The maintask of calculating (20) is to find two minimum Euclideandistances with the corresponding bit vectors having the lthvalue equal to 1 and 0, respectively. Due to the diagonalproperty of the equivalent channel matrix R in (19), thisminima-search procedure is conducted for each real-valuedscalar symbol independently, which is then equivalent to thesymbol-level bit-flipping operation in the SM signal detectionalgorithm, i.e., (12). As a result, instead of searching all

√M

real-valued constellation points, the LLR computation in SDmode can be divided into two steps. The first step is to getthe ML scalar symbol (sML) using the NSU in the last stageof type-B process element (PE-B), which performs single-node extension by finding the best scalar symbol of eachfarther node. The second step is to find another minimumsymbol (sML

l ) with its lth bit value different to sML andcompute the deviation of their Euclidean distances. This jobcan be accomplished by the BFLCU in the BFB. Based onthe above analysis, the detailed data-path when the detectoris configured to SD mode is given in Fig. 11 (the black partsare active data-paths, while the grey parts are disabled withclock-gating technique). It is worthwhile to mention that theproposed architecture is capable of detecting SD signals in



TABLE III

COMPARISON OF THIS PAPER TO PREVIOUS 4 × 4 SOFT-OUTPUT MIMO DETECTORS

JSAC’ 06 [15] TVLSI’ 07 [16] TVLSI’ 11 [21] JSSC’ 12 [31] ISCAS’ 10 [20] This Paper

MIMO Modes SM SM SM SM SM SM/SD/SDMA

Antenna Size 4×4 4×4 4×4 4×4 4×4 4×4

Modulation 16-QAM 64-QAM 64-QAM 64-QAM 64-QAM 64-QAM

AlgorithmSoft-output Soft-output Soft-output SISO Soft-output Early-pruned FSD

K-best K-best best-first MMSE-PIC K-best with bit-flip

Process Technology 0.18 μm 0.13 μm 65 nm 90 nm 65 nm 65 nm

Max. Clock Rate 200 MHz 270 MHz 333 MHz 568 MHz 833 MHz 167 MHz

Throughput 106.6 Mb/s 8.57 Mb/s 83.3 Mb/s 757 Mb/s 2 Gb/s 1 Gb/s

Core Area 0.56 mm2 2.38 mm2 N/A 2 1.5 mm2 0.57 mm2 0.25 mm2

Gate Count 97 kGa 280 kGa 64 kGa 410 kGb/160 kGa 298 kGa 83.7 kGa

Hardware Efficiency 0.91 kG/(Mb/s)a 32.67 kG/(Mb/s)a 0.77 kG/(Mb/s)a 0.21 kG/(Mb/s)a 0.15 kG/(Mb/s)a 0.084 kG/(Mb/s)a

Power Consumption N/A94 mW 11.5 mW 189.1 mW 280 mW 59.3 mW @ 1.2 V

@ 1.2 V @ 1.0 V @ 1.2 V @ 1.3 V (SM mode)

NormalizedN/A 47 mW 16.6 mW 136.6 mW 238.6 mW 59.3 mW

Power Consumption

NormalizedN/A 5484 pJ/b 199.2 pJ/b 180.4 pJ/b 119.3 pJ/b 59.3 pJ/b

Energy Consumptiona The gate count without the pre-processing operations to channel decomposition.b The gate count, including the pre-processing operations to channel decomposition.

a fully parallel fashion, leading to an enormous throughputenhancement. This is a consequence of the fact that PE-B inthe detector simultaneously deals with four nodes per clockcycle and the number of symbols to be processed in our SDdetection has also been fixed to four (e.g., the parameter i in(20) is within the range of [1, 2, 3, 4]).

The proposed architecture is also flexible in supportingdifferent modulations and antenna configurations (MACs).The multistage PE structure and the candidate sharingscheme [24] in TSB are used for supporting multiple antennanumbers and constellation sizes, respectively. Additionally,LLCB can also be configured to process different MACs byactivating different ML cells. For example, only ML cellsML1−ML12 are used when the detector is configured to 2 × 264-QAM mode. Finally, we use sub-sets of the bit-flippingcircuitry for different modulations, i.e., Fig. 10(a)–(c) for64-QAM, [(a) and (b)] for 16-QAM, and only (a) for QPSK.Accordingly, the checking boundaries are changed in differentmodulations, e.g., sML

2 is selected from sign(sML) × [1, 3] for16-QAM, by comparing |sML| with 2R.

V. IMPLEMENTATION RESULTS AND COMPARISON

The designed triple-mode soft-output MIMO detector ismodeled in Verilog hardware description language (Verilog-HDL), synthesized using Synopsys Design Compiler with a65-nm CMOS standard digital cell library, and routed usingCadence SoC encounter/silicon ensemble. We use 12 b forthe PEDs and eight bits for the output LLRs, which havebeen decided by fixed-point simulations. Fig. 12 shows thelayout of the detector core, which occupies 0.25 mm2 area(at 68% cell density) and takes 83.7 K equivalent gates. Here,an equivalent gate is counted as the size of a two-input NAND

gate. The pre-processing to the channel matrix (e.g., real-value decomposition and QR decomposition) is not included

in this implementation. To enable a more comprehensiveunderstanding of the hardware resource distribution, the totalcore area is partitioned by function blocks, as shown in Table I.We can see that the extra area required to support soft-outputgeneration (i.e., list LLCB and BFB) is approximately anadditional 50% to that required by the hard-output detector(i.e., TSB).

At normal 1.2-V core power supply, the detector can operateat a clock rate of 167 MHz for all the three MIMO modes.The maximum allowable clock rate is obtained by post-layoutsimulation with delay information back annotated in SDFformat. With clock frequency fc, the throughput of the detectoris formulated as

Throughput = fc × RSFC × logM2 ×N

C(21)

where M is the constellation size, N is the antenna number,RSFC is the coding rate of the space-frequency code, andC is the number of clock cycles needed for calculating theall nodes. The parameter RSFC = 1 for SM transmissionand RSFC = 1/N in SDMA mode, since only one layer ofsignal is transmitted for each user. As a result, the detectionthroughput in SDMA mode is lower than that in SM mode.The pair-wise Alamouti space-frequency code is adopted inSD mode, in which RSFC is set to 1/2. In the post-outsimulation, L total is set to 16. Therefore, C equals to 4in SM/SDMA detection and 1 in SD detection. Table IIsummarizes peak throughput when the detector is configuredto different MIMO modes. To investigate power efficiency,power simulations were conducted for the post-layout designannotated with switching activities. Operating at 167 MHz,the detector consumes 59.3-mW core power with 1.2-V supplyvoltage and 25 °C temperature when configured to SM mode.The corresponding energy consumption per bit detection is



59.3 pJ/b. When configured to SD and SDMA mode, thedetector uses a clock-gating technology for those shieldedfunction blocks to achieve low power. The power and energyconsumption in these modes is also tabulated in Table II. Thepower consumption is much lower in SD mode by closinglarge parts of the function blocks, as demonstrated in Fig. 11.On the other hand, the SDMA signal detector reuse most of theblocks except for BFB and parts of LLCB, and thus consumesslightly less power than the SM detector. Thereby, the detectorconsumes the highest energy when configured to SDMA modedue to the low detection throughput.

Table III lists the overall performance of our detector andseveral recently reported 4 × 4 soft-output detectors. Theproposed detector is the only one that supports the signaldetection of SM, SD, and SDMA MIMO modes. Despitethe superiority of this reconfigurable multimode property, ourdetector demonstrates the best hardware efficiency, which iscalculated by normalizing the number of equivalent gate countto the detection throughput. The cost reduction is mainly pro-vided by the algorithm-architecture co-design method, whichreuses the same building blocks in different MIMO modes.Besides, the symbol-level bit-flipping strategy is capable ofgenerating high-quality LLRs with very small hardware over-head. Moreover, it allows for extensive branch pruning in thetree search, which reduces the cost significantly by savinga huge amount of hardware-consuming Euclidean distancecalculations. For example, as demonstrated in Fig. 5, ourtree-search algorithm expands only 16 branches to provide asimilar detection performance to the K-Best algorithm in [16]where 64

√M branches are calculated at each layer. Although

our detector does not demonstrate the highest throughputamong the reported implementations, it is one of the very fewdetectors that achieve gigabit-per-second throughput to meetthe requirement of next-generation cellular system. To ensure afair enough comparison, the power consumption in Table III isnormalized to the 65-nm technology and 1.2-V supply voltageand is formulated as

Powernorm = Power ×(

1.2 V

Voltage

)2

× 65 nm

Technology. (22)

VI. CONCLUSION

This paper, for the first time, presented the VLSI imple-mentation of a triple-mode soft-output MIMO detector thatsupports the detection of SM, SDMA, and SD signals. Thisdesign applied algorithm-level modifications to a FSD, suchas early-prune technology with polygon-shaped constraint andsymbol-level bit-flipping, to improve the soft informationaccuracy. In addition, an antenna-number-independent MAPalgorithm was shown to be very effective in detecting Alam-outi signals. In terms of VLSI implementation, a unifiedarchitecture was developed to be reconfigured to supportdifferent MIMO modes, leading to extensive hardware saving.Moreover, several circuit-level techniques were adopted in thedesign of function blocks to further improve the implemen-tation efficiency. Post-layout simulation results have shownthat the proposed detector reaches gigabit-per-second detectionthroughput and outperforms the other reported works in terms

of multimode support capability, hardware efficiency (44%saving in normalized gate count) as well as energy efficiency(50% reduction in energy consumption).

REFERENCES

[1] T. Nakamura, “Requirements for further advancements for evolveduniversal terrestrial radio access (E-UTRA) (LTE-advanced),” StanfordRes. Inst., Stanford, CA, Tech. Rep. 36.913, Dec. 2008.

[2] System Requirements. (2010) [Online]. Available:http://ieee802.org/16/tgm/docs/80216m-07_002r4.pdf

[3] Overview of 3GPP Release 10 V0.0.8. (2010) [Online]. Available:http://www.3gpp.org/ftp/Information/WORK_PLAN/Description_Rele-ases/Rel-10_description_20100924.zip

[4] P. W. Wolniansky, G. J. Foschini, G. D. Golden, and R. A. Valenzuela,“V-BLAST: An architecture for realizing very high data rates over therich-scattering wireless channel,” in Proc. Int. Symp. Signals, Syst.,Electron., Sep. 1998, pp. 295–300.

[5] B. C. Kian, A. Doufexi, and S. Armour, “On the performance ofSU-MIMO and MU-MIMO in 3GPP LTE downlink,” in Proc. IEEEInt. Symp. Pers. Indoor Mobile Radio Commun. Conf., Sep. 2009,pp. 1482–1486.

[6] Q. Li, G. Li, W. Lee, M. Lee, D. Mazzarese, B. Clerckx, and Z. Li,“MIMO techniques in WiMAX and LTE: A feature overview,” IEEECommun. Mag., vol. 48, no. 5, pp. 86–92, May 2010.

[7] B. M. Hochwald and S. Brink, “Achieving near-capacity on a multiple-antenna channel,” IEEE Trans. Commun., vol. 51, no. 3, pp. 389–399,May 2003.

[8] G. Bauch and G. Dietl, “Multiuser MIMO for achieving IMT-Advanced requirements,” in Proc. Int. Conf. Telecommun., Nov. 2008,pp. 1–7.

[9] C. Spiegel, J. Berkmann, B. Zijian, T. Scholand, and C. Drewes, “MIMOschemes in UTRA LTE, a comparison,” in Proc. IEEE Veh. Technol.Conf., May 2008, pp. 2228–2232.

[10] L. G. Barbero and J. S. Thompson, “Fixing the complexity of the spheredecoder for MIMO detection,” IEEE Trans. Wireless Commun., vol. 7,no. 6, pp. 2131–2142, Jun. 2008.

[11] V. Tarokh, H. Jafarkhani, and A. Calderbank, “Space-time block codingfor wireless communications: Performance results,” IEEE J. Sel. AreasCommun., vol. 17, no. 3, pp. 451–460, Mar. 1999.

[12] S. Alamouti, “A simple transmit diversity technique for wireless commu-nications,” IEEE J. Sel. Areas Commun., vol. 16, no. 10, pp. 1451–1458,Oct. 1998.

[13] User Equipment (UE) Radio Transmission and Reception (Release10). (2008) [Online]. Available: http://www.3gpp.org/ftp/Specs/archive/36_series/36.101/36101-a11.zip

[14] Physical Layer Procedures (Release 9). (2010) [Online]. Available:http://www.3gpp.org/ftp/Specs/2010-03/Rel-9/36_series/36213-910.zip

[15] Z. Guo and P. Nilsson, “Algorithm and implementation of the K-bestsphere decoding for MIMO detection,” IEEE J. Sel. Areas Commun.,vol. 4, no. 3, pp. 491–503, Mar. 2006.

[16] S. Chen, T. Zhang, and Y. Xin, “Relaxed K-best MIMO signal detectordesign and VLSI implementation,” IEEE Trans. Very Large Scale Integr.(VLSI) Syst., vol. 15, no. 3, pp. 328–337, Mar. 2007.

[17] C. Studer, A. Burg, and H. Bolcskei, “Soft-output sphere decoding:Algorithms and VLSI implementation,” IEEE J. Sel. Areas Commun.,vol. 26, no. 2, pp. 290–300, Feb. 2008.

[18] C.-H. Liao, T.-P. Wang, and T.-D. Chiueh, “A 74.8 mW soft-outputdetector IC for 8×8 spatial-multiplexing MIMO communications,” IEEEJ. Solid-State Circuits, vol. 45, no. 2, pp. 411–421, Feb. 2010.

[19] L. G. Barbero and J. S. Thompson, “Extending a fixed-complexity spheredecoder to obtain likelihood information for turbo-MIMO systems,”IEEE Trans. Veh. Technol., vol. 57, no. 5, pp. 2804–2814, Sep. 2008.

[20] D. Patel, V. Smolyakov, M. Shabany, and P. G. Gulak, “VLSI imple-mentation of a WiMAX/LTE compliant low-complexity high-throughputsoft-output K-best MIMO detector,” in Proc. IEEE Int. Symp. CircuitsSyst. Conf., May 2010, pp. 593–596.

[21] C.-A. Shen, A. M. Eltawil, K. N. Salama, and S. Mondal, “A best-firstsoft/hard decision tree searching MIMO decoder for a 4 × 4 64-QAMsystem,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20,no. 8, pp. 1537–1541, Aug. 2011.

[22] J. Jalden, L. G. Barbero, B. Ottersten, and J. S. Thompson, “The errorprobability of the fixed-complexity sphere decoder,” IEEE Trans. SignalProcess., vol. 57, no. 7, pp. 2711–2720, Jul. 2009.



[23] V. Ponnampalam, D. McNamara, A. Lillie, and M. Sandell, “On gener-ating soft outputs for lattice-reduction-aided MIMO detection,” in Proc.IEEE Int. Conf. Commun., May 2007, pp. 4144–4149.

[24] L. Liu, J. Löfgren, and P. Nilsson, “Area-efficient configurable high-throughput signal detector supporting multiple MIMO modes,” IEEETrans. Circuits Syst. I, Reg. Papers, vol. 59, no. 9, pp. 2085–2096,Sep. 2012.

[25] M. Wenk, M. Zellweger, A. Burg, N. Felber, and W. Fichtner, “K-bestMIMO detection VLSI architectures achieving up to 424 Mb/s,” in Proc.IEEE Int. Symp. Circuits Syst. Conf., May 2006, pp. 1151–1154.

[26] S. Dragan, L. Angel, and B. P. Constantinos, “Design and experimentalvalidation of MIMO multiuser detection for downlink packet data,”EURASIP J. Appl. Signal Process., vol. 11, pp. 1769–1777, Jan. 2005.

[27] P. Fertl, J. Jalden, and G. Matz, “Capacity-based performance compar-ison of MIMO-BICM demodulators,” in Proc. IEEE Workshop SignalProcess. Adv. Wireless Commun. Conf., Jul. 2008, pp. 166–170.

[28] L. Azzam and E. Ayanoglu, “Reduced complexity sphere decoding forsquare QAM via a new lattice representation,” in Proc. IEEE GlobalTelecommun. Conf., Nov. 2007, pp. 4242–4246.

[29] J. Lofgren and P. Nilsson, “On MIMO K-best sphere detector architec-ture complexity reductions,” in Proc. Int. Conf. Signal Process. Commun.Syst., Dec. 2008, pp. 1–9.

[30] Physical Channels and Modulation (Release 9). (2010) [Online]. Avail-able: http://www.3gpp.org/ftp/Specs/2010-03/Rel-9/36_series/36211-910.zip

[31] C. Studer, S. Fateh, and D. Seethaler, “ASIC implementation ofsoft-input soft-output MIMO detection using MMSE parallel inter-ference cancellation,” IEEE J. Solid-State Circuits, vol. 46, no. 7,pp. 1754–1765, Jul. 2011.

Liang Liu (S’10–M’11) received the B.S. and Ph.D.degrees from Fudan University, Shanghai, China, in2005 and 2010, respectively.

He was with the Electrical, Computer and Sys-tems Engineering Department, Rensselaer Polytech-nic Institute, Troy, NY, as a Visiting Scholar, from2010 to 2010. He is currently a Post-DoctoralResearcher with the Electrical and Information Tech-nology Department, Lund University, Lund, Sweden.His current research interests include digital circuitsdesign for wireless communication system.

Johan Löfgren (S’06) received the M.S. degreefrom the Chalmers University of Technology,Gothenburg, Sweden, in 2002.

He was with mobile phone development for Eric-sson and Sony Ericsson. In 2006, he joined theElectrical and Information Technology Department,Lund University, Lund, Sweden, as a Ph.D. student.He is currently involved in projects focusing onchannel estimation and symbol detection algorithmsand implementations. His current research inter-ests include the implementation issues in digital

communication.

Peter Nilsson (S’90–M’96–SM’12) received theM.S. degree in electrical engineering, the Licenti-ate of Engineering degree, and the Ph.D. degreein engineering from Lund Institute of Technology,Lund University, Lund, Sweden, in 1992 and 1996,respectively.

He was an Assistant Professor with the Depart-ment of Applied Electronics (now Department ofElectrical and Information Technology), Lund Uni-versity, where he became an Associate Professor andin December 2003, he received the “Docent” degree.

In July 2008, he became a Full Professor. He was the National ProgramManager for Socware Research and Education, a System-on-Chip Programfor research and Master’s educations, from 2000 to 2005. He has authoredor co-authored 80 peer-reviewed journal and conference papers. His currentresearch interests include implementation of digital circuits.

Dr. Nilsson was an Associate Editor for the IEEE TRANSACTIONS ON

CIRCUITS AND SYSTEMS–Part I: Regular Papers, from 2004 to 05, and isa member of the VLSI Systems and Applications Technical Committee in theIEEE Circuits and Systems Society.

Viktor Öwall (M’90) received the M.Sc. and Ph.D.degrees in electrical engineering from Lund Univer-sity, Lund, Sweden, in 1988 and 1994, respectively.

He was with the Electrical Engineering Depart-ment, University of California at Los Angeles, asa Post-Doctoral Fellow, from 1995 to 1996, wherehe worked in multimedia simulations. Since 1996,he has been with the Department of Electrical andInformation Technology, Lund University, where heis currently a full Professor and since 2009, the Headof Department. He is the Director of the VINNOVA

Industrial Excellence Center in System Design on Silicon. His current researchinterests include digital hardware implementation, especially algorithms andarchitectures for wireless communication, image processing and biomedicalapplications. Research projects include combining theoretical research withhardware implementation aspects in the areas of wireless communication,video processing, and digital holography.

Dr. Öwall was an Associate Editor of the IEEE TRANSACTIONS ON CIR-CUITS AND SYSTEMS–Part II: ANALOG AND DIGITAL SIGNAL PROCESSING

from 2000 to 2002 and the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS–Part I: Regular Papers from 2007 to 2009. He was the GuestEditor for the Special issue on ISCAS 2010 of the IEEE TRANSACTIONS

ON BIOMEDICAL CIRCUITS AND SYSTEMS.

Documents

SISO MIMO (1)