Single-Chip, Multiband 3G Femtocell Transceiver ADF4602 .Single-Chip, Multiband 3G Femtocell Transceiver

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Single-Chip, Multiband 3G Femtocell Transceiver

ADF4602

Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20092011 Analog Devices, Inc. All rights reserved.

FEATURES Single-chip, multiband 3G transceiver

3GPP 25.104 release 9 WCDMA/HSPA compatible UMTS band coverage

Local area Class BS in Band I to Band VI and Band VIII to Band X

Direct conversion transmitter and receiver Minimal external components

Integrated, multiband, multimode monitoring No Tx SAW or Rx interstage SAW filters Integrated power management (3.1 V to 3.6 V supply) Integrated synthesizers, including PLL loop filters Integrated PA bias control DACs/GPOs

WCDMA and GSM receive baseband filter options Easy-to-use with minimal calibration

Automatic Rx DC offset control Simple gain, frequency, mode programming

Low supply current 50 mA typical Rx current 50 mA to 100 mA Tx current (varies with output power)

6 mm 6 mm 40-pin LFCSP package

APPLICATIONS 3G home base stations (femtocells)

FUNCTIONAL BLOCK DIAGRAM

DA

C1

DA

C2

GPO

1 TO

4

Tx_PWR_CONTROL

Tx_PWR_CONTROL

TXBBIBTXBBI

TXBBQTXBBQB

VSUP7

VSUP6

RXBBIRXBBIB

VDD

RXLBRF

RXHB2RF

RXHB1RF

TXLBRF

RXBBQRXBBQB

DA

C1

DA

C2

GPO

[4:1

]

Tx_PWR_CONTROL

Tx_PWR_CONTROL

TXHBRF

LOOPFILTER

Rx PLL

Rx_LO_LBSELECTABLE BANDWIDTH

BASEBAND FILTERS

Rx_LO_LB

FRAC NSYNTHE-

SIZERLO GENERATOR

LOOPFILTER

FRAC NSYNTHE-

SIZERLO GENERATOR

DC OFFSETCORRECTION

SERIALINTER-FACE

DC OFFSETCORRECTION

QCHAN-

NEL

ICHAN-

NEL

VSUP8

26MHz 19.2MHz

ADF4602

VIN

TR

EFC

LK

CH

IPC

LK

VSU

P2

LDO2

VSU

P3

LDO3

VSU

P4

LDO4

VSU

P5

LDO5

Tx PLL

0709

2-00

1

VSU

P1

LDO1

REFIN

SEN

SCLK

SDA

TA

Figure 1.

ADF4602

Rev. A | Page 2 of 36

TABLE OF CONTENTS Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications..................................................................................... 4

Timing Characteristics..................................................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Theory of Operation ...................................................................... 19

Transmitter Description ............................................................ 19

DACs ............................................................................................ 20

General Purpose Outputs.......................................................... 20

Receiver Description.................................................................. 20

Power Management ................................................................... 23

Frequency Synthesis................................................................... 24

Serial Port Interface (SPI).............................................................. 25

Operation and Timing............................................................... 25

Registers........................................................................................... 26

Register Map ............................................................................... 26

Register Description .................................................................. 27

Software Initialization Procedure................................................. 31

Initialization Sequence .............................................................. 31

Applications Information .............................................................. 33

Interfacing the ADF4602 to the AD9963................................ 33

Outline Dimensions ....................................................................... 35

Ordering Guide .......................................................................... 35

REVISION HISTORY 2/11Rev. 0 to Rev. A

Changes to Features and Applications........................................... 1 Changes to Table 1............................................................................ 4 Changes to Table 3............................................................................ 9 Changes to Figure 4........................................................................ 10 Changes to Figure 13...................................................................... 13 Changes to Figure 21 and Figure 22............................................. 14 Changes to Figure 26 and Figure 27............................................. 15 Changes to Figure 31 through Figure 33 ..................................... 16 Changes to Figure 44...................................................................... 21 Changes to DC Offset Compensation Section ........................... 23 Changes to Figure 51...................................................................... 26 Changes to Table 13........................................................................ 30 Replaced Applications Information Section ............................... 33 Changes to Figure 53...................................................................... 34

10/09Revision 0: Initial Version

ADF4602

Rev. A | Page 3 of 36

GENERAL DESCRIPTION The ADF4602 is a 3G transceiver integrated circuit (IC) offering unparalleled integration and feature set. The IC is ideally suited to high performance 3G femtocells providing cellular fixed mobile converged (FMC) services. With only a handful of external components, a full multiband transceiver is implemented.

UMTS Band I through Band VI and Band VIII through Band X are supported in a single device.

The receiver is based on a direct conversion architecture. This architecture is the ideal choice for highly integrated wideband CDMA (WCDMA) receivers, reducing the bill of materials by fully integrating all interstage filtering. The front end includes three high performance, single-ended low noise amplifiers (LNAs), allowing the device to support tri-band applications. The single-ended input structure eases interface and reduces the matching components required for small footprint single-ended duplexers. The excellent device linearity achieves good performance with a large range of SAW and ceramic filter duplexers.

The integrated receive baseband filters offer selectable bandwidth, enabling the device to receive both WCDMA and GSM-EDGE radio signals. The selectable bandwidth filter,

coupled with the multiband LNA input structure, allows GSM-EDGE signals to be monitored as part of a UMTS home base station.

The transmitter uses an innovative direct conversion modulator that achieves high modulation accuracy with exceptionally low noise, eliminating the need for external transmit SAW filters.

The fully integrated phase lock loops (PLLs) provide high performance and low power fractional-N frequency synthesis for both receive and transmit sections. Special precautions have been taken to provide the isolation demanded by frequency division duplex (FDD) systems. All VCO and loop filter components are fully integrated.

The ADF4602 also contains on-chip low dropout voltage regulators (LDOs) to deliver regulated supply voltages to the functions on chip, with an input voltage of between 3.1 V and 3.6 V.

The IC is controlled via a standard 3-wire serial interface with advanced internal features allowing simple software programming. Comprehensive power-down modes are included to minimize power consumption in normal use.

ADF4602

Rev. A | Page 4 of 36

SPECIFICATIONS VDD = 3.1 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3.3 V and TA = 25C, 26 MHz reference input level = 0.7 V p-p.

Table 1. Parameter Min Typ Max Unit Test Conditions REFERENCE SECTION

Reference Input