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S7-300 Instruction List CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU This instruction list is part of the documentation package with the order number: 6ES7398-8FA10-8BA0 6ES7198-8FA01-8BA0 06/2008 A5E00105517-10

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  • S7-300 Instruction List

    CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU

    This instruction list is part of thedocumentation package with the order number:

    6ES7398-8FA10-8BA06ES7198-8FA01-8BA0

    06/2008A5E00105517-10

  • We have checked the contents of this manual for agreement with thehardware and software described. Since deviations cannot be pre-cluded entirely, we cannot guarantee full agreement. However, thedata in this manual are reviewed regularly and any necessary cor-rections included in subsequent editions. Suggestions for improve-ment are welcomed.

    Disclaim of LiabilityCopyright � Siemens AG 2008 All rights reserved

    The reproduction, transmission or use of this document or itscontents is not permitted without express written authority.Offenders will be liable for damages. All rights, including rightscreated by patent grant or registration of a utility model or design, arereserved.

    Siemens AGIndustry SectorPostfach 484890437 NÜRNBERG / GERMANY

    © Siemens AG 2008Technical data subject to change.

    A5E00105517-10

  • Contents

    1S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Contents

    Validity Range of the Instructions List 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Address Identifiers and Parameter Ranges 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Abbreviations and Mnemonics 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Registers 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Examples of Addressing 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Examples of how to calculate the pointer 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Execution Times with Indirect Addressing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Calculating the Execution Time Using a CPU 314C-2 DP as an Example 25. . . . . . . . . . . . . . . . . . . . . . . . . .

    List of Instructions 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Bit Logic Instructions 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Bit Logic Instructions with Parenthetical Expressions 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    ORing of AND Operations 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Logic Instructions with Timers and Counters 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Word Logic Instructions with the Contents of Accumulator 1 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Evaluating Conditions Using AND, OR and EXCLUSIVE OR 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Edge-Triggered Instructions 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  • Contents

    2S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Setting/Resetting Bit Addresses 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Instructions Directly Affecting the RLO 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Timer Instructions 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Counter Instructions 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Load Instructions 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Load Instructions for Timers and Counters 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Transfer Instructions 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Load and Transfer Instructions for Address Registers 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Load and Transfer Instructions for the Status Word 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Load Instructions for DB Number and DB Length 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Integer Math (16 Bits) 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Integer Math (32 Bits) 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Floating-Point Math (32 Bits) 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Square Root and Square Instructions (32 Bits) 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Logarithmic Function (32 Bits) 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Trigonometrical Functions (32 Bits) 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Adding Constants 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  • Contents

    3S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Adding Using Address Registers 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Comparison Instructions with Integers (16 Bits) 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Comparison Instructions with Integers (32 Bits) 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Comparison Instructions with Real Numbers (32 Bits) 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Shift Instructions 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Rotate Instructions 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Accumulator Transfer Instructions, Incrementing and Decrementing 91. . . . . . . . . . . . . . . . . . . . . . . .

    Program Display and Null Operation Instructions 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Data Type Conversion Instructions 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Forming the Ones and Twos Complements 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Block Call Instructions 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Block End Instructions 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Exchanging Shared Data Block and Instance Data Block 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Jump Instructions 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Instructions for the Master Control Relay (MCR) 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  • Contents

    4S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Organisation Blocks (OB) 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Function Blocks (FB) 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Functions (FC) 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Data Blocks 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Memory required by the SFBs for the integrated inputs and outputs 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    System Functions (SFC) 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    System Function Blocks (SFB) 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Standard Function Blocks for S7-Communication via CP or Integrated PROFINET Interface 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    Function blocks for open system interconnection over Industrial Ethernet 140. . . . . . . . . . . . . . . . . . . . . . . .

    IEC Functions 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    System Status Sublist 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    PROFIBUS DP Sublists 154. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

    S7 Communication Sublists and PROFINET Sublists 157. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

  • Validity Range of the Instructions List

    5S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Validity Range of the Instructions List

    CPU As of order no.

    As of Version In the following referred to as

    Firmware

    CPU 312 6ES7 312-1AE13-0AB0 V2.6 312

    CPU 312C 6ES7 312-5BE03-0AB0

    CPU 313C 6ES7 313-5BF03-0AB0 V2.6 31x

    CPU 313C-2 PtP 6ES7 313-6BF03-0AB0

    CPU 313C-2 DP 6ES7 313-6CF03-0AB0

    CPU 314 6ES7 314-1AG13-0AB0

    CPU 314C-2 PtP 6ES7 314-6BG03-0AB0

    CPU 314C-2 DP 6ES7 314-6CG03-0AB0

    CPU 315-2 DP 6ES7 315-2AG10-0AB0 V2.6 31x or 315

    CPU 315-2 PN/DP 6ES7 315-2EH13-0AB0 V2.6 315 or 315 PN

    CPU 315T-2 DP 6ES7 315-6TG10-0AB0 V2.4 315 or 315T

    CPU 317-2 DP 6ES7 317-2AJ10-0AB0 V2.6 31x, 317

    CPU 317-2 PN/DP 6ES7 317-2EK13-0AB0 V2.6 317 or 317 PN

    CPU 317T-2 DP 6ES7 317-6TJ10-0AB0 V2.4 317 or 317T

    CPU 319–3 PN/DP 6ES7 318–3EL00–0AB0 V2.7 319 or 319 PN

  • Validity Range of the Instructions List

    6S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    CPU As of order no.

    As of Version In the following referred to as

    Firmware

    BM 147-1 CPU 6ES7 147-1AA10-0AB0 V2.1.0 147

    BM 147-2 CPU 6ES7 147-2AA00-0XB0 V2.1.0 147

    IM 151-7 CPU 6ES7 151-7AA20-0AB0 V2.6 151-71)

    IM 151-8 CPU 6ES7 151-8AB00-0AB0 V2.7 151-81)

    IM 154-8 CPU 6ES7 154-8AB00-0AB0 V2.5 154

    1) If the values are effective for the IM151-7 CPU and the IM151-8 CPU. you will only see “151” in the operation list.

  • Address Identifiers and Parameter Ranges

    7S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Address Identifiers and Parameter Ranges

    Addr IDParameter Ranges

    DescriptionAddr. ID31x 147 151 154 317 319

    Description31x, 147, 151, 154 317 319

    p

    Q 0.0 to 127.7(can be set up 2047.71))

    0.0 to 255.7(can be set up 2047.71))

    0.0 to 255.7(can be set up 4095.7)

    Output (in PIQ)

    QB 0 to 127(can be set up 20471))

    0 to 255(can be set up 20471))

    0 to 255(can be set up 4095)

    Output byte (in PIQ)

    QW 0 to 126(can be set up 20461))

    0 to 254(can be set up 20461))

    0 to 254(can be set up 4094)

    Output word (in PIQ)

    QD 0 to 124(can be set up 20441))

    0 to 252(can be set up 20441))

    0 to 252(can be set up 4092)

    Output double word (in PIQ)

    1) only CPU 315-2 PN, CPU 317-2 DP, CPU 317-2 PN/DP, IM 151-8 CPU and IM 154-8 CPU

  • Address Identifiers and Parameter Ranges

    8S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Parameter RangesParameter Ranges

    Addr. ID 31xC, 312, 314, 147, 151-7

    315, 154 151-8 317 319Description

    DBX 0.0 to 16383.7 0.0 to16383.7

    0.0 to65535.7

    0.0 to65535.7

    0.0 to65535.7

    Data bit in data block

    DB 1 to 511 1 to 1023 1 to 511 1 to 2047 1 to 4095 Data block

    DBB 0 to 16383 0 to 16383 0 to 65535 0 to 65535 0 to 65535 Data byte in DB

    DBW 0 to 16382 0 to 16382 0 to 65534 0 to 65534 0 to 65534 Data word in DB

    DBD 0 to 16380 0 to 16380 0 to 65532 0 to 65532 0 to 65532 Data double word in DB

    DIX 0.0 to 16383.7 0.0 to16383.7

    0.0 to65535.7

    0.0 to65535.7

    0.0 to65535.7

    Data bit in instance DB

    DI 1 to 511 1 to 1023 1 to 511 1 to 2047 1 to 2047 Instance data block

    DIB 0 to 16383 0 to 16383 0 to 65535 0 to 65535 0 to 65535 Data byte in instance DB

    DIW 0 to 16382 0 to 16382 0 to 65535 0 to 65534 0 to 65534 Data word in instance DB

    DID 0 to 16380 0 to 16380 0 to 65532 0 to 65532 0 to 65532 Data double word ininstance DB

  • Address Identifiers and Parameter Ranges

    9S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Addr IDParameter Ranges

    DescriptionAddr. ID31x, 147, 151, 154 317 319

    Description

    I 0.0 to 127.7(can be set up 2047.71))

    0.0 to 255.7(can be set up 2047.71))

    0.0 to 255.7(can be set up 4095.7)

    Inputs (in PII)

    IB 0 to 127 0 to 255(can be set up 20471))

    0 to 255(can be set up 20471))

    0.0 to 255.7(can be set up 4095)

    Input byte (in PII)

    IW 0 to 126 0 to 254(can be set up 20461))

    0 to 254(can be set up 20461))

    0.0 to 255.7(can be set up 4094)

    Input word (in PII)

    ID 0 to 124 0 to 252(can be set up 20441))

    0 to 252(can be set up 20441))

    0.0 to 255.7(can be set up 4092)

    Input double word (in PII)

    Parameter Ranges

    Addr. ID312 313C, 314, 314C, 147,

    151-7, 151-8, 154317 / 319

    Description

    L 0.0 to 255.7 0.0 to 509.7 0.0 to 1023.7 Local data bit

    LB 0 to 255 0 to 509 0 to 1023 Local data byte

    LW 0 to 254 0 to 508 0 to 1022 Local data word

    LD 0 to 252 0 to 506 0 to 1020 Local data double word

    1) only CPU 315-2 PN, CPU 317-2 DP, CPU 317-2 PN/DP, IM 151-8 CPU and IM 154-8 CPU

  • Address Identifiers and Parameter Ranges

    10S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Parameter RangesD i tiAddr. ID 312 313C, 314, 314C,

    147, 151315, 154 317 319 Description

    M 0.0 to 127.7 0.0 to 255.7 0.0 to 2047.7 0.0 to 4095.7 0.0 to 8191.7 Bit memory bit

    MB 0 to 127 0 to 255 0 to 2047 0 to 4095 0 to 8191 Bit memory byte

    MW 0 to 126 0 to 254 0 to 2046 0 to 4094 0 to 8190 Bit memory word

    MD 0 to 124 0 to 252 0 to 2044 0 to 4092 0 to 8188 Bit memory double word

    Addr. ID Except for CPU 315, 151-8,154, 317 and 319315, 151-8, 154 317 319 Description

    PQB 0 to 1023 0 to 2047 0 to 8191 0 to 8191 Peripheral output byte (direct I/O access)

    PQW 0 to 1022 0 to 2046 0 to 8190 0 to 8190 Peripheral output word (direct I/O access)

    PQD 0 to 1020 0 to 2044 0 to 8188 0 to 8188 Peripheral output double word (direct I/O access)

    PIB 0 to 1023 0 to 2047 0 to 8191 0 to 8191 Peripheral input byte(direct I/O access)

    PIW 0 to 1022 0 to 2046 0 to 8190 0 to 8190 Peripheral input word (direct I/O access)

    PID 0 to 1020 0 to 2044 0 to 8188 0 to 8188 Peripheral input double word (direct I/O access)

  • Address Identifiers and Parameter Ranges

    11S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Addr IDParameter Ranges

    DescriptionAddr. ID312 31x, 147, 151, 154 317 319

    Description

    T 0 – 127 0 – 255 0 to 511 0 to 2047 Timer

    Z 0 – 127 0 – 255 0 to 511 0 to 2047 Counter

    Parameter – – – – Instruction adressed via parameter

    B#16#W#16#DW#16#

    – – – – ByteWordDouble wordhexadecimal

    D# – – – – IEC date constant

    L# – – – – 32-bit integer constant

    P# – – – – Pointer constant

    S5T#Time – – – – S5 time constant 1) (16 bits),T#1D_5H-3M_1S_2MS

    T#Time – – – – IEC time constant,T#1D_5H-3M_1S_2MS

    TOD#Time – – – – time constant (16-/32-Bit),T#1D_5H-3M_1S_2MS

    C# – – – – Counter constant (BCD-codiert)

    1) for loading of S5 timers

  • Address Identifiers and Parameter Ranges

    12S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Addr IDParameter Ranges

    DescriptionAddr. ID312 31x, 147, 151, 154 317 319

    Description

    2# – – – – Binary constant

    B (b1,b2) B (b1,b2;b3,b4)

    – – – – Constant, 2 or 4 Byte

  • Abbreviations and Mnemonics

    13S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Abbreviations and Mnemonics

    The following abbreviations and mnemonics are used in the Instruction List:

    Abbre-viations

    Description Example

    k8 8-bit constant 32

    k16 16-bit constant 631

    k32 32-bit constant 1272 5624

    i8 8-bit integer –155

    i16 16-bit integer +6523

    i32 32-bit integer –2 222 222

    m P#x.y (pointer) P#240.3

    n Binary constant 1001 1100

    p Hexadecimal constant EA12

    q Real number (32-bit floating-point number) 12.34567E+5

    LABEL Symbolic jump address (max. 4 characters) DEST

    a Byte address 2

    b Bit address x.1

    c Operand range I, Q, M, L, DBX, DIX

  • Abbreviations and Mnemonics

    14S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Abbre-viations

    Description Example

    f Timer/Counter No. 5

    g Operand range IB, QB, PIB, MB, LB, DBB, DIB

    h Operand range IW, QW, PIW, MW, LW, DBW, DIW

    i Operand range ID, QD, PID, MD, LD, DBD, DID

    r Block No. 10

  • Registers

    15S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Registers

    ACCU1 and ACCU2 (32 Bits)

    The accumulators are registers for processing bytes, words or double words. The operands are loaded into the accumulators, where theyare logically gated. The result of the logic operation (RLO) is in ACCU1.

    Accumulator designations:

    ACCU Bits

    ACCUx (x = 1 to 2) Bits 0 to 31

    ACCUx-L Bits 0 to 15

    ACCUx-H Bits 16 to 31

    ACCUx-LL Bits 0 to 7

    ACCUx-LH Bits 8 to 15

    ACCUx-HL Bits 16 to 23

    ACCUx-HH Bits 24 to 31

  • Registers

    16S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Address Registers AR1 and AR2 (32 Bits)

    The address registers contain the area-internal or area-crossing addresses for instructions using indirect addressing. The address regis-ters are 32 bits long.

    The area-internal and/or area-crossing addresses have the following syntax:

    • Area-internal address

    00000000 00000bbb bbbbbbbb bbbbbxxx

    • Area-crossing address

    10000yyy 00000bbb bbbbbbbb bbbbbxxx

    Legend: b Byte addressx Bit numbery Area identifier (see section “Examples of Addressing”)

  • Registers

    17S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Status Word (16 Bits)

    The status word bits are evaluated or set by the instructions.

    The status word is 16 bits long.

    Bit Assignment Description

    0 FC First check bit , Bit cannot be written and evaluated in the user program since it is not updated at programruntime

    1 RLO Result of (previous) logic operation

    2 STA Status, Bit cannot be written and evaluated in the user program since it is not updated at program runtime

    3 OR Or, Bit cannot be written and evaluated in the user program since it is not updated at program runtime

    4 OS Stored overflow

    5 OV Overflow

    6 CC 0 Condition code

    7 CC 1 Condition code

    8 BR Binary result

    9 ... 15 Unassigned –

  • Examples of Addressing

    18S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Examples of Addressing

    Addressing Examples Description

    Immediate Addressing

    L +27 Load 16-bit integer constant “27” into ACCU1

    L L#–1 Load 32-bit integer constant “–1” into ACCU1

    L 2#1010101010101010 Load binary constant into ACCU1

    L DW#16#A0F0_BCFD Load hexadecimal constant into ACCU1

    L ’END’ Load ASCII character into ACCU1

    L T#500 ms Load time value into ACCU1

    L C#100 Load count value into ACCU1

    L B#(100,12) Load 2-byte constant

    L B#(100,12,50,8) Load 4-byte constant

    L P#10.0 Load area-internal pointer into ACCU1

    L P#E20.6 Load area-crossing pointer into ACCU1

    L –2.5 Load real number into ACCU1

    L D#1995–01–20 Load date

    L TOD#13:20:33.125 Load time of day

  • Examples of Addressing

    19S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Addressing Examples Description

    Direct Addressing

    A I 0.0 ANDing of input bit 0.0

    L IB 1 Load input byte 1 into ACCU1

    L IW 0 Load input word 0 into ACCU1

    L ID 0 Load input double word 0 into ACCU1

    Indirect Addressing of Timers/Counters

    SP T [LW 8] Start timer; the timer number is in local word 8

    CU C [LW 10] Start counter; the counter number is in local data word 10

    Area-Internal Memory-Indirect Addressing

    A I [LD 12]Example: L P#22.2

    T LD 12A I [LD 12]

    AND operation: The address of the input is in local data double word 12 as pointer

    A I [DBD 1] AND operation: The address of the input is in data double word 1 of the DB as pointer

    A Q [DID 12] AND operation: The address of the output is in data double word 12 of the instance DB as pointer

    A Q [MD 12] AND operation: The address of the output is in memory marker double word 12 of the instance DB aspointer

  • Examples of Addressing

    20S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Addressing Examples Description

    Area-Internal Register-Indirect Addressing

    A I [AR1,P#12.2] AND operation: The address of the input is calculated from the “pointer value in AR1+ P#12.2”

    Area-Crossing Register-Indirect Addressing

    For area-crossing register-indirect addressing, bits 24 to 26 of the address must also contain an area identifier. The address is in theaddress register.

    Area Coding Coding Areaidentifier (binary) (hex.)P 1000 0000 80 I/O areaI 1000 0001 81 Input areaQ 1000 0010 82 Output areaM 1000 0011 83 Bit memory areaDB 1000 0100 84 Data areaDI 1000 0101 85 Instance data areaL 1000 0110 86 Local data areaVL 1000 0111 87 Predecessor local data (access to local data of invoking block)

    L B [AR1,P#8.0] Load byte into ACCU1: The address is calculated from the “pointer value in AR1+ P#8.0”

    A [AR1,P#32.3] AND operation: The address of the operand is calculated from the “pointer value in AR1+ P#32.3”

    Addressing Via Parameters

    A Parameter Addressing via parameters

  • Examples of how to calculate the pointer

    21S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Examples of how to calculate the pointer

    • Example for sum of bit addresses �7:

    LAR1 P#8.2A I [AR1,P#10.2]

    Result: Input 18.4 is addressed (by adding the byte and bit addresses)

    • Example for sum of bit addresses�7:

    L MD 0 Random pointer, e.g. P#10.5LAR1A I [AR1,P#10.7]

    Result: Input 21.4 is addressed (by adding the byte and bit addresses with carry)

  • Execution Times with Indirect Addressing

    22S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Execution Times with Indirect Addressing

    You must calculate the execution times when using indirect addressing. This chapter shows you how.

    Two-Part Statement

    A statement with indirectly addressed instructions consists of two parts:

    Part 1: Load the address of the instruction

    Part 2: Execute the instruction

    In other words, you must calculate the execution time of a statement with indirectly addressed instructions from these two parts.

  • Execution Times with Indirect Addressing

    23S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Calculating the Execution Time

    The total execution time is calculated as follows:Time required for loading the address

    + execution time of the instruction= Total execution time of the instruction

    The execution times listed in the chapter entitled “List of Instructions” apply to the execution times of the second part of an instruction, i.e.for the actual execution of an instruction.

    You must then add the time required for loading the address of the instruction to this execution time (see Table on following page).

  • Execution Times with Indirect Addressing

    24S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    The execution time for loading the address of the instruction from the various areas is shown in the following table.

    Address is in Execution Time in �s

    Address is in ...312 31x, 147, 151, 154 317 319

    Bit memory area MWord (for times, counters and block calls)Double word

    0.71.6

    0.40.9

    0.080.21

    0.020.05

    Data block DB/DXWord (for times, counters and block calls)Double word

    1.53.7

    0.82.0

    0.200.25

    0.020.05

    Local data area LWord (for times, counters and block calls)Double word

    0.92.2

    0.51.2

    0.080.20

    0.020.05

    AR1/AR2 (area-internal) 1.0 0.5 0.20 0.021)

    AR1/AR2 (area-crossing) 3.0 1.6 0.31 0.05

    Parameter (word) ... for:• Timers• Counters• Block calls

    2.0 1.0 0.08 0.02

    Parameter (double word) ... forBits, bytes, words and double words

    4.0 2.0 0.26 0.01

    The pages that follow contain examples for calculating the instruction run time for the various indirectly addressed instructions.

    1) For the adress areas I/Q/M/L 0.05 �s

  • Calculating the Execution Time Using a CPU 314C-2 DP as an Example

    25S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Calculating the Execution Time Using a CPU 314C-2 DP as an Example

    You will find a few examples here for calculating the execution times for the various methods of indirect addressing. Execution times arecalculated for the CPU 314C-2 DP.

    Calculating the Execution Times for Area-Internal Memory-Indirect Addressing

    Example: A I [DBD 12]

    Step 1: Load the contents of DBD 12 (time required is listed in the table on page 24)

    Address is in ... Execution Time in �s

    Bit memory area MWordDouble word

    0.40.9

    Data block DB/DIWordDouble word 2.0

    0.8

  • Calculating the Execution Time Using a CPU 314C-2 DP as an Example

    26S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instructions”)

    Typical Execution Time in �s

    Direct Addressing Indirect Addressing

    0.1

    :

    1.6+

    :Time for A I

    Total execution time: 2.0 μs+ 1.6 μs= 3.6 μs

  • Calculating the Execution Time Using a CPU 314C-2 DP as an Example

    27S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Calculating the Execution Time for Area-Internal Register-Indirect Addressing

    Example: A I [AR1, P#34.3]

    Step 1: Load the contents of AR1, and increment it by the offset 34.3 (the time required is listed in the table on page 24)

    Address is in ... Execution Time in �s

    : :

    AR1/AR2 (area-internal) 0.5

    : :

    Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instructions”)

    Typical Execution Time in �s

    Direct Addressing Indirect Addressing

    0.1

    :

    1.6+

    :Time for A I

    Total execution time: 0.5 μs+ 1.6 μs= 2.1 μs

  • Calculating the Execution Time Using a CPU 314C-2 DP as an Example

    28S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Calculating the Execution Time for Area-Crossing Memory-Indirect Addressing

    Example: A [AR1, P#23.1] ... with I 1.0 in AR1

    Step 1: Load the contents of AR1, and increment them by the offset 23.1 (the time required is in the table on page 24)

    Address is in ... Execution Time in �s

    : :

    AR1/AR2 (area-crossing) 1.6

    : :

    Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instructions”)

    Typical Execution Time in �s

    Direct Addressing Indirect Addressing

    0.1

    :

    1.6+

    :Time for A I

    Total execution time: 1.6 μs+ 1.6 μs= 3.2 μs

  • Calculating the Execution Time Using a CPU 314C-2 DP as an Example

    29S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Execution Time for Addressing via Parameters

    Example: A Parameter ... with I 0.5 in the block parameter list

    Step 1: Load input I 0.5 addressed via the parameter (the time required is in the table on page 24).

    Address is in ... Execution Time in �s

    : :

    : :

    Parameter (double word) 2.0

    Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled “List of Instructions”)

    Typical Execution Time in �s

    Direct Addressing Indirect Addressing

    0.1

    :

    1.6+

    :Time for A I

    Total execution time: 2.0 μs+ 1.6 μs= 3.6 μs

  • List of Instructions

    30S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    List of Instructions

    This chapter contains the complete list of S7-300 instructions. The descriptions have been kept as concise as possible. You will find a de-tailed functional description in the various STEP 7 reference manuals.Please note that, in the case of indirect addressing (examples see page 19), you must add the time required for loading the address of theparticular instruction to the execution times listed (see page 24).

  • Bit Logic Instructions

    31S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Bit Logic Instructions

    Examining the signal state of the addressed instruction and gating the result with the RLO according to the appropriate logic function.

    Typical Execution Time in �s

    Instruc- AddressLength

    in

    Direct Addressing

    Indirect Addressing 1)

    Instruc-tion

    AddressIdentifier

    Description inWords2)

    312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    AI/Q a.bM a.bL a.bDBX a.bDIX a.b

    ANDInput/outputBit memoryLocal data bitData bitInstance data bit

    1/21/2222

    0.20.40.72.92.9

    0.10.20.31.41.4

    0.050.050.060.170.17

    0.010.010.020.020.02

    3.0+3.2+3.7+4.5+4.5+

    1.6+1.7+2.0+2.4+2.4+

    0.09+0.09+0.07+0.08+0.07+

    0.01+0.01+0.01+0.01+0.01+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal ( AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: A BR CC 1 CC 0 OV OS OR STA RLO FCInstruction depends on: – – – – – Yes – Yes Yes

    Instruction affects: – – – – – Yes Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Bit Logic Instructions

    32S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- AddressLength

    in

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier

    Description inWords2)

    312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    ANI/Q a.bM a.bL a.bDBX a.bDIX a.b

    AND NOTInput/outputBit memoryLocal data bitData bitInstance data bit

    1/21/2222

    0.30.40.83.03.0

    0.20.20.41.51.5

    0.050.050.060.170.17

    0.010.010.020.020.02

    3.2+3.4+3.9+4.7+4.7+

    1.7+1.8+2.1+2.5+2.5+

    0.09+0.09+0.08+0.09+0.07+

    0.01+0.01+0.01+0.01+0.01+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: AN BR CC 1 CC 0 OV OS OR STA RLO FCInstruction depends on: – – – – – Yes – Yes Yes

    Instruction affects: – – – – – Yes Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Bit Logic Instructions

    33S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- AddressLength

    in

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    OI/Q a.bM a.bL a.bDBX a.bDIX a.b

    ORInput/outputBit memoryLocal data bitData bitInstance data bit

    1/21/2222

    0.20.30.72.92.9

    0.10.20.31.41.4

    0.050.050.060.200.20

    0.010.010.020.020.02

    3.0+3.2+3.7+4.6+4.6+

    1.6+1.7+2.0+2.4+2.4+

    0.11+0.11+0.10+0.11+0.09+

    0.01+0.01+0.01+0.01+0.01+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: O BR CC 1 CC 0 OV OS OR STA RLO2 FC

    Instruction depends on: – – – – – – – Yes Yes

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Bit Logic Instructions

    34S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- AddressLength

    in

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    ONI/Q a.bM a.bL a.bDBX a.bDIX a.b

    OR NOTInput/outputBit memoryLocal data bitData bitInstance data bit

    1/21/2222

    0.30.40.83.03.0

    0.20.20.41.51.5

    0.050.050.060.200.20

    0.010.010.020.020.02

    3.2+3.5+3.9+4.7+4.7+

    1.7+1.8+2.1+2.5+2.5+

    0.11+0.11+0.10+0.11+0.09+

    0.01+0.01+0.01+0.01+0.01+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: ON BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes Yes

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Bit Logic Instructions

    35S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- AddressDescription

    Lengthin

    DirectAddressing

    IndirectAddressing 1)

    Instruction

    AddressIdentifier Description

    inWords

    2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    XI/Q a.bM a.bL a.bDBX a.bDIX a.b

    EXCLUSIVE ORInput/outputBit memoryLocal data bitData bitInstance data bit

    1/21/2222

    0.20.30.72.92.9

    0.10.20.31.41.4

    0.050.050.060.200.20

    0.010.010.020.020.02

    2.9+3.2+3.7+4.5+4.5+

    1.6+1.7+2.0+2.4+2.4+

    0.11+0.11+0.10+0.11+0.09+

    0.01+0.01+0.01+0.01+0.01+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: X BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes Yes

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Bit Logic Instructions

    36S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- AddressLength

    in

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    XNI/Q a.bM a.bL a.bDBX a.bDIX a.b

    EXCLUSIVE OR NOTInput/outputBit memoryLocal data bitData bitInstance data bit

    1/21/2222

    0.30.40.83.03.0

    0.20.20.41.51.5

    0.050.050.060.200.20

    0.010.010.020.020.02

    3.2+3.5+3.9+4.7+4.7+

    1.7+1.8+2.1+2.5+2.5+

    0.11+0.11+0.10+0.11+0.10+

    0.01+0.01+0.01+0.01+0.01+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: XN BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes Yes

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Bit Logic Instructions with Parenthetical Expressions

    37S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Bit Logic Instructions with Parenthetical Expressions

    Saving the BR, RLO and OR bits and a function identifier (A, AN, ...) to the nesting stack. Seven nesting levels are possible per block. Thelisted parenthesese also apply to the “right parenthesis”-Instructions.

    AddressTypical Execution Time in �s1) 1

    InstructionAddressIdentifier Description Length in

    Words312

    31x, 147,151, 154

    317 319

    A( AND left parenthesis 1 3.2 1.6 0.18 0.02

    AN( AND NOT left parenthesis 1 3.3 1.6 0.18 0.02

    O( OR left parenthesis 1 3.0 1.5 0.11 0.02

    ON( OR NOT left parenthesis 1 3.0 1.5 0.11 0.02

    X( EXCLUSIVE ORleft parenthesis

    1 3.0 1.5 0.11 0.02

    XN( EXCLUSIVE OR NOTleft parenthesis

    1 3.0 1.5 0.11 0.02

    Status word for: A(, AN(, O(, ON(, X(, XN( BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: Yes – – – – Yes – Yes Yes

    Instruction affects: – – – – – 0 1 – 0

    1) also applies to “right parenthesis”- Instructions

  • Bit Logic Instructions with Parenthetical Expressions

    38S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    AddressTypical Execution Time in �s

    InstructionAddressIdentifier Description Length in

    Words312

    31x, 147,151, 154

    317 319

    ) Right parenthesis, pop-ping an entry off the nest-ing stack, gating the RLOwith the current RLO inthe processor

    1 1.0 1.0 0.1 0.02

    Status word for: ) BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: Yes – – – – Yes 1 Yes 1

  • ORing of AND Operations

    39S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    ORing of AND Operations

    The ORing of AND operations is implemented according to the rule: AND before OR.

    AddressTypical Execution Time in �s

    InstructionAddressIdentifier Description Length in

    Words312

    31x, 147,151, 154

    317 319

    O ORing of ANDoperations accordingto the rule:AND before OR

    1 0.2 0.1 0.04 0.01

    Status word for: O BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – Yes – Yes Yes

    Instruction affects: – – – – – Yes 1 – Yes

  • Logic Instructions with Timers and Counters

    40S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Logic Instructions with Timers and Counters

    Examining the signal state of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function.

    Typical Execution Time in �s

    AddressLength

    DirectAddressing

    IndirectAddressing 1)

    InstructionAddressIdentifier Description

    Lengthin

    Words 2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    AT fC f

    ANDTimerCounter

    1/2+1/2+

    0.60.3

    0.30.2

    0.360.10

    0.130.09

    2.1+2.0+

    1.1+1.1+

    0.42+0.13+

    0.13+0.09+

    Timer para.Counter p.

    Timer/counter(adressed viaparameter)

    2 ––

    ––

    ––

    ––

    ++

    ++

    ++

    ++

    Status word for: A CC 1 BR CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – Yes – Yes Yes

    Instruction affects: – – – – – Yes Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Logic Instructions with Timers and Counters

    41S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    InstructionAddress

    DescriptionLength

    in

    DirectAddressing

    IndirectAddressing 1)

    InstructionAddressIdentifier

    Description inWords 2)

    312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    ANT fC f

    AND NOTTimerCounter

    1/21/2

    0.80.5

    0.40.3

    0.360.10

    0.130.09

    2.3+2.2+

    1.2+1.2+

    0.42+0.13+

    0.13+0.09+

    Timer para.Counter p.

    Timer/counter (addressed viaparameter)

    2 ––

    ––

    ––

    ––

    ++

    ++

    ++

    ++

    Status word for: AN BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – Yes – Yes Yes

    Instruction affects: – – – – – Yes Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Logic Instructions with Timers and Counters

    42S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    AddressLength

    DirectAddressing

    IndirectAddressing 1)

    InstructionAddressIdentifier Description

    Lengthin

    Words 2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    O T fC f

    OR timerOR counter

    1/21/2

    0.60.3

    0.30.2

    0.360.10

    0.130.09

    2.1+2.0+

    1.1+1.0+

    0.42+0.13+

    0.13+0.09+

    Timerpara.Counter p.

    OR timer/counter (adressed via pa-rameter)

    2 ––

    ––

    ––

    ––

    ++

    ++

    ++

    ++

    ON T fC f

    OR NOT timerOR NOT counter

    1/21/2

    0.80.5

    0.40.3

    0.360.10

    0.130.09

    2.3+2.2+

    1.2+1.1+

    0.42+0.13+

    0.13+0.09+

    Timerpara.Counter p.

    OR NOT timer/counter(addressed viaparameter)

    2 ––

    ––

    ––

    ––

    ++

    ++

    ++

    ++

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Logic Instructions with Timers and Counters

    43S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Instruction

    Typical Execution Time in �s

    Lengthin

    Words 2)Description

    AddressIdentifierInstruction

    IndirectAddressing 1)

    DirectAddressingLength

    inWords 2)

    DescriptionAddressIdentifierInstruction

    319317

    31x,147,151,154

    312319317

    31x,147,151,154

    312

    Lengthin

    Words 2)Description

    AddressIdentifier

    XT fC f

    EXCLUSIVE ORtimercounter

    1/21/2

    0.60.4

    0.30.2

    0.360.10

    0.130.09

    2.1+2.0+

    1.1+1.1+

    0.42+0.13+

    0.13+0.09+

    Timerpara.Counter p.

    EXCLUSIVE ORtimer/counter (addressed viaparameter)

    2 ––

    ––

    ––

    ––

    ++

    ++

    ++

    ++

    Status word for: O, ON, X BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes Yes

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Logic Instructions with Timers and Counters

    44S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    AddressLength

    DirectAddressing

    IndirectAddressing 1)

    InstructionAddressIdentifier Description

    Lengthin

    Words 2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    XNT fC f

    EXCLUSIVE ORtimercounter

    1/21/2

    0.80.5

    0.40.3

    0.360.10

    0.130.09

    2.3+2.2+

    1.2+1.2+

    0.42+0.13+

    0.13+0.09+

    Timerpara.Counter p.

    EXCLUSIVE ORNOT timer/coun-ter (addressedvia parameter)

    2 ––

    ––

    ––

    ––

    ++

    ++

    ++

    ++

    Status word for: XN BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes Yes

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)2) With direct instruction addressing/ with indirect instruction adressing

  • Word Logic Instructions with the Contents of Accumulator 1

    45S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Word Logic Instructions with the Contents of Accumulator 1

    Gating the contents of ACCU1 and/or ACCU1-L with a word or double word according to the appropriate function. The word or double wordis either a constant in the instruction or in ACCU2. The result is in ACCU1 and/or ACCU1-L.

    AddressTypical Execution Time in �s

    InstructionAddressIdentifier Description Length in

    Words312

    31x, 147,151, 154

    317 319

    AW AND ACCU2-L 1 0.6 0.3 0.21 0.02

    AW k16 AND 16-bit constant 2 0.6 0.3 0.19 0.02

    OW OR ACCU2-L 1 0.6 0.3 0.18 0.02

    OW k16 OR 16-bit constant 2 0.6 0.3 0.18 0.02

    XOW EXCLUSIVE OR ACCU2-L 1 0.6 0.3 0.21 0.02

    XOW k16 EXCLUSIVE OR 16-bit constant 2 0.6 0.3 0.21 0.02

    AD AND ACCU2 1 1.9 1.0 0.13 0.02

    AD k32 AND 32-bit constant 3 2.1 1.0 0.18 0.02

    Status word for: AW, OW, XOW, AD BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – – –

    Instruction affects: – Yes 0 0 – – – – –

  • Word Logic Instructions with the Contents of Accumulator 1

    46S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    AddressTypical Execution Time in �s

    InstructionAddressIdentifier Description Length in

    Words312

    31x, 147,151, 154

    317 319

    OD OR ACCU2 1 1.9 1.0 0.13 0.02

    OD k32 OR 32-bit constant 3 2.1 1.0 0.18 0.02

    XOD EXCLUSIVE OR ACCU2 1 1.9 1.0 0.13 0.02

    XOD k32 EXCLUSIVE OR 32-bit constant 3 2.1 1.0 0.18 0.02

    Status word for: OD, XOD BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – – –

    Instruction affects: – Yes 0 0 – – – – –

  • Evaluating Conditions Using AND, OR and EXCLUSIVE OR

    47S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Evaluating Conditions Using AND, OR and EXCLUSIVE OR

    Examining the specified conditions for their signal status, and gating the result with the RLO according to the appropriate function.

    In-Ad-

    dressTypical Execution Time in �sIn-

    struc-tion

    dressIdenti-

    fier

    DescriptionLength

    in Words312

    31x, 147,151, 154

    317 319

    A/O/ X

    ==0 AND, OR, EXCLUSIVE ORResult=0 (CC 1=0)and (CC 0=0)

    1 0.3 0.2 0.03 0.03

    X>0 Result>0 (CC 1=1) and (CC 0=0) 1 0.5 0.3 0.05 0.03

  • Evaluating Conditions Using AND, OR and EXCLUSIVE OR

    48S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    In-Address

    Typical Execution Time in �sIn-struc-tion

    AddressIdentifier Description Length

    in Words312

    31x, 147,151, 154

    317 319

    AN/ ON/XN

    ==0 AND NOT, OR NOT, EXCLUSIVE OR NOTResult=0 (CC 1=0) and (CC 0=0)

    1 0.3 0.2 0.03 0.03

    XN>0 Result>0 (CC 1=1) and (CC 0=0) 1 0.5 0.3 0.05 0.03

  • Edge-Triggered Instructions

    49S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Edge-Triggered Instructions

    Detection of an edge change. The current signal state of the RLO is compared with the signal state of the instruction or “edge bit memory”.FP detects a change in the RLO from “0” to “1”; FN detects a change in the RLO from “1” to “0”.

    Typical Execution Time in �s

    Instruc- Address Length

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier Description

    Lengthin Words

    312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    FP I/Q a.bM a.bL a.b

    Detecting the positiveedge in the RLO.The bit addressed in

    222

    0.51.01.2

    0.30.50.6

    0.130.290.30

    0.040.040.04

    3.3+3.6+4.0+

    1.8+1.9+2.1+

    0.10+0.10+0.08+

    0.02+0.02+0.02+L a.b

    DBX a.bDIX a.b

    The bit addressed inthe instruction is theauxiliary edge bitmemory.

    222

    1.23.63.6

    0.61.81.8

    0.300.200.20

    0.040.040.04

    4.0+5.2+5.2+

    2.1+2.7+2.7+

    0.08+0.11+0.09+

    0.02+0.02+0.02+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: FP BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)

  • Edge-Triggered Instructions

    50S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- Address Length

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier Description

    Lengthin Words

    312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    FN I/Q a.bM a.bL a.bDBX a.bDIX a.b

    Detecting the negtiveedge in the RLO. Thebit addressed in theintruction is the auxi-liary edge bit memory.

    22222

    0.71.11.33.73.7

    0.30.50.71.91.9

    0.130.130.140.200.20

    0.040.040.040.040.04

    3.5+3.8+4.2+5.2+5.2+

    1.9+2.0+2.2+2.8+2.8+

    0.10+0.10+0.08+0.11+0.09+

    0.02+0.02+0.02+0.02+0.02+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: FN BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 Yes Yes 1

    1) Plus time required for loading the address of the instruction (see page 24)

  • Setting/Resetting Bit Addresses

    51S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Setting/Resetting Bit AddressesAssigning the value “1” or “0” or the RLO o the addressed instruction. The instructions can be MCR–dependent.

    L thTypical Execution Time in �s

    In-struc-

    AddressIdentifier

    Description

    Lengthin

    Words

    DirectAddressing

    IndirectAddressing 1)struc

    tionIdentifier

    pWords

    2) 31231x,147151,154

    317 319 31231x,147151,154

    317 319

    S I/Q a.b

    M a.b

    L a.b

    DBX a.b

    DIX a.b

    Set input/output to “1”(MCR-dependent)Set bit memory to “1”(MCR-dependent)Set local data bit to “1”(MCR-dependent)Set data bit to “1”(MCR-dependent)Set instance data bit to “1”(MCR-dependent)

    1/2

    1/2

    2

    2

    2

    0.20.30.41.80.92.03.43.53.43.5

    0.10.20.20.90.41.01.71.71.71.7

    0.110.130.110.130.120.140.190.190.190.19

    0.020.060.020.060.020.060.020.060.020.06

    3.1+3.3+3.4+3.7+3.8+3.9+4.8+5.0+4.8+5.0+

    1.7+1.8+1.8+2.0+2.0+2.1+2.6+2.7+2.6+2.7+

    0.08+0.10+0.11+0.12+0.07+0.09+0.10+0.11+0.09+0.11+

    0.02+0.06+0.02+0.06+0.02+0.06+0.02+0.06+0.02+0.06+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: S BR CC 1 CC 0 OV OS OR STA RLO FCInstruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 Yes – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Setting/Resetting Bit Addresses

    52S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    AddressLength

    DirectAddressing

    IndirectAddressing 1)

    InstructionAddressIdentifier Description

    Lengthin

    Word 2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    R I/Q a.b

    M a.b

    L a.b

    DBX a.b

    DIX a.b

    Reset input/output to “0”(MCR-dependent)Set bit memory to “0”(MCR-dependent)Set local data bit to“ 0”(MCR-dependent)Set data bit to “0”(MCR-dependent)Set instance data bit to “0”(MCR-dependent)

    1/2

    1/2

    2

    2

    2

    0.30.30.51.80.92.03.43.63.43.6

    0.10.20.30.90.41.01.71.81.71.8

    0.120.130.120.130.120.140.230.250.230.25

    0.020.060.020.060.020.060.020.060.020.06

    3.2+3.5+3.5+3.6+3.9+4.0+5.0+5.1+5.0+5.1+

    1.7+1.8+1.8+1.9+2.1+2.1+2.6+2.7+2.6+2.7+

    0.08+0.11+0.11+0.13+0.10+0.12+0.14+0.16+0.13+0.16+

    0.02+0.06+0.02+0.06+0.02+0.06+0.02+0.06+0.02+0.06+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: R BR CC 1 CC 0 OV OS OR STA RLO FCInstruction depends on: – – – – – – – Yes –Instruction affects: – – – – – 0 Yes – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Setting/Resetting Bit Addresses

    53S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    In-Address

    Lengthin

    DirectAddressing

    IndirectAddressing 1)In

    struc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    = I/Q a.b

    M a.b

    L a.b

    DBX a.b

    DIX a.b

    Assign RLO to input/output(MCR-dependent)Assign RLO to bit memory(MCR-dependent)Assign RLO to local data bit(MCR-dependent)Assign RLO to data bit(MCR-dependent)Assign RLO to instance data bit(MCR-dependent)

    1/2

    1/2

    2

    2

    2

    0.20.30.61.80.82.13.43.63.43.6

    0.10.20.30.90.41.01.71.81.71.8

    0.080.100.080.100.090.110.230.230.230.23

    0.020.060.020.060.020.060.020.060.020.06

    3.2+3.4+3.5+3.7+3.9+4.1+5.0+5.1+5.0+5.1+

    1.7+1.8+1.8+2.0+2.0+2.2+2.6+2.7+2.6+2.7+

    0.10+0.11+0.13+0.13+0.12+0.12+0.16+0.16+0.15+0.16+

    0.02+0.06+0.02+0.06+0.02+0.06+0.02+0.06+0.02+0.06+

    c[AR1,m]c[AR2,m][AR1,m][AR2,m]Parameter

    Register-ind., area-internal(AR1)Register-ind., area-internal(AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    Status word for: = BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 Yes – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Instructions Directly Affecting the RLO

    54S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Instructions Directly Affecting the RLO

    The following instructions have a direct effect on the RLO.

    AddressLength in Typical Execution Time in �s

    InstructionAddressIdentifier Description

    gWords

    31231x, 147,151, 154

    317 319

    CLR Set RLO to ”0” 2 0.2 0.1 0.03 0.01

    Status word for: CLR BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – – –

    Instruction affects: – – – – – 0 0 0 0

    SET Set RLO to ”1” 2 0.2 0.1 0.03 0.01

    Status word for: SET BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – – –

    Instruction affects: – – – – – 0 1 1 0

    NOT Negate RLO 2 0.2 0.1 0.03 0.01

    Status word for: NOT BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – Yes – Yes –

    Instruction affects: – – – – – – 1 Yes –

  • Instructions Directly Affecting the RLO

    55S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    AddressLength in Typical Execution Time in �s

    InstructionAddressIdentifier Description

    gWords

    31231x, 147,151, 154

    317 319

    SAVE Retain the RLO inthe Bit BR

    1 0.2 0.1 0.03 0.01

    Status word for: SAVE BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: Yes – – – – – – – –

  • Timer Instructions

    56S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Timer InstructionsStarting or resetting a timer (addressed directly or via a parameter). The time value must be in ACCU1-L.

    Typical Execution Time in �s

    InstructionAddressIdentifier

    DescriptionLength

    inDirect

    AddressingIndirect

    Addressing 1)InstructionIdentifier

    Description inWords2)

    31231x, 147,151, 154

    317 319 312 31x, 147,151, 154

    317 319

    SP T f Start timer as pulseon edge change from

    4/6 4.4 2.3 0.91 0.20 5.4+ 2.9+ 0.84+ 0.20+

    Timer para.on edge change from“0” to “1” 2 – – – – + + + +

    SE T f Start timer as exdedpulse on edge change

    4/6 2.2 1.1 0.91 0.18 2.2+ 1.2+ 0.84+ 0.18+

    Timer para.pulse on edge changefrom “0” to “1” 2 – – – – + + + +

    SD T f Start timer as ONdelay on edge change

    4/6 4.6 2.4 0.91 0.23 5.5+ 3.0+ 0.85+ 0.23+

    Timer para.delay on edge changefrom “0” to “1” 2 – – – – + + + +

    SS T f Start timer as retiveON delay on edge

    4/6 4.7 2.4 0.91 0.20 5.7+ 3.0+ 0.86+ 0.20+

    Timer para.ON delay on edgechange from “0” to “1” 2 – – – – + + + +

    Status word for: SP, SE, SD, SS BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 – – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Timer Instructions

    57S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Length Direct Addressing Indirect Addressing 1)

    InstructionAddressIdentifier

    Description

    Lengthin

    Words2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    SA T f Start timer as off-delaytimer when the edge

    4/6 4.9 2.5 0.97 0.24 5.9+ 3.2+ 0.88+ 0.24+

    Timer para.timer when the edgechanges from “1” to “0”. 2 – – – – + + + +

    FR T f Enable timer for restartingon edge change from “0”

    4/6 2.3 1.2 0.79 0.10 2.8+ 1.5+ 0.70 0.10+

    Timer para.

    on edge change from 0to “1” (reset edge bitmemory for starting timer)

    2 – – – – + + + +

    R T f Reset timer 4/6 2.3 1.1 0.44 0.12 2.8+ 1.5+ 0.41 0.12+

    Timer para. 2 – – – – + + + +

    Status word for: SA, FR, R BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 – – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing

  • Counter Instructions

    58S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Counter InstructionsThe count value is in ACCU1-L or in the address transferred as parameter.

    Typical Execution Time in �s

    Length Direct Addressing Indirect Addressing 1)

    InstructionAddressIdentifier

    Description

    Lengthin

    Words2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    S C f Presetting of counteron edge change from

    4/6 3.3 1.7 0.33 0.14 4.5+ 2.4+ 0.29+ 0.14+

    Counter p.on edge change from“0” to “1” 2 – – – – + + + +

    R C f Reset counter to “0” 4/6 1.3 0.6 0.17 0.10 2.1+ 1.1+ 0.13+ 0.10+

    Counter p. 2 – – – – + + + +

    CU C f Increment counter by1 on edge change

    4/6 1.9 1.0 0.20 0.10 2.9+ 1.6+ 0.17+ 0.10+

    Counter p.1 on edge changefrom “0” to “1” 2 – – – – + + + +

    CD C f Decrement counterby 1 on edge change

    4/6 1.9 0.9 0.20 0.10 2.9+ 1.5+ 0.17+ 0.10+

    Counter p.by 1 on edge changefrom “0” to “1” 2 – – – – + + + +

    Status word for: S, R, CU, CD BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 – – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Counter Instructions

    59S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    AddressLength

    in

    DirectAddressing

    IndirectAddressing 1)

    InstructionAddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    FR C f Enable counter onedge change from “0”to “1” (reset edge bit

    2 1.6 0.8 0.20 0.10 2.6+ 1.4 0.17+ 0.10+

    Counter p.to “1” (reset edge bitmemory for up anddown counting)

    2 – – – – + + – –

    Status word for: FR BR CC 1 CC 0 OV OS OR STA RLO FC

    Instruction depends on: – – – – – – – Yes –

    Instruction affects: – – – – – 0 – – 0

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Load Instructions

    60S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Load InstructionsLoading address identifiers into ACCU1. The conts of ACCU1 and ACCU2 are saved first. The status word is not affected.

    Typical Execution Time in �s

    In- LengthDirect Addressing Indirect Addressing 1)

    In-struc-tion

    AddressIdentifier

    DescriptionLength

    inWords

    2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    LIB aQB aPIB aPIB aPIB aPIB aPIB aPIB aPIB aPIB aPIB a

    Load ...Input byteOutput bytePeripheral input byte for 31x... for 147... for 151-7 (Bus 1m)... for 151-8 (Bus 1m)... for 154Digital Onboard I/O 3)Analog Onboard I/O 4)

    1/21/21/21/21/21/21/21/21/21/21/2

    0.40.470.2

    ––––––

    51.5–

    0.20.243.350.5104.8136.468.388.868.348.3162.1

    0.050.0515.01

    ––––––––

    0.010.0113.1

    ––––––––

    2.7+2.7+

    108.4+––––––

    65.2+–

    1.4+1.4+44.6+51.8+105.0+138.2+69.6+90.5+69.6+55.6+169.4+

    0.14+0.14+15.08+

    ––––––––

    0.01+0.01+13.1+

    ––––––––

    MB aLB aDBB aDIB a

    Bit memory byteLocal data byteData byteInstance data byte into ACCU1

    1/2222

    0.50.93.03.0

    0.20.51.51.5

    0.050.050.170.17

    0.010.020.020.02

    2.6+3.3+4.7+4.7+

    1.4+1.7+2.5+2.5+

    0.14+0.13+0.12+0.12+

    0.01+0.01+0.01+0.01+

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing 3) Access to digital onboard I/O 4) Access to analog onboard I/O

  • Load Instructions

    61S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    In- LengthDirect Addressing Indirect Addressing 1)

    In-struc-tion

    AddressIdentifier

    DescriptionLength

    inWords

    2)312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    L g[AR1,m]g[AR2,m]B[AR1,m]B[AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing (AR1)Area-crossing (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Load Instructions

    62S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    In- AddressLength Direct Addressing Indirect Addressing 1)

    In-struc-tion

    AddressIdentifier Description

    gin

    Words2)

    31231x,147,

    151, 154317 319 312

    31x,147,

    151, 154317 319

    LIW aQW aPIW aPIW aPIW aPIW aPIW aPIW aPIW aPIW aPIW a

    Load ...Input wordOutput wordPeripheral input word for 31x... for 147... for 151-7 (Bus 1m)... for 151-8 (Bus 1m)... for 154Digital Onboard I/O 3)

    Analog Onboard I/O 4)

    1/21/2222222222

    0.60.676.7

    ––––––

    61.4–

    0.30.347.456.2105.8141.772.997.772.957.6170.5

    0.100.1020.71

    ––––––––

    0.010.0116.7

    ––––––––

    2.9+2.9+

    131.1+––––––

    77.6+–

    1.6+1.6+48.9+57.8+108.4+142.5+74.2+99.4+74.2+66.3+179.2+

    0.15+0.15+20.75+

    ––––––––

    0.01+0.01+16.7+

    ––––––––

    MW aLW a

    Bit memory wordLocal data word

    1/22

    0.81.1

    0.40.6

    0.100.10

    0.010.02

    3.2+3.8+

    1.7+2.0+

    0.15+0.16+

    0.01+0.01+LW a

    DBW aDIW a

    Local data wordData wordInstance data word...into ACCU1

    21/21/2

    1.13.53.5

    0.61.81.8

    0.100.240.24

    0.020.020.02

    3.8+5.6+5.6+

    2.0+3.0+3.0+

    0.16+0.16+0.16+

    0.01+0.01+0.01+

    h[AR1,m]h[AR2,m]W[AR1,m]W[AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing 3) Access to digital onboard I/O 4) Access to analog onboard I/O

  • Load Instructions

    63S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    In-Address

    Lengthin

    DirectAddressing

    IndirectAddressing 1)In

    struc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312x

    31x,147,151,154

    317 319

    LID aQD aPID aPID aPID aPID aPID aPID aPID aPID a

    Load ...Input double wordOutput double wordPeripheral input double word... for 147... for 151-7 (Bus 1m)... for 151-8 (Bus 1m)... for 154Analog Onboard I/O 3)

    1/21/222222222

    0.80.895.9

    –––––––

    0.40.460.268.7120.2161.081.6109.381.6303.0

    0.200.2027.58

    –––––––

    0.020.0224.9

    –––––––

    3.1+3.1+

    150.6+–––––––

    1.6+1.6+61.9+70.8+21.8+163.6+82.9+111.1+82.9+323.0+

    0.17+0.17+27.65+

    –––––––

    0.01+0.01+24.9+

    –––––––

    MD aLD aDBD a

    Bit memory double wordLocal data double wordData double word

    1/222

    1.01.54 7

    0.50.72 3

    0.190.190 33

    0.020.020 02

    3.8+4.4+6 9+

    2.0+2.3+3 7+

    0.17+0.19+0 19+

    0.01+0.01+0 01+DBD a

    DID aData double wordInstance data double word... into ACCU1

    22

    4.74.7

    2.32.3

    0.330.33

    0.020.02

    6.9+6.9+

    3.7+3.7+

    0.19+0.19+

    0.01+0.01+

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing 3) Access to analog onboard I/O

  • Load Instructions

    64S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    In-Address

    Lengthin

    DirectAddressing

    IndirectAddressing 1)In

    struc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312x

    31x,147,151,154

    317 319

    L i[AR1.m]i[AR2,m]D[AR1.m]D[AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing via (AR1)Area-crossing via (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Load Instructions

    65S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    Instruc- AddressLength

    DirectAddressing

    IndirectAddressing 1)

    Instruc-tion

    AddressIdentifier Description

    Lengthin

    Words312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    Lk8k16k32

    Load ...8-bit constant into ACCU1-LL16-bit constant into ACCU1-L32-bit constant into ACCU1

    123

    0.40.40.5

    0.20.20.3

    0.050.050.05

    0.010.010.01

    –––

    –––

    –––

    –––

    Parameter Load constant into ACCU1 (ad- 2 – – – – + + + +Parameter Load constant into ACCU1 (addressed via parameter)

    2 + + + +

    L 2#n Load 16-bit binary constant intoACCU1-L

    2 0.4 0.2 0.05 0.01 – – – –

    Load 32-bit binary constant intoACCU1

    3 0.5 0.3 0.05 0.01 – – – –

    L B#8#p Load 8-bit hexadecimal constantinto ACCU1-L

    1 0.4 0.2 0.05 0.01 – – – –

    W#16#p Load 16-bit hexadecimal constantinto ACCU1-L

    2 0.4 0.2 0.05 0.01 – – – –

    DW#16#p Load 32-bit hexadecimal constantinto ACCU1-L

    3 0.5 0.3 0.05 0.01 – – – –

    1) Plus time required for loading the address of the instruction (see page 24)

  • Load Instructions

    66S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �sAdd

    Typical Execution Time in �sInstruc-

    tionAddressIdentifier

    Description Lengthin Words 312

    31x, 147,151, 154

    317 319

    L ’x’ Load 1 characters 0.4 0.2 0.05 0.01

    L ’xx’ Load 2 characters 2 0.4 0.2 0.05 0.01

    L ’xxx’ Load 3 characters 0.5 0.3 0.08 0.01

    L ’xxxx’ Load 4 characters 3 0.5 0.3 0.08 0.01

    L D# date Load IEC date (BCD) 3 0.5 0.3 0.08 0.01

    L S5T# time value Load S5 time constant (16 bits) 2 0.5 0.3 0.05 0.01

    L TOD# time value Load 32-bit time constantIEC – daytime

    3 0.5 0.3 0.08 0.01

    L T# time value Load 16-bit timer constant 2 0.4 0.2 0.05 0.01

    Load 32-bit timer constant 3 0.5 0.3 0.08 0.01

    L C# count value Load 16-bit counter constant 2 0.4 0.2 0.05 0.01

    L P# bit pointer Load bit pointer 3 0.5 0.3 0.08 0.01

    L L# integer Load 32 bit integer constant 3 0.5 0.3 0.08 0.01

    L Real number Load real number 3 0.5 0.3 0.08 0.01

  • Load Instructions for Timers and Counters

    67S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Load Instructions for Timers and Counters

    Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU2. The bits of the status word are notaffected.

    L tTypical Execution Time in �s

    Instruc-tion

    Operand Description

    Length in

    Words

    DirectAddressing

    IndirectAddressing 1)

    tionp p

    Words2) 312

    31x, 147,151, 154

    317 319 31231x, 147,151, 154

    317 319

    L T f Load time value 1/2 1.7 0.8 0.43 0.19 2.0+ 1.1+ 0.39+ 0.19+

    Timer para. Load time value(adressed via parameter)

    2 – – – – + + + +

    L C f Load count value 1/2 1.4 0.7 0.14 0.08 2.3+ 1.2+ 0.11+ 0.08+

    Counter para. Load count value(adressed via parameter)

    2 – – – – + + + +

    LD T f Load time value in BCD 1/2 4.2 2.2 0.87 0.30 5.0+ 2.5+ 0.84+ 0.30+

    Timer para. Load time value in BCD(adressed via parameter)

    2 – – – – + + + +

    LD C f Load count value in BCD 1/2 4.4 2.2 0.56 0.19 5.4+ 2.9+ 0.53+ 0.19+

    Counter para. Load count value(adressed via parameter)

    2 – – – – + + + +

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Transfer Instructions

    68S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Transfer Instructions

    Transferring the contents of ACCU1 to the addressed Inrand. The status word is not affected. Remember that some transfer instructionsdepend on the MCR.

    LengthTypical Execution Time in �s

    In-struc-

    AddressIdentifier

    Description

    Lengthin

    Words

    DirectAddressing

    IndirectAddressing 1)struc

    tionIdentifier

    DescriptionWords

    2) 31231x,147,151,154

    317 319 31231x,147,151,154

    317 319

    T

    IB a

    QB a

    PQB a

    PQB a

    Transfer contents ofACCU1-LL to ...input byte(MCR-dependent)output byte(MCR-dependent)peripheral output byte for 31x(MCR–dependent)... for 147... for 147 (MCR–dependent)

    1/2

    1/2

    1/2

    1/2

    0.21.10.21.158.758.8

    ––

    0.10.50.10.535.936.145.145.3

    0.060.120.060.1213.1013.53

    ––

    0.010.050.010.0510.310.3

    ––

    2.4+2.7+2.4+2.7+

    104.8+105.2+

    ––

    1.3+1.5+1.3+1.5+37.5+37.8+46.6+46.8+

    0.13+0.15+0.12+0.15+13.11+13.51+

    ––

    0.01+0.05+0.01+0.05+10.3+10.3+

    ––

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Transfer Instructions

    69S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    LengthTypical Execution Time in �s

    In-struc-

    AddressIdentifier

    Description

    Lengthin

    Words

    DirectAddressing

    IndirectAddressing 1)struc

    tionIdentifier

    DescriptionWords

    2) 31231x,147,151,154

    317 319 31231x,147,151,154

    317 319

    T PQB a

    PQB a

    PQB a

    PQB a

    PQB a

    ... for 151-7 (Bus 1m)

    ... for 151-7 (MCR–dependent)

    ... for 151-8 (Bus 1m)

    ... for 151-8 (MCR–dependent)

    ... for 154

    ... for 154 (MCR–dependent)

    1/2

    1/2

    1/2

    1/2

    1/2

    ––––––––––

    93.193.6118.9119.263.764.681.482.363.764.6

    ––––––––––

    ––––––––––

    ––––––––––

    94.9+95.4+121.2+121.4+65.0+65.9+83.0+83.9+65.0+65.9+

    ––––––––––

    ––––––––––

    T PQB a

    PQB a

    Digital Onboard I/O 3)

    (MCR-dependent)Analog Onboard I/O 4)

    (MCR-dependent)

    1/2

    1/2

    57.358.2

    ––

    53.954.449.249.7

    ––––

    ––––

    70.6+71.2+

    ––

    61.0+61.3+56.3+56.8+

    ––––

    ––––

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing 3) Access to digital onboard I/O 4) Access to analog onboard I/O

  • Transfer Instructions

    70S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Length

    Typical Execution Time in �s

    In-Address

    Lengthin

    Direct Addressing Indirect Addressing 1)Instruc-tion

    AddressIdentifier Description

    inWords

    2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    T MB a

    LB a

    DBB a

    DIB a

    bit memory byte(MCR-dependent)local data byte(MCR-dependent)data byte(MCR-dependent)instance data byte(MCR-dependent)

    1/2

    2

    2

    2

    0.21.20.41.52.72.72.42.7

    0.10.60.20.81.31.31.31.3

    0.060.120.060.140.240.160.240.16

    0.010.050.020.050.020.050.020.05

    2.4+2.7+3.3+2.9+4.1+4.5+4.1+4.5+

    1.3+1.5+1.7+1.5+2.2+2.4+2.2+2.4+

    0.13+0.15+0.11+0.16+0.13+0.16+0.14+0.16+

    0.01+0.05+0.01+0.05+0.01+0.05+0.01+0.05+

    T g[AR1,m]g[AR2,m]B[AR1,m]B[AR2,m]Parameter

    Register-ind., area-internal (AR1)Register-ind., area-internal (AR2)Area-crossing (AR1)Area-crossing (AR2)Via parameter

    22222

    –––––

    –––––

    –––––

    –––––

    +++++

    +++++

    +++++

    +++++

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Transfer Instructions

    71S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    InLength Direct Addressing Indirect Addressing 1)

    In-struc-tion

    AddressIdentifier

    Description

    Lengthin

    Words2) 312

    31x,147,151,154

    317 319 312

    31x,147,151,154

    317 319

    T

    IW

    QW

    PQW

    PQW

    Transfer contents of ACCU1-L to...input word(MCR-dependent)output word(MCR-dependent)

    peripheral output word(MCR-dependent)... for 147... for 147 (MCR–dependent)

    1/2

    1/2

    1/2

    1/2

    0.41.10.41.1

    64.464.6

    ––

    0.20.60.20.6

    40.440.652.853.1

    0.130.130.130.13

    15.0415.32

    ––

    0.010.050.010.05

    11.611.6

    ––

    2.6+2.9+2.6+2.9+

    121.6+120.5+

    ––

    1.4+1.5+1.4+1.5+

    41.8+42.1+53.9+54.1+

    0.14+0.16+0.14+0.16+

    14.99+15.43+

    ––

    0.01+0.05+0.01+0.05+

    11.6+11.6+

    ––

    1) Plus time required for loading the address of the instruction (see page 24) 2) With direct instruction addressing/ with indirect instruction addressing

  • Transfer Instructions

    72S7-300 Instruction list, CPU 31xC, CPU 31x, IM 151-7 CPU, IM 151-8 CPU, IM 154-8 CPU, BM 147-1 CPU, BM 147-2 CPU A5E00105517-10

    Typical Execution Time in �s

    InLength Direct Addressing Indirect Addressing 1)

    In-struc-tion

    AddressIdentifier

    Description

    Lengthin

    Words2) 312

    31x,147,151,154