Shift Register Petri Net

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A Petri Net Based Method for Storage Units Estimation*Albano P. Machado Paulo Romero Ma rtins MacielCentro de In fo rmi t i c a Centro de I n f o r m i t i c a C e n t r o d e InformLica

Unive r s idade Fede ra l de Unive r s idade Federal d e U n i v e r s id a d e F e d e r a l deP e m a m b u c o P e m a m b u c o PemambucoRecife, Brasi l Recife, Brasil Recife , B r a d

apm2@cin .u fpe .b r [email protected] [email protected]

Ahel GuilherminoS. Filho

Abstract - This work presents a structural methodologyfor computing the number of storage units (registers) inhardware/software co-design context considering timingconstraints. The proposed method is based on oneintermediate model - data flow net, specified by our team,that takes into account timing precedence and data-dependency. The considered hardware/software co-designframework uses Petri nets as common formalism forperforming quantitative and qualitative analysis.Keywords: Petri nets, Esrimares, Hardware/sofrware cu-design. Data-dependency, Srurage Units.1 Introduction

Most m odem electronic systems consist of dedicatedhardware and programmable components (called softwarecomponents). Over the last few years, the number ofmethodologies that concurrently apply design techniquesfrom different areas to develop mixed hardwarekoftwaresystem has been grow ing considerably.The concurrent design of mixed hardware/softwaresystems has shown to be advantageous when considered as

a whole instead of considering as independent entities.Nowadays, the electronic market demands high-performance and low cost systems. These requirements areessential for the market competitiveness. Furthermore,short time-to-market is an important factor. It means thatfacilitating the re-use of previous designs, faster designexploration, qualitative analysidverification in an earlyphase of the design, prototyping, and the reduction of therequired time-to-test, reduce the overall time required froma specification to the final product.When designing such mixed hardwarelsoftwaresystem, the analysis of design alternatives and the decisionof where to implem ent each part of system, that is, inhardware or in software, are very important tasks. Theestimation of quality metrics permits design spaceexploration and may guide the decision of theimplementation media of the system's parts [3]. Suchmetrics are calculated at system level, or rather, withoutreal implementation. Hence, such estimations also speed

up system's design and permit the analysis of designconstraints, providing a quick feed-back for designdecisions.Petri nets are a very well established family of formaldescription techniques, well suited for modelingconcurrent, asynchronous and non-deterministic systems.Many authors have shown the large use of Petri nets inseveral areas, such as computer science, electronicengineering, chemistry and business management.

This paper proposes an approach for estimating thestorage units, taking into account timing constraints andextends some previous works considering the data-dependency in the estimation process. The proposedmethod considers a data-flow net that capture data-dependency to calculate the number of registers and alsolakes into account timing precedence relation. We havedeveloped a framework based on Petri net forhardware/software co-design and methods for estimationshould be developed or adapted for being considered inthis design environment. We expect that this workrepresents an important improvement for the developedmethodology for hardware area estimation. The nextsection presents previous wo rks, followed by an overv iewof the system design framework in Section 3. Section 4introduces timed Petri net. Section 5 presents theintermediate Petri net model considered in this work.Section 6 describes the proposed methodo logy for storageunit estimation. Case studies are described in Section 7.Finally some conclusions and perspectives for futureworks are presented.2 PreviousWork

Several works, in the literature, concern withestimating bound for area costs [51, 1151, 1171, [201, [211,etc. Techniques such as clique partitioning are applied inorder to group variables that can be mapped together [31.Most of previous work in storage requirement estimationuse data-flow and control-flow graphs as an internalrepresentation, obtained by the compilation of a formalspecification language. [8] surveys some importanthardwarekoftware co-design systems environments:Cosyma, Vulcan 11,Lycos, Pure, SpecSyn, Pulis, Cosmos,

10250-7803-7952-7/03/$17.00 Q 2003 IEEE.


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etc. In Cosyma [16], the compiler outputs an ExtendSyntax Graph (ESG). Estimation are carried out based onhardware and software runtime. In Vulcan I1 [6] thedescription is compiled into a system graph model basedon a data-flow graph, hardware and softwareimplementation are statically estimated. The intermediatemodel in Lycos [ l l ] is based on CommunicatingControData Flow Graphs (CDFGk), in which a set ofmetrics is estimated including hardware area. Pure [24]stands for Petri net based Unified Representation. In thissystem, estimation is based on statistics obtained in thesimulation phase and user-interation. SpecSyn [4] uses asintermediate model the Specification level intermediateformat (SLIF), similar to a task-flow graph, whereestimation of hardware parameters are obtained. Cosm os[25J uses SOLAR as an intermediate unified model, thatcombines extended finite-state machines (EFSM) andremote procedure call (RPC). O ur framework considers asintermediate model - controlldata flow net, based ontimed Petri nets. This model allows for analysis ofbchavioral and structural properties[8]. Howev er, thiswork considers only the data-dependency representation.3 System Design

HardwareJsoftware co-design is a paradigm for thedesign of programmable and application specificcomponents. The considered framework (see Figure 1)takes in account two possible specification languages:Occam [71 and C-like descriptions. However, behavioralspecifications are translated into an intermediate modelbased timed Petri nets.

Qualitative analysis and verification phases is animportant step in the hardwarelsoftware co-design process,because it allows for errors to be detected at an early ph aseof the design and, of course, decrease the overall designcosts.

The hardwarelsoftware partitioning phase groupsprocesses in clusters considering those metrics computedin the quantitative analysis: communication cost [9], loadbalance and precedence relation degree [ lo ] and areaestimates [9]. As result, each obtained cluster isimplemented either as hardware device or in a softwarecomponent.

Figure I : Task Diagram

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4 Timed Petri NetPetri net is a family of formal modeling techniquesable to represent concurrency, no-determinism.

synchronization, timing constraints, control and data-dependencies. Besides, Petri nets have already proved tosupport algorithms for solving key problem s in modeling,synthesis, quantitative and qualitative analysis ofconcurrent systems [141, [191. Placeltransition Petri nets%e used to model a logical point of view of the systems,however no formal attention is given to temporal relationsand constraints [23], [26]. A place-transition ner is a 6-tuple N = (P, , I , 0,K , M,J where: P = {p l _..,ia.., .] isa finite set of places, T = It, ..., j,..., m / is a set oftransitio ns, I: P x T 4 N s the input matrix, 0: P xT 4 N is the ourpur morrix, K : + N U -] is a vectorof place capaciries an d M : + N is a marking vectorwhere MO s the initial marking.

The first temporal approach was proposed byRamchandani [18]. Time d Petri nets [221, [23], [26] arePetri nets extensions in which the time information isexpressed by duration (determinist timed net with ihreephase policy firing semantics) and is associated to thetransitions. A Timed Petri Nets is a triple N f = (N , D, Jwhere: N is a Petri net, D : + IR U 0 is a functionwhich associates to each transition I, the duration of thefiring di. C : + ( 0 i R i J , f E T i s a choicefunction which assigns a free choice probability to eachtransition of the net, whereE,,Tc c ( r J = I . T , E T i s a set ofstructural conflicting transitions.

The subclass called Marked Graph [I41 ischaracterized by the restriction in the number of input andoutput arcs of places. Each place has exactly one input andone output transition. More formally N is classified as amarked graph if only if, lI(p,)l=lan d I0fp;)l= I , Vp i EP. Marked graphs can represent synchronization andconcurrency, but, as places cannot have more than oneinput and output transitions, they cannot model mergingand conflict. They have been widely studied because theymodel a large number of practical systems and because oftheir simple analysis of properties. Marked Graphs aresuitable for representing d ata depend encies.

A stare of timed Petri net is defined by a triple offunctions, one of witch describes the distribution of tokensin places, the second distribution of tokens in (firing)transitions and the third one is the remaining firing timethat provides a history of transitions firings. A state s oftimed Petri net Nr is a triple s = (m . n, rJ where: m is amarking function, m:P + { O , l , ...): is a firing-rankfunction, n:T + {O , l , , . . ] : r is a remaining-firing-timefunction, which assigns the remain firing time to eachindependent firing (if any) of a transition. An initial sfafesi o f a ne t N I is a triple si = (mi, n r jJ .The remaining-firing-time function r, , is equal to the firing times d ( t ) fo rall those transitions f for which n,> 0.

d(t). if n, t i > 0 A I 2 k Sn, t) ,u n d e f i n e d , o t h e r w i s e ;WrcTJ r, f t J / h ] =


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and the marking mi is defined asa i p d ) mi(pJ = m e ( P I -E.(p,tj*i ( i J .

r e O r ( p lA state si is reachable from state s, if there is a

sequence of directly states from the state si o the state sAlso, a set S ( N f )of reachable states is defined as the set ofall states of a ne t N I which are reachable from the initialstates of the net N I . The slate siwhich is reachable from thestate si s thus obtained by the termination of the hexttiring (i.e., those firings for which the remaining firingtime is the smallest one), updating the marking of a net,and then initiating new firings (if any). A s f a f egraph G ofa bounded free-choice timed Petri net is a labeled directedgraph G ( N f )= (S ,D,) where: S is the set of reachablestates, D s a set of directed arcs, D c V x V , such that (si.s j ) is in D ff si is directly reachable from s,,h is a vertexlabeling function which assigns the holding time of thestate si= (mi,, r i ) to each state si E S(Nt) , h : +Re,h(si) = min ( r i ( t ) [ l l ) .

r e T ~ n i ( r J 0Step semantics [22] is a firing strategy that takes intoaccount maximal sets of concurrently enabled transitionsexecution. Thus, the set of reachable markings is therebyreduced.5 Intermediate Model

Petri nets have been considered the intermediateformat in own design framework. Two distinct modelswere developed in order to represent the behavior of theapplication being modeled: a control and data-flow models(See Figure 2). These models may he used independentlyfor computing metrics such as execution time, datadependency, resource estimation, etc. Besides, they canalso he bound for simulation purposes. Both models wereoriginally conceived for representing Occam specification,but others source languages like C/C++ are also beingconsidered. The control and data-flo w models timed P etrinets. Under the structural point of view, the model is amapping from description objects into Petri netcomponents. Transitions represent actions of originalspecification and have an associated duration. Places areused for connecting actions in the order in which they wereoriginally described.

In the data-flow model [12], places represent valuesand transitions represent arithmetic expressions, operatorsand constructs of the specification language. Each valueproduced by a process (including variables, constants andintermediate values) has an equivalent place, whosemarking models the presence of the value. There exists twospecial pairs of place and transitions for each pro cess ( s t a nand end), which feed all initial values and consume allfinal values. The translation process generates a net thatha s #I(pJ= #O(p)= l for every place p . but the s f a n andend places of each process has #I(pj= #O(p)=O,respectively. When a closure transition is added to the

model, between the en d place and the start place, the netbecomes a marked graph. There are four specialtransitions considered in the model: s t u n (linked to stunplaces), end (linked to end places), sink (when a variableis written) and clone (when a variable i s read).@star t

bFigure 2 Control and data-flow netsThe purpose of this model is to capture data-dependence. This model represents several operations

sequences that produce, modify or consume data. Themodel reflects the highest degree of the parallelism of th eprocess, since the actual order of the oper ation s isrepresented in the control flow model.This model allows integration with the control- flowmodel, bringing the possibility of joint system analysis,simulation, as well as an improvement in estimates results.The complete model and its formal definition is describedin [13].6 Estimation number of storageunits

Storage units are required for holding data valuesrepresented by the constants, variables and arrays of agiven behavior, For a given high-level behavioraldescription, the hardware design is divided into classes offunctional blocks: data-paths and controllers [ 9 ] .Therefore, one aspect that should he considered is thenecessary number of registers to execute a givenbehavioral description.

The simplest estimation strategy assumes that eachvariable in the behavior will be implemented as a separateregister or memory [8]. However, such an implementationmay have an excessive number of storage units, sincevariable values are not needed during the entire executionof the behav ior, It may be possible to minimize the numb erof storage units by mapping several variables that are notconcurrently used to the same register. The proposedapproach consists of estimating the number of registersconsidering causal dependencies captured by the Petri netdata flow model (datadepend ency between operators of adescription) as well as timing precedence between suchoperations.Two variables a and b can may be allocated into thesame register, if a and b are never In use at the same

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time. Therefore, our algorithm needs to analyze theintermediate representation program - data-flow model todetermine with variables are in use at the same time. Wesay a variable is live if it holds a value that may be neededin the future.To illustrate this approach we will start with a verysmall example, the Occam d escription bellow :PAR

INTa, b, C, d:PA Rc:= a + b

d: = c + bb: = a + dThe data-flow model generated is depicted in Figure 3 .Although processes are specified to work in parallel, theywere serialized due to variables data-dependencies. Thestate-graph generated for this net is shown in Figure 4.

O dFigure 3: Data Flow Model generated by translator

Figure 4 State graphAt the beginning of the process, in the state s l , the

sfan lace has one token, enabling the transition fo. Thistransition fires in parallel (step semantics) and o ne token isremoved from stan place and tokens are stored in placesa& b6 ca do . The firing associated with this transitionterminates reaching state sz. The marked places, in thisstate, enable transitions fl r rz, f3 and r4 . Firing theseenabled transitions concurrently, the state s3 is reached,tokens are storage in places al. l. b , , b2 , an d so on. In

order to simplify the graphical representation, annotationsthat do not are essential for ones unders tanding have beenomitted such as state holding time and transition remainingfiring time for instance, since all operations in this smalldescription have the same duration. Observing the changefrom state sj o s4 , it is worth note the simultaneous firingof transitions r,, r j and tlo. The transition r6 represents asummation of variable a with b . As we can see, variable ccannot share the same storage unit which holds the valuesof variables Q and b , since these variables still will be usedin the future, i.e., variables lifetimes overlap, as shown inthe state graph (state sg), where these variables aresimultaneous alive.The algorithm solution consists in finding the stateswith the maximal number of marked places, representingsimultaneous alive variables. According with the stategraph, the state s4 (c l . a3.u4, bs. b4J have five markedplaces representing variables. Looking at place a4 in thenet, we verify that it enables transition end, so this place isnot considered, because it simply waits the processtermination. Plac e b4 enables sink transition, so neither thisplace is considered, because an attribution was done. Themaximum number of simultaneously alive variables isobtaine d in states $4 (c,, a3, b j ) and ss c ~ ,3,b3) . Thus,three storagek units are necessary for this specification.The proposed algorithm is:

lnput : data-flow model - a timed Petri net N =f P , T, 1,0,D, ,MO ).Output: The number of storage units needed tocan y out the behavior.

I . Compute the state graph;Steps:11. For each state, count the number of placesrepresenting variables, throwing away the placesthat enable transitions like sink and end.III. Take the state with the largest number of markedplaces representing simultaneously alive variables.This number of places represents the number ofstorage units needed t o store variables.The time complexity for generating the state-graph ofthe net (marked graph, step semantics) is 0 ( T ) . T hecomplexity of the algorithm for estimating the number ofregisters is O( N * P J , where T represents the number of

transitions, P the number of places and N + [ I , T ] thetotal number of states. Thus, the total time complexity ofthe proposed approach is O(T + N * P J .7 CaseStudies

In order to validate the proposed method, we appliedit to four specifications. First, to an small example wherecomparisons with the clique partitioning approach weredone. Afterwards we considered the YdOrde r DifferentialEquation and the 5 Order Elliptic Wave Filter from theHLS benchmark suite [2] and compared the results withother previous works. Finally a vending machine wastaking into account. Besides estimating the number of

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storage units and compared the obtained results with ourprevious estimation [SI, two hardware implementationswere generated.7.1 A n SmallExamplevariable lifetimes (Figure 5) from [3].In this section we take the scheduled behavior andv, v v "2 ",v vi ". V% VI,r. v v* i

s. sFigure 5: Schedu led behavior and variables lifetimeTh e representation in Occam of this scheduled behavior, isdescribed below:EARI N Tvl,vZ,v3,v4,v5, v6,v7,vX,v9, v10, vll:SEQv3 :=v1+vZ

EA Rv5:=v6*v3"7:=v3-v4"ll:=vlo*v5"8 :=v5tv3v9: =v7tv1vl:=vll-vXvZ : vX*v9

PA R

ERR

The first step is to translate this code to theintermediate model (data-flow timed Petri net model). Thestale graph generated from the timed Petri nets have 17states. The maximal number of simultaneously alivevariables is shown in Table I.

Table I: Small ExampleState I Alive variables at the same time

Y , , vi , V 4 , V b . 1'10Y , . Y 3 . Y , . P b . V , Ov , * v 3 . V I . V 6 , Y I O

The presented result obtained by clique partitioningmethod was 5 registers for 11 variables. Unfortunately thismethod is an NF-hard problem, so in practice, greedyheuristics are employed [ I ] . Our algorithm found the sameresult of the clique partitioning, that is, five storage units.7.2 2" Or de r Different ia l Equation a n d the Sa OrderEll ipt ic Wa ve Fi l te r

In this section we applied the proposed method to twowell-know high level synthesis benchmarks from the HLSbenchmark suite: the 2"dOrder Differential Equation (DE)and the 5" Order Elliptic W ave Filter (EWF).T he DE specification bas 13 variables. The state graphgenerated from the timed Petri nets, obtained from this

Source I F i " a l UnibL B E l l S l I 2(+), 3(*)

Our Estimalim I 2(+). 3(*)ILF [20] I 2i+), 2(*)

Occam specification, has 31 states. The maximal numberof simultaneously alive variables is shown in Table 2.Thus, i t is necessary six registers.Table 2: 2"'Order Differential Eaua tion

Registen6 '4 '6 '

Slaw 1 Alive v a r i a b l e s ai the same time5 ,< I ?-%U,, u.rur, &!or 11 .13, !?( 0 I .. ",,".,~,,,~,~.,~,,,~,,/

The EWF specification has 19 variables. The st3tegraph from EWF has 64 states. Table 3 shows theniahimal numher o f siniul tmeuu\ly a live vxiahles. T h ~ ts.we need six storage units.Tahle 3. thc SIh Orde r Elliptic Wave Filter

I I Alive variablesst the same imetate

Experimental results on these benchmarks are givenin Table 4an d 5. Basically, w e comp ared our results withLBE [15], OASIC [ 5 ] , ILP [20].HAL [I71 and InSyn[21]. As we can see, we obtained the same lower boundestimate found by LBE [15], according Table 4. In Table5, we obtained smaller estimates than others. Thus, ourapproach finds some design alternatives w ith less registercost than these works.

Table 4 2"d Order Differential Equation

Table 5: 5* Orde r Elliptic Wa ve Filter~~~I S a v e e I FuneUonalUnIfs I Rcgjsten 1

1. T h e inpuIIoutpur variables are stored in registers2. The nput variables am NOT stored in re@irrerr+: addm (IS.0 nr). * p : 2-stape pipdined multiplicr(2S.O nr)

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This results were considered to compare our estimateswith those results obtained by conven tional scheduling andallocation processes.7.3 Vending Machine

Figure 6, depicts a structural view of the main control(dashed block) block and others modules of a vendingmachine specification. It was implemented in hardwareand successfully mapped onto FPGA Xilinx's XC4000Eseries, in 401 3EHQ240 family.

Figure 6 Vending MachineThe behavior of this machine is described below.After its reset, the machine waits for a coin. When the

client inserts the first coin, the machine stays in the waitingstate until a soft drink is requested. When a drink isselected, the machine verifies the stock for the particularsoft drink. If the money inserted is insufficient for thepurchase of the drink ordered, the machine refunds thevalue paid to the client, otherwise it calculates the changeand checks if the balance in the machine is sufficient togive the change. If so, the machine delivers the soft drinkand the change. If not, the client is notified and decideseither^ to pay more for the drink or to receive a refund.When giving the change, the machine calculates thechange value in number of coins of 50 and 10 cents. Thesoft drink vending machine's Occam specification isdepicted below:CHAN OF INT EM, VM, PR, RE, L D , LR, AC. NAC, HC,HNC, CA50, CA10, NMDSO, NMD10:INT change:PAR

IN'S coinvalue, tot alpaid, price, emvSE Q

re", ac, nac, p rv :SEQprice := 8change := 0totalpaid := 0pr v := 0WHILE p rv = 0SEQEM ? em"

SE QWHILE em" = 0

EM ? emvVM ? coinvaluetotalpaid := totalpaid +coinvalueP R ? pr vRE ? revTF

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SEQchange := rotalpaid ~ priceIFchange < 0LD ! 1

PA RHC ! 0HNC ! 0nmdlO := 0nmd50:= change/50CA50 ? ca50nmd50 (= 0"50


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about 27% of area reduction (gates), when the proposedmethod for register estimation w as considered.

Tab l e 7: Hardware area resu l t sI FPGAT a W G u na sh C*m*a

8

Previa IS"at ion OurEstimationI%*, >lis80 70,U0 73

Inumber of storage units using timed Petri net. Theapproach calculates the numbers of storage units based onthe state-graph analysis derived from a Petri net thatrepresents the data-dependencies of behavioralspecifications. The obtained results have been comparedwith those obtained by other methods, such as cliquepartitioning based method, ILP [20], HAL 17], LB E [15],OASIC [5] and InSyn [21]. The results in terms ofaccuracy were similar or better. With regard to the cliquepartition, the proposed method has lower complexity,since variable lifetime are not explicitly computed.Another advantage, for our particular framework, is theimprovement of our previous results, since we haveadopted timed Petri net as intermediate models and themethodology fo r estimation is still under developm ent. Asfuture works, we intend to use this same intermediatemodel for improving estimates of multiplexers andfunctional units.References

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Shift Register Petri Net