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7/14/2019 Sedra42021 AppA
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VLSI Fabrication Technology
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Microelectronic Circuits - Fifth Edition Sedra/Smith 2Copyright 2004 by Oxford University Press, Inc.
Figure A.1 Silicon ingot and wafer slices.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 3Copyright 2004 by Oxford University Press, Inc.
Figure A.2 (a) An 8-pin plastic dual-in-line IC package, (b) A 16-pin surface mount package.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 4Copyright 2004 by Oxford University Press, Inc.
Figure A.3 A typical n-well CMOS process flow.
(a) Define n-well diffusion (mask #1)
(b) Define active regions (mask #2)
(e) n+ diffusion (mask #4)
(f) p+ diffusion (mask #5)
(c) LOCOS oxidation (g) Contact holes (mask #6)
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Microelectronic Circuits - Fifth Edition Sedra/Smith 5Copyright 2004 by Oxford University Press, Inc.
Figure A.3 (Continued)
(d) Polysilicon gate (mask #3) (h) Metallization (mask #7)
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Microelectronic Circuits - Fifth Edition Sedra/Smith 6Copyright 2004 by Oxford University Press, Inc.
Figure A.4 Cross-sectional diagram of an n- andp-MOSFET.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 7Copyright 2004 by Oxford University Press, Inc.
Figure A.5 Cross sections of resistors of various types available from a typical n-well CMOS process.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 8Copyright 2004 by Oxford University Press, Inc.
Figure A.6 Interpoly and MOS capacitors in an n-well CMOS process.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 9Copyright 2004 by Oxford University Press, Inc.
Figure A.7 A pn junction diode in an n-well CMOS process.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 10Copyright 2004 by Oxford University Press, Inc.
Figure A.8 Cross-sectional diagram of a BiCMOS process.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 11Copyright 2004 by Oxford University Press, Inc.
Figure A.9 A lateralpnp transistor.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 12Copyright 2004 by Oxford University Press, Inc.
Figure A.10 p-Base and pinchedp-base resistors.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 13Copyright 2004 by Oxford University Press, Inc.
Figure A.11 Cross-sectional diagram of a symmetrical self-aligned npn SiGe heterojunction bipolar transistor (HBT).
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Microelectronic Circuits - Fifth Edition Sedra/Smith 14Copyright 2004 by Oxford University Press, Inc.
Figure A.12 A CMOS inverter schematic and its layout.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 15Copyright 2004 by Oxford University Press, Inc.
Figure A.13 Cross section along the plane AA of a CMOS inverter.
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Microelectronic Circuits - Fifth Edition Sedra/Smith 16Copyright 2004 by Oxford University Press, Inc.
Figure A.14 A set of photomasks for the n-well CMOS inverter. Note that each layer requires a separate plate: (a), (d), (e), and (f) dark-field masks;
(b), (c), and (g) clear-field masks.