Slide 1

Scanner Optimization for DPT

Bob SochaASML

MC

Esc

her

Immersion

EUV

Double

Patter

ning

/ Slide 2

Outline

SRAM gate DPT example

− Overlay, CDU, Resolution (Design) trade-off

Spacer Challenges

Conclusion

/ Slide 3

Enabling DPT

DPT for the 22nm node (logic) and 32nm node (memory) is a necessary realityOverlay is critical− DPT− Vertical scaling (3D layout)

Most cost effective DPT implementations will involve scanner optimization and design optimizationImplementation of DPT for one layer (such as spacer at logic gate for CDU) has design effects of other layers (increased M1 2-D complexity)The customer that most effectively optimizes the design and scanner together will produce the most cost effective productStrong need developing for closer interaction between designers,fab, and scanner vendor.How much of this interaction knowledge can be done in the designlibrary and in the place and route CAD tools.

/ Slide 4

Low k1: High Design to Wafer Integration

Low k1 (<0.4) : Integration of design, mask and Lithography processes

OPC & RET’s: PSM,

Scatterbars, C

PL, DDL

Verificatio

n

Sour

ce-

Mask

optim

izatio

n

Appl

icatio

nSp

ecifi

c tu

ning

Design forManufacturingDFM

Application SpecificManufacturing

Design space Manufacturing space

Litho aware design constraints

/ Slide 5

Outline

SRAM gate DPT example

− Overlay, CDU, Resolution (Design) trade-off

Spacer Challenges

Conclusion

/ Slide 6

Typical SRAM Gate Layer

Unit Cell needed for Area Calculation

• The Area of the SRAM cell is the most widely used Metric to determine the shrink of the node• As a result, the area must also be used to compare Litho-DPT to Spacer-DPT shrink capabilities.

•Comparison between Litho-DPT to Spacer-DPT based on 1-D geometries (1Dmetric) is not relevant

Pitch < 0.5λ/NA

w+CDUSE

s+OVSE

L+CDUSE

B+OVSE

ASE is a function of 3 variables RSE, OVSE and CDSE

/ Slide 7

Process Steps Required

LELE Spacer

/ Slide 8

Double patterning require better and more lithography

3-421# process steps relative to single exposure

1D, Mainly Memory2D, All2D, All Application

2-321#mask steps

7-20%*

3%

Spacer double

patterning

3.5%7%∆CD

7%20%Overlay (depending on DFM)

Litho double patterning

Single exposure

Litho exposure equipment parameter as percentage of CD

* Depending on the amount of “Design For Manufacturing” effort

/ Slide 9

OVSE and CDUSE requirements for 35nm HP SRAM(shrink of the 50nm HP SE SRAM area by 50%)

Litho-DPT• Below 50% line is the area of interest• OVSE must be less than 2.5nm for 50% shrink with Litho-DPT at CDUSE=3nm• If current CDUSE=3nm and OVSE=5nm, a 56.2% shrink can be done with Litho-DPT• If current CDUSE=3nm and OVSE=5nm, a 49.5% shrink can be done with Spacer-DPT

Spacer-DPT

/ Slide 10

Outline

SRAM gate DPT example

− Overlay, CDU, Resolution (Design) trade-off

Spacer Challenges

Conclusion

/ Slide 11

Cost of Ownership estimates for 32nm

* Mask cost based on 5000 wafers / mask usage

0

20

40

60

80

100

193nm Spacer DPT 193nm Litho DPT EUV

Lith

o C

ost p

er L

ayer

[$]

Fixed Operating Source Chemical CVD Etch Metrology Other Strip Reticle

Defect free mask Defect free mask / no pellicle/ no pellicleSource power / Source power / resist sensitivityresist sensitivity

Pattern splitPattern splitProcess Process complexity complexity Overlay & CDUOverlay & CDU

Pattern splitPattern splitProcess Process complexitycomplexityCDU control CDU control

ChallengesChallenges

Further cost reduction opportunity?

/ Slide 12

Spacer process can be used for random structuresDesired layout After spacer process applied

/ Slide 13

Spacer needs overlay friendly layout to enjoy overlay advantage from the self aligned process

Areas surrounded by geometry formed by spacer are less sensitive to overlay errors.Areas not surrounded by geometry formed by spacer are more sensitive to overlay errors. Possible CD error or bridging can occur.Without design change, overlay is still critical for spacer when exposing a clear field mask!

/ Slide 14

Spacer with overlay friendly layout to enjoy overlay advantage from the self aligned process

In areas not surrounded by geometry formed by spacer, the space width between patterns must increase.Design change to increase the space width between patterns may need tighter overlay for next layer.Design change to shift a pattern to increase space width may require verification of the electrical performance.With these design changes, the cell size may increase.

/ Slide 15

Spacer Challenges

CoO is higher with Spacer DPT compared to LELE/LFLE DPT− Spacer process integration/complexity increases cycle time

Not all designs can benefit from Spacer DPT self-alignment− Burdens the designer or makes design rules overly restrictive− Industry not yet ready for Spacer friendly designs