SC7314

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SC7314 Datasheet

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SC73144-CH OUTPUT STEREO AUDIO PROCESSOR WITH 4 STEREO INPUTS AND TONE/VOLUME CONTROLDESCRIPTIONThe SC7314 is a volume, tone (bass and treble), balance (left/ right) and fader (front/rear) processor for quality audio applications in car radio and Hi-Fi systems. Selectable input gain and external loudness function are provided. Control is accomplished by serial I2C bus microprocessor interface. The AC signal settings is obtained by resistor networks and switches combined with operational amplifiers. Due to the Used CMOS technology, low distortion, low noise and low DC stepping are obtained.

FEATURES* Input multiplexer: --4 stereo inputs --Selectable input gain for optimal adaptation to different sources * Four speaker attenuators: --4 independent speakers control in 1.25dB steps for balance and fader facilities --Independent mute function * All functions programmable via serial I C Bus * Loudness function * Volume control in 1.25dB steps * Treble and bass control * Input and output for external equalizer or noise reduction system2

ORDERING INFORMATIONDevice SC7314 SC7314S SC7314D Package DIP-28-600-2.54 SOP-28-375-1.27 SDIP-28-400-1.778

BLOCK DIAGRAM18 6 17 12 20 19 3 24 L 16 L1 L2 15 L3 14 L4 13 R1 8 R2 9 10 11 28 R3 R4 CREF Volume & Loudness Bass Treble Speaker ATT/Mute Volume & Loudness Input Selection & Gain Control Speaker ATT/Mute SCL

Bass

Treble

27

Serial Bus Decoder + Latches

SDA

26

DGND

25

Supply

R 1 2 5 7 22 21 4 23

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ABSOLUTE MAXIMUM RATINGSCharacteristics Supply Voltage Operating Temperature Storage Temperature Symbol VS Tamb Tstg Ratings 10.5 -20 ~ +75 -40 ~ +150 Unit V C C

QUICK REFERENCE DATACharacteristics Supply Voltage Maximum Input Signal Handling Total Harmonic Distortion ,V=1Vrms, f=1kHz Signal To Noise Ratio Channel Separation, f=1kHz Volume Control, 1.25dB Step Bass And Treble Control, 2dB Step Fader And Balance Control, 1.25dB Step Input Gain, 3.75dB Step Mute Attenuation S/N Sc -78.75 -14 -38.75 0 100 106 103 0 +14 0 11.25 dB dB dB dB dB dB dB Symbol Vs VCL THD Min. 6 2 0.01 0.1 Typ. 9 Max. 10 Unit V Vrms %

ELECTRICAL CHARACTERISTICS (Refer to the test circuit)(Tamb=25C,VS=9.0V,RL=10k RG=600 all controls flat(G=0), f=1kHz,Unless otherwise specified) Characteristics SUPPLY VOLTAGE Operating Supply Voltage Operating Supply Current Ripple Rejection Of Supply Voltage INPUTS SELECTORS Input Resistance Clipping Level Input Separation (note 2) Output Load Resistance Minimum Input Gain Maximum Input Gain Step Resolution Input Noise DC Steps RII VCL SIN RL GIN(MIN) GIN(MAX) GSTEP eIN VDC G=11.25dB Adjacent gain steps G=18.75 to MUTE Pin 6,18 Input 1, 2, 3, 4 35 2 80 4 -1 0 11.25 3.75 2 4 4 20 1 50 2.5 100 70 k Vrms dB k dB dB dB V mV mV(To be continued)

Symbol VS IS SVR

Test conditions

Min. 6

Typ. 9 20.0

Max. 10.0 35.0

Unit V mA dB

60

80

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Characteristics VOLUME CONTROL Input Resistance Control Range Minimum Attenuation Maximum Attenuation Step Resolution Attenuation Set Error Tracking Error DC Steps SPEAKER ATTENUATORS Control Range Step Resolution Attenuation Set Error Output Mute Attenuation DC Steps BASS CONTROL (note 1) Control Range Step Resolution Internal Feedback Resistance TREBLE CONTROL (note 1) Control Range Step Resolution AUDIO OUTPUTS Clipping Level Output Load Resistance Output Load Capacitance Output Resistance DC Voltage Level GENERAL

Symbol RIV Crange AV(min) AV(max) ASTEP EA ET VDC

Test conditions

Min. 20 70 -1 70 0.5

Typ. 33 75 0 75 1.25 0

Max. 50 80 1 80 1.75 1.25 2 2

Unit k dB dB dB dB dB dB mV mV

AV=0 to 20dB AV=-20 to 60dB

-1.25 -3

Adjacent attenuation steps From 0dB to AV max

0 0.5

3 7.5

Crange SSTEP EA AMUTE VDC Adjacent attenuation steps From 0dB to MUTE

35 0.5

37.5 1.25

40 1.75 1.5

dB dB dB dB

80

100 0 1 3 10 16 3 58

mV mV

GB BSTEP RB

Maximum boost/cut

12 1 34

14 2 44

dB dB k

Gt TSTEP

Maximum boost/cut

13 1

14 2

15 3

dB dB

VOCL RL CL ROUT VOUT

THD=0.3%

2 4

2.5

Vrms k 10 nF V V 15 V V dB(To be continued)

30 4.2

75 4.5

120 4.8

BW=20 ~20kHz,flat output muted Output Noise eNO BW=20 ~20kHz,flat All gains=0dB A curve, all gains =0 dB Signal To Noise Ratio S/N All gains=0dB; Vo=1Vrms

2.5 5 3 106

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Characteristics

Symbol

Test conditions AV=0,VIN=10mV AV=-20dB, VIN=1Vrms AV=-20dB,VIN=0.3Vrms

Min.

Typ. 0.01 0.09 0.04

Max. 0.1 0.3

Unit % % % dB

Distortion

d

Channel Separation Left/Right Total Tracking Error BUS INPUTS Input Low Voltage Input High Voltage Input Current Output Voltage SDA Acknowledge NOTES:

Sc AV=0 to dB 20 AV=-20 to 60 dB

80

103 0 0 1 2

dB dB

VIL VIH IIN Vo Io=1.6mA 3 -5

1

V V A V

+5 0.4

(1) Bass and treble response see Figure 16. The center frequency and quality of the response behavior can be chosen by the external circuitry. A standard first order bass response can realized by a standard feedback network. (2) The selected input is grounded through the 2.2F capacitor.

PIN CONFIGURATIONS

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TYPICAL CHARACTERISTICS PERFORMANCE

Loudness (dB)

Loudness (dB)

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Channel Separation (dB)

THD & Noise (%)

THD (%)

THD & Noise (%)

Noise (V

Noise (V

Loudness (dB)

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TYPICAL CHARACTERISTICS PERFORMANCE (continued)

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SC7314

APPLICATION NOTES1. I2c bus interface Data transmission from microprocessor to the SC7314 and viceversa takes place through the 2 wires I 2C BUS interface, consisting of the two lines SDA and SCL(pull-up resistors to positive supply voltage must be connected). 2.Data validity As shown in Figure 17, the data of the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW.

Fig. 17 Data Validity on the I2C BUS

3. Start and stop conditions As shown in Figure 18, a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.SCL//

I2C BUS

SDA//

start

stop

Fig. 18 Timing diagram of I2C BUS

4. Byte format Every byte transferred on the SDA line must obtain 8 bits. Each byte must be followed by the an acknowledge bit. The MSB is transferred first. 5. Acknowledge The master (microprocessor) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse(see Figure 19). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remain at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.

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Fig. 19 Acknowledge on the I2C BUS

6. Transmission without acknowledge Avoiding to detect the acknowledge of the audioprocessor, the microprocessor can use a simpler transmission: simply it waits one clock without checking the slave acknowledgig, and sends the new data. This approach of course is less protected from mis-working and decreases the noise immunity.

SOFTWARE SPECIFICATION1. Interface protocol The interface protocol comprises:

A start conditions A chip address byte, containing the SC7314 address (the 8 th bit of the bytes must be 0). The SC7314 must always acknowledge at the end of each transmitted byte. A sequence of data(N-bytes + acknowledge) A stop condition (P)

2. Chips address 1 (MSB) 3. Data bytes MSB 0 1 1 0 0 0 0 1 1 1 1 1 B2 0 1 0 1 1 B1 B1 B1 G1 0 1 B0 B0 B0 G0 C3 C3 A2 A2 A2 S2 C2 C2 A1 A1 A1 S1 C1 C1 LSB A0 A0 A0 S0 C0 C0 Volume Control Speaker ATT L Speaker ATT R Audio switch Bass control Treble control Function 0 0 0 1 0 0 0 (LSB)

Note: Ax=1.25dB steps;Bx=10dB steps;Cx=2dB steps;Gx=3.75dB steps

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SDETAILED DESCRIPTION OF DATA BYTES1. Volume MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A2 A1 0 0 1 1 0 0 1 1 A1 LSB A0 0 1 0 1 0 1 0 1 A0 Function Volume 1.25dB steps 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 Volume 10dB steps 0 -10 -20 -30 -40 -50 -60 -70

For example, a volume of 45dB is given by: