Sarnoff, March 16, 2001Janusz Starzyk1 School of Electrical Engineering and Computer Science

Sarnoff, March 16, 2001 Janusz Starzyk 1

Janusz Starzyk

School of Electrical Engineering

and Computer Science


Research Topics

• Virtex - FPGA Design of GPS Receiver

• Modeling and Test of Mixed Systems with Embedded Software

• CAD Tools for Circuit Analysis and Test

• Neural Network Data Classification

• Focused Reducts and Rough Sets in ATR

• Design of Self-Organizing Neural Network Architectures (Analog and Digital)

• Design of Dynamically Reconfigurable Architecture for Mobile Communication Applications


Graduate Students

• PhD students • Al_Aqeeli, Abdulqadir • Alsolaim, Ahamd • Ding, Mingwei• Guo, Yongtao • Liang, Jing • Liu, Dong • Nelson, Dale • Pang, Jing • Zeng, Yujing • Zou, Jun

•MS Students• Chang, Ivan• Lin, Tao• Liu, Tsun-Ho • Norris, Eugene• Gunavardena, Sanjeev • Zhou, Zen


Research Sponsors

• Federal Aviation Administration

• National Institute of Standards and Technology

• Air Force Office of Scientific Research

• Wright Laboratories

• Sarnoff Research Corporation


GPS Space Segment

24 satellites

6 Orbital planes

55 degrees inclination

20 200 km above the Earth's surface

11 hours 58 minute orbital period

Visible for approximately 5 hours above the horizon

Abdulqadir Alaqeeli, Yongtao Guo, Jing Pang

FPGA Design of GPS Systems


GPS Positioning Signals

Signal Frequency (MHz) Wavelength (cm)L1 154fo = 1575.42 ~19L2 120fo =1227.60 ~24


GPS Receiver

Front End Structure


GPS Receiver

Signal Acquisition / Signal Tracking


Satellite Signal Anomalies

• Focus on Signal Quality Parameters:

• Carrier-to-Noise Ratio

• Shape of Correlation Function

• False Acquisition Peaks

• Code-Carrier Divergence

• Sudden Change in Code and/or Carrier

• Change in the Satellite Code


GPS Block Processing

• The following parameters are estimated using

1-ms blocks of sampled data:

• Code Phase

• Frequency and Carrier Phase

• Carrier-to-Noise Ratio

• No tracking loops are used !

….. …..

1 ms = 5000 samples


GPS Block Processing

• Sampled Satellite Signal Model:

]))((2sin[ 0, kmffTDACs iiIFskkki

i, represents ith ms

sTs6102.0

5000,2,1 k

5000)1( imi


Code and Carrier Frequency Acquisition

Sampledsignal

Sk

)2cos( kfT rjs

1 block

rf

rC

jpI ,

jpQ ,

MaxEnergy

Detector)2sin( kfT r

jsMax

22 QI

Correlator

Correlator

Local CA codeoffset=p

LPF: Bandwidth 2.2MHz.5000,2,1 p

sTs7102


GPS ReceiverSoftware Simulation With MATLAB

KHzfMHzfMHzf simifidealif 4246.125.1 __ Result:


GPS Receiver– signal acquisition

Cos map

RF front end A/D (5MHz) Quad Mixer

NCO

GPS Signal Processor

Sin map

C/A code Generator

Conjugate Multiplier

Peak detector Absolute

FFT(complex)

IFFT(complex)

FFT(complex)

Block Diagram of GPS Signal Acquisition

Hardware Implemented on Virtex FPGA


GPS Receiver

Hardware ImplementationFRE_SEARCH: for j in 1 to 10 loop

i:=j;

SIN_COS_MODULOR(sv_data,i,1,svi);

SIN_COS_MODULOR(sv_data,i,2,svq);

TO_COMPLEX(count,svi,svq,svi_svq);

FFT_IFFT_TRANSFER(count,svi_svq,sv_f,true);

COMPLEX_MULTIPLY(sv_f,caf,sv_f_caf);

FFT_IFFT_TRANSFER(count_fft,sv_f_caf,sv_c,false); --vector multiplying

POWER_DETECTOR(sv_c,Y_E(i));

if Y_E(i)>MAX_POWER then

MAX_POWER :=Y_E(i);

MAX_FREQ := integer(fr)+integer(freq_sta)+(i-1)*integer(freq_step);

end if;

end loop;

KHzfMHzfMHzf simifidealif 4246.125.1 __

Result: Just as MATLAB simulation result


GPS C/A Code Generator

PRN(pseudo-random noise) C/A-code

Highly stable external 10.23 MHz oscillator

Clock division to obtain 1.023 MHz clock

10 bit LFSR with a 1023 chip length

Internal setup for satellite selection

FPGA implementation

Signal displaed on digital oscilloscope

Jing Pang


GPS C/A Code Generator

Block diagram of C/A code generator design

10 bit LFSR

10311 XXG 10 bit LFSR

109863212 XXXXXXG

External 10.23MHz clock input

1/10 frequency divider

1.023MHz clock output

clockdatain

testerout

digital oscilloscope


GPS Signal Generator


P-Code Generator


Virtex FPGA


Nallatech Board


ICS-Card

ADC

Analog GPS signal

8MHz 12-bit Samples

Hard Drive

Nallatech’s

Virtex Board

PCI BusMax 33MHz

8MHz (up to 50MHz) 12-bit Samples

The samples go to the Hard Drive for storage and to the Virtex Board for real-time processing

GPS Signal Acquisition Al_Aqeeli, Abdulqadir


Code Phase Search(n search bins)

1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1

0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 1 1

1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1

1 0 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 0 0 0

Shift=0

Shift=1

Shift=m

Shift=n-1 Inco

min

g C

od

e

0 - - P - 0 - - 0


Walsh Transform(WT) Based Correlator

• Only one transform is required• nlog(n) real additions (or subtractions).

Permutation WT PermutationIncoming

signal

WT and PN codes are permutationally similar


Permutations Generator

RAM

WA

+

Y(2:0) 3

3 Address

3-bitCounter 3

for simplicity, example of 3bit PN code is shown


Walsh Transform

+

+

+

+

+

+

+

+

Positive ConnectionNegative Connection

X0

X1

X2

X3

Y0

Y1

Y2

Y3


1024-Point Walsh Transform

• Impossible to build a completely parallel architecture for 1024-point WT.

• Why? (I/O pins, silicon (or logic) area)

• Partition 1024 butterfly into smaller butterflies. (parallel arch. for small butterfly)

• 64 blocks of these 32-point WTs


Implementation of WT-Based PN Correlator

RAM RAM

32-point WT

32-point WT

controllers

Peak-search circuit

Incoming samples


Design Performance

• silicon area (60% of Virtex FPGA)

• New code phase every 3 code periods.

• Max. Freq. = 96MHz

• 20 times faster than FFT-based arch*.

• WT hardware correlator is 2500 times faster than WT software correlator.

This can be up to 600 times faster if current design modifications work

successfully


Modeling and Test of Mixed Systems with Embedded Software

Objective - build a behavioral model for WSV consisting of:

Analog parts:

Probe/Time-Base/Trigger Generator/Frequency Counter

Digital Parts:

PLD Controller for Probe/Time-base/Frequency Counter

Software:

Real C/C++ programs for PLD controller used as input variables to the behavioral model.

Interfaces:

· between analog/digital parts, digital parts/software

Liu Dong


Behavioral Modeling of Analog Parts

• Selected SABER® from ANALOGY Inc. as Model-Build and Simulation Package for analog parts of the system

• Particular tasks:

Integrate design, modeling, simulation, and analysis into one platform throughout the whole process

Provide interface with SPICE/MATLAB programs

Use Hardware Description Language MAST for mixed-signal circuits

Run a simulation that contains behavioral and transistor level component simultaneously.


Silicon Board after 2005

RF? / Analog

200 32 Bit ASPP’s

ImageSpeech

DataGesture

50 GIPS-500GOPS

www

0.1µm , 200M+ Transistors

More than IP assembly!!

20 MbyteDistributed Memory

200MHz

reconfigurable interconnect

FLEXIBILITY - REUSE - IP

Embedded Software

1 M gatereconfigurable

computing

1 M gatehardwired

logic<1 Volt

2 Watt

ENERGY/OP : 100


System Design and IP UML

cC++, JAVAMATLAB

Global System Thinking

System specs -> Software

200M+ transistors

People

CAE, IP, VSIA

200M+ transistorSoC Architecture

x[i]=fft(4y[k])...

S

A

VHDL

1V,1Watt

Source: DeMan (ISSCC99)


CAD Tools for Circuit Analysis and Test

Mixed signal and mixed mode system analysis

C++ program to generate system equations

Small sensitivity analysis and fault testing

Ambiguity group partition

Large sensitivity analysis

Catastrophic fault detection


Woodbury formula in matrix theory

Time Sampling

1111111 VAPVASPAAVPSA

1

0

110

110

10

1

01

)(

)(

TQPTQdiagPTT

QdiagPTT

tt

t

,.........

...

......

...

...

22

11

22

11

2

1

21

22221

11211

0

110

ffff lk

lk

lk

nlk

lk

lk

nfnn

f

f

t

x

x

x

x

x

x

XQdiagXXX


Test Equation

Single measurement node of single excitations:t

lklklkifiii ffxxxX ]...[]...[

221121

iMF

b

if

i

i

mlk

mlklk

m

lklklk

lklklk

mi

i

i

iM X

xxx

xxx

xxx

X

X

X

X

ff

ff

ff

...

...

......

...

...

......

2

1

)()()(

)2()2()2(

)1()1()1(

2

1

2211

2211

2211

The same measurement node of different locations of the same excitations :

Test equation relates the limited measured circuit responses with the faults in a linear way!


Fault Diagnosis

Fault Detection Different measured results on fault-free and

faulty circuit indicates faults detected.

Idea of Fault Location: find out which columns in a known

coefficient matrix satisfy the test equation

Problem of fault location is transformed into math problem:

Locate the minimum size ambiguity group

mb

mb

mb

bbb

bbb

MPb

p

p

p

xxx

xxx

xxx

X

...

......

...

...

21

21

21

222

111


Filter Example Circuit


Resistive Example Circuit

20 nodes, 42 parameters, and 2 faulty parameters {R6, R26}

7 voltage measurements on node {2}

J is applied between ground and node {2, 5, 7, 8 , 11, 17, 19} respectively

n=19, p=42, f=2, m=7, f+1<m<p

Model of OP AMP


Non-zero vector of measured deviations between fault-free circuit and CUT indicates that at least one faults is detected by the given measurements.

Fault Detection

002i-1.3729e+ 003-3.5511e-

013i-2.1975e+ 014-5.1196e-

011i-6.1077e+ 011-1.5544e-

007i-1.4482e- 008-3.7453e

002i-7.0256e+ 001-2.6940e

007i-3.5430e- 006-1.0007e-

002i-1.3729e+ 003-3.5511e-

MX

Assume R6 and R26 deviates as left, measure nodal voltage of node {2} for the CUT and corresponding fault-free circuit

/50.510000/120000/16 eG

/63324.4111100/175000/126 eG


Fault Location

Summary of ambiguity locating technique:

Gaussian elimination any independent set will dependent

on the measurement deviation vector

QR factorization find the linear combination matrix

Theorem and Lemmas locate the suspicious faulty groups

Swapping performance reduce the size of the qualified

ambiguity groups

The ambiguity group with minimum size is

concluded as the solution the fault location!


C++ program Matlab program

Spice format input

System admittance

matrix

Modeling complex parts, i.e. CMOS, NPN, motor

Ambiguity group partition

System test equation (integration method for electro-mechanical system)

For each ambiguity group, find minimum form linear combination matrix

Solution invariant matrix

Obtaining detectable faults

Block diagram of my program MASTA (mixed-mode ambiguous system testability analysis program)

CAD Tools for Circuit Analysis and Test


Concept of “ Logic Brain”

Random learning data generation

Multiple space classification of data

Feature function extraction

Dynamic selectivity strategy

Training procedure for data identification

FPGA implementation for fast training process

Neural Network Data Classification

Sarnoff, March 16, 2001 Janusz Starzyk

Clustering for Classification of HRR Signals

-3 -2 -1 0 1 2 3

-2

-1

0

1

2

3

y

x

the sample dataGaussian approximation of the whole classmulti-Gaussian approximation

•Zeng, Yujing


Sample of Clustering Results


Cluster Growth Program


Distribution of MD and AMD


Threshold = Ratio * MinDistance


Comparison with k-means clustering

-0.2 0 0.2 0.4 0.6 0.8 1 1.2 -0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

class01 class02

On Iris data 95% correct classification vs. 90% for k-means


Application to Image SegmentationApplication to Image Segmentation


Segmentation Result by Centroidlinkage

( err = 11.72/pix, 263 regions)

Segmentation Result by Clustering ( err = 6.57/pix, 282 regions)



Segmentation Result by Centroidlinkage

( err = 7.23/pix, 648 regions)

Segmentation Result by Clustering ( err = 6.57/pix, 282 regions)



Future WorkFuture Work

• Extending the clustering program to higher dimensions;

• Finding the preprocessing suitable for the clustering program

• Developing hierarchical clustering program based on the current approach

• Improving the estimate of the thresholds used in the cluster growth program and the merging program


Rough Sets vs Fuzzy Sets

Fuzzy Sets - How gray is the pixel

Rough Sets - How big is the pixel

• Nelson, Dale


High Range Resolution Radar

P

R

O

CESS

OR

TRANSMITTEDWAVEFORM

REFLECTED WAVEFORM

0 1 TIME

UNKNOWNAIRCRAFT


HRR Signals on Two Targets

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

0 50 100 150 2000

1

2

Target A Target B


Partition the Signal

Interleave Partitioning

1 128

1 128

1 128

1 128

1

1st 2nd 3rd 4th 5th 6th 7th 8th

1 Piece

2 Pieces

4 Pieces

8 Pieces


Why Use a Wavelet Transform?

0 200 400 600 800 1000 12000

5

10

15

20

25

30

35

40

45

50Feature and Maximum Cluster Sizes

Feature Index

Cluster

Size

Original Signal

Best-20/60 signalsClassified

BestWavelet50/60 SignalsClassified!!

Many features are better than the best from original signal


Binary Multi-Class Labeling

-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.250

2

4

6

8

10

12

14

16

18

Range Bin Value

Target Gaussians Bin 910

target 1target 2target 3target 4target 5target 6

-0.1 -0.05 0 0.05 0.1 0.150

2

4

6

8

10

12

14

Range Bin Value



0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50

1

2

3

4

5

6

7

8

9

10

Range Bin Value



0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.020

50

100

150

200

250

Range Bin Value




Weighting Formula

n

i i

n

ii

t

Pcc

PccPccPcc

W

1

max1

max

11

11

1


Classification Results


Results TestingDiv. Sel. Pcc Pdec Pcc Pdec Pcc Pdec Pcc Pdec

1 1 0.7922 0.9038

2 1 0.79095 0.79726

2 2 0.79381 0.75705 0.81229 0.94424

2 1st 0.91704 0.73964

2 2nd 0.43967 0.7954 0.79694 0.94942 0.88116 0.992

Sarnoff, March 16, 2001 Janusz Starzyk5 10 15 20 25 30 35 40 45 50

1000

2000

3000

4000

5000

6000

7000

8000

9000

10000Run Time

Number of Bins

Tim

e

Rough Set Theoretic HRR ATR

0 1 TIME

METHOD

-Normalize Signal

-Partition Signal

- Block

- Interleave

-Wavelet Transform

-Binary Multi-class Entropy Labeling

-Entropy based Range Bin Selection

-Determine Minimal Reducts

-Fuse marginal reducts for classification

BREAKTHROUGHS-Reduct (classifier) generation time from exponential to quadratic !-Fusion of marginal (poor performing) reducts-Wavelet Transform Aiding-Multi partition to increase number of range bins considered-Use of binary multi-class entropy labeling-Entropy based range bin selection-Performance within 1% of theoretic best-Max problem size increased by 2 orders of magnitude

APPLICATIONS

-1-D Signals

-HRR

-LADAR vibration

-Sonar

-Medical

-Stock market

-Data Mining

Quadratic

Exponential


Design of Self-Organizing Neural Network

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

MbyNMUX

+/-

EBE EBE EBE

ThresholdValue

EBE

ThresholdValue

Jing Liang, Mingwei Ding, Yongtao Guo


Analog CounterLiang Jing

C 1 C

2

M 1 M

2

M 3 M 4

M 5

Clk_in

V_ref

Clr

V_out

Vdd

Fig. 2 The analog counter


Analysis of the OperationAnalysis of the Operation

34

33

44MM I

LW

LWI

dt

dVCII C

Mo2

4 2

)( 32

1

4

3

3

42 tprefddC VVV

C

C

L

L

W

WV

C1

C2

M1

M2

M3

M4

M5

Clk_in

V_ref

Clr

V_out

Vdd

Fig. 2 The analog counter

dt

dVCI C

C1

1 1


Mutual Information Principle

1

0

1,1,1,1, )1log(1)log(a a

ca

a

ca

a

ca

a

ca

p

p

p

p

p

p

p

pE

The entropy based mutual information is defined as follows:

max

1E

EI

cn

ccc ppE

1max )log(where

and the differential entropy

)1log()1(log)( pppppI

Use a symmetrical function


Mutual Information Principle

Fig. 4 Mutual information building function and its approximations

Two approximation are usedlinear:

and quadratic approximation:

)5.021(2log)( ppI

)1()2(log4)( pppI


Mutual Information Learning


ENTROPY-BASED EVALUATOR

PC

I Interface Core

PC

I Interface Core

FIFO

Ctrl

FIFO

Ctrl

EB

E Interface

EB

E Interface

R1

R2

Fig.3 FPGA-based Architecture

Control UnitControl Unit

DMUX

Reg

Reg

LUTLUT

ECU

ECU

ComparatorUnit

ComparatorUnit

Output

PCI

Display

ReqStartDone

EBE

OE

MUX

SEL SEL

Yongtao Guo


CLK

DATA

Start

Request

Done

N_1

N_2

OE

MuxSelect1

MuxSelect2

in_data

Threshold

in_threshold

Curr_Entropy

Max_Entropy

out_data

OutThreshold

State

Nextstate

34 45 56 67 78 89 9A AB BC CD DE

0E 17

3 3 3 3 3 3 3 3 3 3 3

0E 17 1E 1B 10 06

34 45 56 67 78 89 9A AB BC CD DE

0E 17

0E 17 1E 1B 10 06

1 1 1 1 1 1 1 1 1 1 1

67

EF

1E

0

0

00

EF

1E

00

3

0

ns6 8 10 12 14 16 18 20 22 24 26 28

Simulation Results


EBE hardware model:Memory circuit (LUT)Comparator unitECU Two registers

Hardware Implementation

Threshold

MaxInfo

LUTLUT

ECU

ECUComparator

Unit

ComparatorUnit

EBE

OE


Hardware Implementation ECU Architecture

From LUT

From LUT

To LUT

To COM

M

R

>

Threshold

N

T

>

R

>

ThresholdAdjustment

RMUL

DIV

SHI

R

+/-

R

Figure-Entropy Calculating Unit


Synthesis & Performance--Map design to Virtex


Synthesis & Performance--FPGA Map


Synthesis & Performance--Schematic


Synthesis & Performance--FPGA Floorplan

Vendor: Xilinx

Family: VIRTEX

Device: V800BG432

Speed: -4

Number of External GCLKIOBs 1 out of 4 25%

Number of External IOBs 47 out of 316 14%

Number of BLOCKRAMs 4 out of 28 14%

Number of SLICEs 463 out of 9408 4 %

Number of DLLs 1 out of 4 25%

Number of GCLKs 1 out of 4 25%

Number of TBUFs 256 out of 9632 2%

Number of flip-flops: 336

Minimum period: 24.838ns

Maximum frequency: 40.261MHz

Total equivalent gate count for design: 88,186

Additional JTAG gate count for IOBs: 2,304


System-on-a-Chip for future mobile terminals

System on a Chip (SoC)

Micro-controller DSP

Dynamically Reconfigurable

Architecture

Memory

Peripherals

Alsolaim, Ahamd


DReAM Architecture

Processing Plane

Communication Plane

Configuration Plane

I/O Plane

Control Plane


DReAM Architecture

Reconfigurable Processing Unit (RPU)

Fast local connections lines

Dynamic Switching Box Unit

Global connection lines

Configuration memory

I/O unit.

Local Communication switching unit.

Global Communication switching unit.


Block diagram of the RPU

Input from Global connections

Output to local connections Output to Global connections

RAP1RAP2

Input Interface (TXU)

Output Interface (RXU)

RAM 2 RAM 1

ControlSDP Unit

Input from local connections


Operation(N repetitions of single

operations)

# RAPs used(0.35 m CMOS)

Number of cycles

Freq. [MHz]

Multiply with changing Y 2 10*N+1 11.8

Multiply with Fixed Y

2 N+2 100

MAC with changing Y

2 11*N 10.9

MAC with fixed Y 2 N+2 100

Division 2 N+2 to 43*N 100 to 2.8

Addition 2 N 120

Subtraction 2 N 120

Performance of all the RPU


Scrambling code

QPSK Modulation

Walsh Code

Multimedia

Binary Data

Text

Image

Compression

CRC

Interleaving

Rate MatchingAdd additional bits:

PilotFrame formatPower command

RRC Filter

I

Q

Walsh Code

Scrambling code

RRC Filter

QPSK Modulation

RRC Filter

I

Q

Walsh Code

Walsh Code

Scrambling code

Scrambling code

RRC Filter

QPSK Modulation

QPSK Modulation

LPF

LPF

De-Compression

CRC

De-Interleaving

Rate Matching

Channel

For simplicity, A/D, D/A, RAKE, Synchronization, and Channel estimation are omitted for simplicity.

Matlab simulation environment


Behavioral Model of Intel 8031Phillip Southard

Design of Pass Transistor VLSI Cell Library

Tao Lin, Phillip Southard

Recent Projects Supported by Sarnoff


Intel 8031 with 8-bit CPU, 64K Data & Memory Space

128 bytes of on-chip Data RAM

32 bi-directional/individually addressable I/O lines

2 16-bit timer/counters

6-source/5-vector interrupt structure

Synthesize the RTL and behavior model of Intel 8031

Xilinx FPGA implementation

Phillip Southard

Behavioral Model of Intel 8031


Project Status

• Design process was demonstrated by using a subset of instructions from the 8031

• Process for modeling a microcontroller was successful.

• Testing completed with a hardware modeler verified that instructions were implemented correctly.


The purpose is to generate a PTL library comparable to the general CMOS library and examine the possibility of using PTL in the top-down design.

Tao Lin, Phillip Southard

Design of Pass Transistor VLSI Cell Library


Advantages of the PTL

1. Pass-transistor logic (PTL) has extremely simple basic cell which can generate all logic functions:

2. NMOS based pass-transistor circuitshave a great potential to surpass the CMOS not only in performance but also in area and power.

a a

b c

out


BDD in PTL Design

F

Tb

c

T

1 0

ETa

E

d

1 0

ET

E

a a’VDD

d d’VDD

c c’

b b’

F=abc+b’d+c’dF


Example: MUX2 in PTL

CMOS (12 transistors) PTL (7 transistors)

A

B S

S

OUT

OUT

A B

S

S

S

S

A B

S S


CMOS and PTL LayoutsCMOS PTL 37.5 x 80 = 300046 x 80 = 3680

Documents

Sarnoff, March 16, 2001Janusz Starzyk1 School of Electrical Engineering and Computer Science