SAM D21EL / SAM D21GL Summary - Microchip …ww1.microchip.com/downloads/jp/DeviceDoc/40001885A_JP.pdf · SAM D21EL / SAM D21GL Summary Author: ... Event System; DMA Controller; Timer

Datasheet Summary 40001885A_JP p. 1 2017 Microchip Technology

32 ARM

SAM D21EL / SAM D21GL

SAM D21L 32 ARM Cortex-M0+ 64KB 8KB SRAM 3248 SAM D21L 48 MHz 2.46 CoreMark/MHz HEX

()

ARM Cortex-M0+ CPU 48 MHz

MTB (Micro Trace Buffer)

32/64 KB 4/8 KB SRAM

(POR)(BOD) :

48 MHz (DFLL48M) 4896 MHz (FDPLL96M)

(EIC) 16 1 2 SWD (Siriarl Wire Debug)//

() SleepWalking

12 (DMAC) 12 5 16 /(TC):

16 TC (2x / ) 8 TC (2x / ) 2 TC 32 TC (2x / )

3 24 / (TCC):

:


32 ARM

4x () (PWM) () ( 5 )

32 (RTC) (/) (WDT) CRC-32 6 (SERCOM):

USART () I2C ( 3.4 MHz) SPI LIN

1 12 /350 ksps / (ADC) ( 18 ) 1/216 / (13/14/15/16

) 10 /350 ksps / (DAC) 4 (AC)()

I/O 38 I/O

48 TQFPQFN 32 QFN

- 1.623.63 V


......................................................................................................................... 1

................................................................................................................................ 1

1. ........................................................................................................................... 5

2. ................................................................................... 6

3. ................................................................................................................... 7 3.1. SAM D21ExL ............................................................................................................................... 7

3.2. SAM D21GxL .............................................................................................................................. 7

3.3. ........................................................................................................................ 7

4. ................................................................................................................ 9

5. .............................................................................................................. 10 5.1. SAM D21GxL ............................................................................................................................ 10

5.2. SAM D21ExL ............................................................................................................................. 11

6. ....................................................................................................... 12

7. ................................................................................. 13 7.1. Cortex M0+ .............................................................................................................. 13

7.2. NVIC (Nested Vector Interrupt Controller) ................................................................................. 14

7.3. Micro Trace ................................................................................................................ 16

7.4. ...................................................................................................................... 17

7.5. AHB-APB ................................................................................................................... 18

7.6. PAC - PAC (Peripheral Access Controller) .................................................................................... 19

8. ....................................................................................................... 29 8.1. ............................................................................................................................. 29

8.2. ......................................................................................................................... 30

8.3. ........................................................................................................... 34

Microchip ......................................................................................... 35

.................................................................................................. 35

......................................................................................................... 35

......................................................................................................... 35

Microchip ............................................................... 36

............................................................................................................ 36

.............................................................................................................................. 37


DNV .............................................................................. 37

.............................................................................................. 38


32 ARM

1.

SAM D21L 32 ARM Cortex-M0+ 64 KB 8 KB SRAM 3248 SAM D21L 48 MHz 2.46 CoreMark/MHz HEX

()

SAM D21L 12 (DMA)12 52 I/O 32 / 5 16 /(TC) 3 24 TC (TCC)

TC /()TC 8 16 2 TC 32 TC 3 TC (TCC) 6 (SERCOM) ( USARTUARTSPII2C ( 3.4 MHz)SMBusPMBusLIN ) 18 350 ksps/12 ADC ( 16 )1 10 /350 ksps DAC4 () 2 SWD (Serial Wire Debug)/

/

CPU

SAM D21L 2 ()CPU

SleepWalking CPU ()

//

SWD

SAM D21L (C /)


32 ARM

2.

SAM D21G16L SAM D21ExL

48 32

I/O (GPIO) 38 26

64 KB 64/32 KB

SRAM 8KB 8/4 KB

/(TC) 5 3

TC 1 2 2

/(TCC) 3 3

TCC 1 8/4/2 6/4/2

DMA 12 12

(SERCOM) 6 4

/ (ADC) 18 14

(AC) 4 4

/(DAC) 1 1

(RTC)

RTC 1 1

RTC 1x 32

2x 16

1x 32

2x 16

16 16

CPU 48 MHz

QFN QFN

TQFP

0.432 MHz (XOSC)

32.768 kHz (OSC32K)

32 kHz (OSCULP32K)

8 MHz (OSC8M)

48 MHz (DFLL48M)

96 MHz (FDPLL96M)

12 12

SW

(WDT)


32 ARM

3.

A = L = /PWM

3.1 SAM D21ExL

() SRAM ()

ATSAMD21E15L-MNT 32K 4K 105 QFN32 &

ATSAMD21E15L-MFT 32K 4K 125 QFN32 &

ATSAMD21E15L-AFT 32K 4K 125 TQFP32 &

ATSAMD21E16L-MNT 64K 8K 105 QFN32 &

ATSAMD21E16L-MFT 64K 8K 125 QFN32 &

ATSAMD21E16L-AFT 64K 8K 125 TQFP32 &

3.2 SAM D21GxL

() SRAM ()

ATSAMD21G16L-MUT 64K 8K 85 QFN48 &

ATSAMD21G16L-MNT 64K 8K 105 QFN48 &

3.3 DSU (Device Service Unit) (DID.DEVSEL)SAM D21L DID 0x1001drxx(dr xx)


32 ARM

3-1. SAM D21L ID

DID.DEVSEL ID (DID)

0x000x61

SAMD21E16L 0x62 0x1001143E

SAMD21E15L 0x63 0x1001143F

0x640x86

SAMD21G16L 0x87 0x10011457

0x880xFF

Note: () (DSU.DID.REVISION)


32 ARM

8 x Timer Counter

6 x SERCOM

4.

1. SERCOM /ADC

2. 3 TCC ((WO))

PORT


32 ARM

5. 5.1 SAM D21GxL

5.1.1 QFN48


32 ARM

5.2 SAM D21ExL

5.2.1 QFN32 / TQFP32


32 ARM

6. 6-1. SAM D21L

SRAM SAM D21L


32 ARM

7. 7.1 Cortex M0+

SAM D21L ARMv6 Thumb-2 ISA ARM Cortex-M0+Cortex M0+ Cortex-M0 Cortex-M3 M4 SAM D21L ARM Cortex-M0+ r0p1 http://www.arm.com

7.1.1 Cortex M0+

7-1. Cortex M0+

M0+

032 28

/

SysTick /

012 2

01234 4

Halting Debug /

()

I/O /

/

/

/ / (1)

/8

/

16 32 32

Note: 1.

ARM Cortex-M0+ 2 1 32 AMBA-3 AHB-Lite :

( RAM ) 1 32 I/O : / PORT

7.1.2 Cortex-M0+

SCS (System Control Space) SCS

Cortex-M0+ Technical Reference Manual(www.arm.com) (SysTick)

http://www.arm.com/http://www.arm.com/


32 ARM

NVIC 24 Cortex-M0+ Technical Reference Manual(www.arm.com)

NVIC (Nested Vectored Interrupt Controller) NVIC

NVIC Cortex-M0+

NVIC (Nested Vector Interrupt Controller) Cortex-M0+ Technical Reference Manual (www.arm.com)

SCB (System Control Block) SCB

Cortex-M0+ Devices Generic User Guide(www.arm.com)

MTB (Micro Trace Buffer) CoreSight MTB-M0+ (MTB)Cortex- M0+

MTB (Micro Trace Buffer) CoreSight MTB-M0+ Technical Reference Manual (www.arm.com)

7.1.3 Cortex-M0+

7-2. Cortex-M0+

0xE000E000 SCS (System Control Space)

0xE000E010 (SysTick)

0xE000E100 NVIC (Nested Vectored Interrupt Controller)

0xE000ED00 SCB (System Control Block)

0x41006000 () MTB (Micro Trace Buffer)

7.1.4 I/O

7.1.4.1 AMBA AHB-Lite I/O Cortex-M0+ I/O I/O

7.2 NVIC (Nested Vector Interrupt Controller)

7.2.1

SAM D21L NVIC 4 32 Cortex-M0+ Technical Reference Manual(www.arm.com)

7.2.2

28 1 ( 7-3

http://www.arm.com/http://www.arm.com/http://www.arm.com/http://www.arm.com/http://www.arm.com/


32 ARM

)/(INTFLAG) 1

(INTENSET)1(INTENCLR)1

(OR) 1 NVIC (ISPR/ICPR)(SETPEND/CLRPEND)NVIC NVIC (ISER/ICER SETENA/CLRENA )NVIC IPR0IPR7

7-3.

NVIC EIC NMI - NMI

PM - 0

SYSCTRL - 1

WDT - 2

RTC - 3

EIC - 4

NVMCTRL - 5

DMAC - 6

7

EVSYS - 8

SERCOM0 - 0 9

SERCOM1 - 1 10

SERCOM2 - 2 11

SERCOM3 - 3 12

SERCOM4 - 4 13

SERCOM5 - 5 14

TCC0 - / 0 15

TCC1 - / 1 16

TCC2 - / 2 17

TC3 - / 3 18

TC4 - / 4 19

TC5 - / 5 20

TC6 - / 6 21

TC7 - / 7 22

ADC - / 23


32 ARM

NVIC AC - 24

DAC - / 25

26

27 7.3 Micro Trace

7.3.1

Cortex-M0+ MTB SRAM SRAM CoreSight

7.3.2

MTB Cortex-M0+Cortex-M0+ CoreSight MTB-M0+ MTB MTB MTB SRAM SRAM MTB SRAM SRAM MTB PC MTB 2 32 PC MTB CoreSight MTB-M0+ Technical Reference Manual (MASTER) EN 11(0)/ MTB MASTER CoreSight Cortex-M0+Technical Reference Manual MASTER EN MTB

MTB 0x41006000 CoreSight ROM CoreSight MTB- M0+ Technical Reference Manual MTB 4

POSITION: MASTER: FLOW: WATERMARK AUTOSTOP AUTOHALT BASE: SRAM

MTB SRAM CoreSight MTB-M0+ Technical Reference Manual


32 ARM

7.4

7.4.1

32

7.4.2

7-4.

ID

CM0+ - Cortex M0+ 0

DSU - 1

7-5.

ID

0

AHB-APB A 1

AHB-APB B 2

AHB-APB C 3

7.4.3 SRAM QoS (Quality of Service) RAM

QoS (Quality of Service)RAM RAM RAM QoS 7-6 QoS

7-6. QoS (Quality of Service)

00 DISABLE (no sensitive operation)

01 LOW (Sensitive Bandwidth)

10 MEDIUM (Sensitive Latency)

11 HIGH (Critical Latency)

QoS 0x00 0x01 RAM 1

2 1 QoS 2 SRAM ID ( ID )


32 ARM

MTB QoS 3 DSU QoS 1

CPU QoS 0x41007110/[1:0] 0x0 (DMAC) QoS QOSCTRL

7.5 AHB-APB AHB-APB AHB APB AHBAHB-APB

AHB-APB AMBA APB V2.0 (APB4) ()

:

AHB-APB (CLK_HPBx_AHB)

7-1. APB T0 T1 T2 T3 T0 T1 T2 T3 T4 T5

PCLK PCLK

PADDR

PWRITE

PADDR

PWRITE

PSEL

PENABLE

PWDATA

PREADY

PSEL

PENABLE

PWDATA

PREADY

No wait states Wait states

Addr 1

Data 1

Addr 1

Data 1


32 ARM

7-2. APB T0 T1 T2 T3

T0 T1 T2 T3

T4 T5

PCLK PCLK

PADDR

PWRITE

PADDR

PWRITE

PSEL

PENABLE

PRDATA

PREADY

PSEL

PENABLE

PRDATA

PREADY

No wait states

Wait states

7.6 PAC (Peripheral Access Controller)

7.6.1

AHB-APB 1 PAC PAC

PAC (CLK_PACx_APB)/CLK_PAC0_APB CLK_PAC1_APB CLK_PAC2_APB PAC

--2 I/O (1 1 )(WPCLR)1WPCLR WPSET

(WPSET)1WPCLR WPSET

(WPCLR WPSET)

(CPU )

PAC CPU n WPSET[n]1PAC ()

()(WPSET )

Addr 1

Data 1

Addr 1

Data


32 ARM

7.6.2 8/16/32 32 1/4 (8 ) 1/2 (16 ) 16 1/2 (8 )PAC

7.6.2.1 PAC0

: WPCLR : 0x00 : 0x000000 :

Bit 6 - EIC 0

1

0 1

Bit 5 - RTC 0

1

0 1


32 ARM

Bit 4 - WDT 0

1

0 1

Bit 3 - GCLK 0

1

0 1

Bit 2 - SYSCTRL 0

1

0 1

Bit 1 - PM 0

1

0 1

: WPSET : 0x04 : 0x000000 :


32 ARM

Bit 6 - EIC 0

1

0 1

Bit 5 - RTC 0

1

0 1

Bit 4 - WDT 0

1

0 1

Bit 3 - GCLK 0

1

0 1

Bit 2 - SYSCTRL 0

1

0 1


32 ARM

Bit 1 - PM 0

1

0 1

7.6.2.2 PAC1

: WPCLR : 0x00 : 0x000002 :

Bit 6 - MTB 0

1

0 1

Bit 3 - PORT 0

1


32 ARM

0 1

Bit 2 - NVMCTRL 0

1

0 1

Bit 1 - DSU 0

1

0 1

: WPSET : 0x04 : 0x000002 :

Bit 6 - MTB 0


32 ARM

1

0 1

Bit 3 - PORT 0

1

0 1

Bit 2 - NVMCTRL 0

1

0 1

Bit 1 - DSU 0

1

0 1

7.6.2.3 PAC2

: WPCLR : 0x00 : 0x00800000 :


32 ARM

Bit 18 - DAC 0

1

0 1

Bit 17 - AC 0

1

0 1

Bit 16 - ADC 0

1

0 1

Bit 1112131415 - TC3TC4TC5TC4TC7 0

1

0 1

Bit 8910 - TCCn 0

1

0 1


32 ARM

Bit 1 - EVSYS 0

1

0 1

Bit 0:12:34:56:78:910:11 - SERCOMn 0

1

0 1

: WPSET : 0x04 : 0x00800000 :

Bit 18 - DAC 0

1

0 1


32 ARM

Bit 17 - AC 0

1

0 1

Bit 16 - ADC 0

1

0 1

Bit 1112131415 - TC3TC4TC5TC6TC7 0

1

0 1

Bit 8910 - TCCn 0

1

0 1

0

1

0 1

Bit 1 - EVSYS 0

1

0 1


32 ARM

8.

8.1

8.1.1 8-1

8-1.

JA JC

32 TQFP 64.7 /W 23.1 /W

32 QFN 40.9 /W 15.2 /W

48 QFN 32.0 /W 10.9 /W

8.1.2 TJ ()

1. TJ = TA + (PD x JA)2. TJ = TA + (PD x (HEATSINK + JC))

JA = -(/W) 8-1 JC = -(/W) 8-1 HEATSINK = ()(/W) PD = (W) TA = ()

1 2 TJ ()


32 ARM

8.2

8.2.1 48 QFN

Note:

8-2.

140 mg


32 ARM

8-3.

8-4.

JEDEC MO-220

JESD97 E3

8.2.2 32 TQFP

MSL3


32 ARM

8-5.

8-6.

8-7.

JEDEC MS-026

JESD97 E3

MSL3

100 mg


32 ARM

8.2.3 32 QFN

Note: GND GNDANA

8-8.

8-9.

MSL3

90 mg


32 ARM

8-10.

JEDEC MO-220

JESD97 E3

8.3 J-STD-20

8-11.

(217 ) 3 /s max.

17525 150200

217 60150 s

5 30 s

260

6 /s max.

25 8 min max.

3


32 ARM

Microchip

Microchip (www.microchip.com)

-

- (FAQ) Microchip

- /(/)

Microchip Microchip

Microchip (http://www.microchip.com/)[DESIGN SUPPORT][Product Change Notification]

Microchip

(FAE)

http://www.microchip.com/support

http://www.microchip.com/http://www.microchip.com/http://www.microchip.com/support


32 ARM

A = L = PWM Note:

1. &/

2. http://www.microchip.com/ packaging

Microchip

Microchip Microchip Microchip Microchip Microchip

Microchip Microchip

Microchip Microchip

Microchip

Microchip Microchip

http://www.microchip.com/packaginghttp://www.microchip.com/packaging

32 ARM


MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip Microchip Microchip

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Microchip Microchip AnyRateAVRAVR AVR FreaksBeaconThingsBitCloudCryptoMemoryCryptoRFdsPICFlashFlex flexPWRHeldoJukeBloxKeeLoqKeeLoq KleerLANCheckLINK MDmaXStylusmaXTouchMediaLBmegaAVRMOSTMOST MPLABOptoLyzerPICpicoPowerPICSTARTPIC32 Prochip DesignerQTouchRightTouchSAM-BASpyNICSSTSST SuperFlashtinyAVRUNI/OXMEGA Microchip Technology Incorporated ClockWorks The Embedded Control Solutions Company EtherSynch Hyper Speed ControlHyperLight Load IntelliMOSmTouchPrecision EdgeQuiet-Wire Microchip Technology Incorporated Adjacent Key SuppressionAKSAnalog-for-the-Digital AgeAny CapacitorAnyInAnyOutBodyCom chipKIT chipKIT CodeGuard CryptoAuthentication CryptoCompanion CryptoController dsPICDEM dsPICDEM.net Dynamic Average Matching DAM ECAN EtherGREENIn-Circuit Serial ProgrammingICSPInter-Chip ConnectivityJitterBlockerKleerNetKleerNet MindiMiWimotorBenchMPASMMPFMPLAB Certified MPLIBMPLINKMultiTRAKNetDetachOmniscient Code GenerationPICDEMPICDEM.netPICkitPICtailPureSiliconQMatrixRightTouch REAL ICERipple BlockerSAM-ICESerial Quad I/OSMART-I.S.SQISuperSwitcherSuperSwitcher IITotal EnduranceTSHARCUSBCheckVariSenseViewSpanWiperLockWireless DNAZENA Microchip Technology Incorporated SQTP Microchip Technology Incorporated Silicon Storage Technology Microchip Technology Inc. GestIC Microchip Technology Inc. Microchip Technology Germany II GmbH & Co. KG 2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

ISBN: 978-1-5224-2057-6

DNV

ISO/TS 16949 Microchip Chandler Tempe ()Gresham () ISO/TS-16949:2009 Microchip PIC MCU dsPIC DSCsKEELOQ EEPROM Microchip ISO 9001:2000


/ /

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1. 2. 3. 3.1 SAM D21ExL3.2 SAM D21GxL3.3 3-1. SAM D21LID

4. 5. 5.1 SAM D21GxL5.1.1 QFN48

5.2 SAM D21ExL5.2.1 QFN32 / TQFP32

6. 6-1. SAM D21L

7. 7.1 Cortex M0+7.1.1 Cortex M0+7-1. Cortex M0+

7.1.2 Cortex-M0+7.1.3 Cortex-M0+7-2. Cortex-M0+

7.1.4 I/O

7.2 NVIC (Nested Vector Interrupt Controller)7.2.1 7.2.2 7-3.

7.3 Micro Trace7.3.1 7.3.2

7.4 7.4.1 7.4.2 7-4. 7-5.

7.4.3 SRAM QoS (Quality of Service)7-6. QoS (Quality of Service)

7.5 AHB-APB7-1. APB7-2. APB

7.6 PAC (Peripheral Access Controller)7.6.1 7.6.2

8. 8.1 8.1.1 8-1.

8.1.2

8.2 8.2.1 48QFN8-2. 8-3. 8-4.

8.2.2 32TQFP8-5. 8-6.8-7.

8.2.3 32QFN8-8.8-9.8-10.

8.3 8-11.

MicrochipMicrochipDNV

Documents

SAM D21EL / SAM D21GL Summary - Microchip …ww1.microchip.com/downloads/jp/DeviceDoc/40001885A_JP.pdf · SAM D21EL / SAM D21GL Summary Author: ... Event System; DMA Controller; Timer