RUIN Rapid Universal INterface

Institute of Experimental and Applied PhysicsCzech Technical University in Prague

11th December 2007

Michal Platkevič

RUIN RUIN Rapid Universal INterfaceRapid Universal INterface

for Medipix

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IEAP – CTU Prague11th December 2007

Michal Platkevič

Work in UTEFWork in UTEFApril 2006 – half-time

November 2006 – full-time

Work:RUIN – Rapid Universal INterfacePCB for stepper motors controlPrototype of USB1 modification for TimepixSpectroscopic modulATLAS – Medipix wirringMeasurement on PALSMeasurement of slow neutrons in ILL

Diploma thesis (June 2007): Signal processor controlled USB2.0 interface for Medipix2 detector

Presentations:USB2.0 Interface Status (CERN)

Signal processor controlled USB2.0 interface for Medipix2 detector (IWORID 9)Status of USB interfaces (MidSweden University)

Medipix /ATLAS – wiring (CERN)Medipix in an extremely hostile environment (CERN)USB2.0 interface for Medipix2 device (CERN)

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Michal Platkevič

(Si)

Amplifier

Compa-rator

Counter: Particle count

000001

Pixel electronics

Pixel electronics

Pixel electronics

+

Bias Voltage

Th

resh

old

leve

l

Threshold level above electronic noise No false counting.

Digital integration (counting) No dark current.

Unlimited dynamic range and exposure time.

Detected count obeys poissonian distribution

Planar pixellated detector (Si, GaAs, CdTe) is bump-bonded to read-out chip

Ionizing particle creates a charge in a sensitive volume

The charge is amplified and compared with a threshold

Digital counter is incremented.

Medipix2 detectorMedipix2 detectorMEDical Imaging PIXel detector of 2nd generation

Pixels: 256 x 256Pixel size: 55 x 55 m2

Area: 1.5 x 1.5 cm2

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Medipix – data read-outMedipix – data read-outThe serial readout uses a LVDS port to shift out all the matrix data.

In readout mode the 14-bit shift register of each pixel is connected to the next one forming a 3584-bit shift register.

Communication between the pixel matrix and the IO logic is carried out through the 256-bit FSR.

The number of clocks needed in order to read one chip are 917512 (256x256x14+8).

External clock have to be used to shift the data from pixel to pixel.

……

……

……

……

……

……

256 pixels

25

6

pix

els

256-bit FSR256-bit FSR

bit bit bit bit bit

bit bit bit bit bit

bit bit bit bit bit

bit bit bit bit bit

… …bit bit bit bit bit bit

LVDS InputLVDS Input

LVDS OutputLVDS

OutputIO

LogicIO

Logic 32-bit CMOS Output32-bit CMOS Output

Facu

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f N

ucle

ar

Scie

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IEAP – CTU PragueIEAP – CTU Prague

New InterfaceNew Interface - - Design Design strategy strategyNew interface design puts emphasis on:•Speed of data read-out. (maximum speed possibility of the Medipix serial read-out: currently 200 MHz) •Support for all chips of MPX family

USB2.0 EthernetUSB2.0 Ethernet

DSPDSP Medipix chipboardMedipix

chipboard

MemoryMemory

Power suppliesPower

supplies

FPGAFPGA

PCand

Power supply

PCand

Power supplyStrategy :

Conecting with PCUSB2.0 - transfer rate of 480 Mb/s

1Gb/s Ethernet

Usage of the digital signal processorHigh data throughput

High computational performance (up to 8000 mips), even sophisticated data processing can be done here (threshold equalization, flat field correction, cluster analysis, data compression …)

Built in management of large memory

Usage of the FPGA Hardware de-serialization of the serial data - decrease a processor load

I/O - LVDS, CMOS

Flexibility – possibility to change functionality without need of hardware modification

New interfaceNew interface

11th December 2007Michal Platkevič

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Principle of Data Read-outPrinciple of Data Read-outThe serial data from the Medipix are shifted to fast shift registers

When the registers are filled up, the parallel data are loaded to the latch.

DSP reads the data from the latch via the data bus

Individual chips of multichip assembly are read out simultaneously.

Shift register is arranged as a 4 eight bit segments. Each segment can be fed from separate MPX chip.

Usage of multiple latches in form of FIFO could be advantageous

32 bits32 bitsM

emory

Mem

oryPLL clock

generator + control logic

PLL clock generator + control logic

USB 2.0USB 2.0

8 bits8 bits 8 bits8 bits 8 bits8 bits 8 bits8 bits

LATCHLATCH

32 bits32 bitsM

emory

Mem

oryPLL clock



USB 2.0USB 2.0


LATCHLATCH

32 bits32 bitsM

emory

Mem

oryPLL clock



USB 2.0USB 2.0


LATCHLATCH

32 bits32 bitsM

emory

Mem

oryPLL clock



USB 2.0USB 2.0


LATCHLATCH

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StatusStatus

• Current prototype fully tested with MXR chip (up to 48 MHz)• Schematic design is finishing• PCB design will be ordered soon …

DSP evaluation

board

FPGA evaluation

board

Power supply for Medipix

Medipix

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Interface LayoutInterface Layout

PowerUSB

HeaderDSP FPGA

Flash

Memory DDR2

RJ45

Cypress

DAC8x

Memory DDR2

ADC8x

Ethernet

Power

Power

Connectors• Power• Mini USB• General purpose

20 pin header• Ethernet

Connectors• Power• Mini USB• General purpose

20 pin header• Ethernet

Power supply PCB• For Medipix• For interface• Power connector

Power supply PCB• For Medipix• For interface• Power connector

Logic• DSP (TI)• FPGA (Lattice)• USB (Cypress)• Ethernet (Intel)• DDR2 memory• Flash memory

Logic• DSP (TI)• FPGA (Lattice)• USB (Cypress)• Ethernet (Intel)• DDR2 memory• Flash memory

Inner Connectors• JTAG for DSP• FPGA programming• General purpose• Power• Medipix• Power for Medipix

Inner Connectors• JTAG for DSP• FPGA programming• General purpose• Power• Medipix• Power for Medipix

Changeable Medipix

chipboard adapter

Changeable Medipix

chipboard adapter

To be more flexible we decided to use modular system

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Michal Platkevič

Interface LayoutInterface Layout

DSPFPGA

Ethernet

Flash

Memory DDR2

Memory DDR2

RJ45

USBCypre

ss

ADC8x

DAC8x

Power

6 cm

14 cm

Power

Power

Changeable chipboard adapter is recognized automatically and LVDS and CMOS pins of FPGA are configured.

All signals from Medipix go via the FPGA (Lattice XP) with configurable inputs outputs – LVDS, CMOS

Debugging

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Supported DetectorsSupported Detectors

Detectors

• Medipix2, Medipix MXR

• Medipix Quad (daisy chain or separately)

• Timepix

• … Medipix3

Read-out:

• Serial

• Parallel

Connecting:

• Directly/via the cable

• CMOS/LVDS

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unused

unused

CMOS 16b

LVDS 8pairs

Data read-out and controlData read-out and control

Bank 2

Bank 3

Bank 6

Bank 7

FPGA

Medipix2, MXR, Timepix- 100 fps at 100 MHz

Serial data

Control

LVDS - 6 pairs• Enable_OUT• Enable_IN• Data_OUT• Data_IN• Clk_IN• Clk_OUT

CMOS• 10 control bits



DSP data bus32 bits x 133 MHz

4.256 Gb/s

Medipix chipboard

Adapter board

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Michal Platkevič

unused

unused

CMOS 16b

LVDS 8pairs


Standard Quad- 25 fps at 100 MHz

Serial data

Control





Bank 2

Bank 3

Bank 6

Bank 7

FPGA


4.256 Gb/s

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Michal Platkevič

LVDS 8pairs

LVDS 8pairs

CMOS 16b

LVDS 8pairs

Data read-out and controlData read-out and controlQuad – each chip read separately 100 fps at 100 MHz

Serial data

LVDS - 24 pairs• 4 x Enable_OUT• 4 x Enable_IN• 4 x Data_IN• 4 x Data_OUT• 4 x Clk_IN• 4 x Clk_OUT




Control

Bank 2

Bank 3

Bank 6

Bank 7

FPGA


4.256 Gb/sSerial data

Serial data

Serial data

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Michal Platkevič

CMOS 16b

CMOS 16b

CMOS 16b

LVDS 8pairs


Medipix2, MXR, Timepix-parallel read-out-3200 fps at 100 MHz

Serial data

Parallel data32b

LVDS - 5 pairs• Enable_OUT• Enable_IN• Data_IN• Clk_IN• Clk_OUT

CMOS• 10 control bits• Parallel data

LVDS - 5 pairs• Enable_OUT• Enable_IN• Data_IN• Clk_IN• Clk_OUT

CMOS• 10 control bits• Parallel data

Control

Bank 2

Bank 3

Bank 6

Bank 7

FPGA


4.256 Gb/s

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Michal Platkevič

LVDS 8pairs

LVDS 8pairs

CMOS 16b

LVDS 8pairs

Data read-out and controlData read-out and control4 x standard Quad25 fps at 100 MHz

Control





Bank 2

Bank 3

Bank 6

Bank 7

FPGA


4.256 Gb/sSerial data

Serial data

Serial data

Serial data

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Michal Platkevič

Finding nameFinding name

• Rapid

• Universal

• INterface

RUINRUIN

RUIN

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Michal Platkevič

Thank you for your attention!Thank you for your attention!

Documents

RUIN Rapid Universal INterface