Robust asynchronous-reset architecture forscan coverageSandeep JainNikila Krishna, - April 15, 2015

Digital integrated circuits typically use asynchronous set/resets to set the value of memory elements(flip-flops) without depending on any clock pulses. This logic, however, requires special handlingduring scan based testing of the device. Also, the logic associated with asynchronous set/reset mayconstitute 2-4% of the total faults in a design. With growing focus on high test-coverage and zeroDPPM, especially for critical applications like automotive and medical devices, it is important tothoroughly test such faults to ensure overall system robustness.

This article presents various scenarios, and the test architecture to robustly detect scan coverage –including potential race conditions – on asynchronous paths.

The salient features of this architecture are:

Targets coverage on internally generated set and reset logic●

Avoids glitches due to reconvergence on scan-enable and async-SE signals●

Reuses scan-in pin during capture to delay the async-SE trigger●

1. Coverage Loss with Test-mode Gating

A design can have reset logic generated from combinational decoding of other sequential cells, inaddition to a top-level reset control. During scan-mode, if this logic gets random scan-data, the sinkflop can get reset thus corrupting the scan shift data. To avoid this situation, the combinational logicis gated-off with a static signal (testmode/scanmode) to feed a constant data during shift as well ascapture.

Figure 1‑1 Static Gating of Internally Generated Reset

However, using a static signal blocks the observe cone of the combinational logic, leading tocoverage loss, as seen in Figure 1‑1.

Figure 1‑2 Bypassing Internally Generated Reset with External Pin

To recover this loss of coverage, we typically bypass the internal reset with external pin-reset. Thebypassing signal is toggled in one of the scan-modes to allow functional path to propagate to scan-flops as shown in Figure 1‑2.

2. Coverage Recovery with Scan-Enable Logic

Figure 2‑1 Async_SE Generated with a Static Bit and an External Pin SE

The coverage loss on functional reset can be recovered, if the gating logic is enabled only duringshift. During capture, the functional values take control of the flop-reset pin.

The scan-enable signal (denoting the shift or capture phase) is gated with a static Test DataRegister(TDR) bit, so that this functionality is enabled only in a specific ATPG mode (when resetcoverage is targeted). The TDR bits needs to be kept out of scan with clock/reset gated, so that thebit retains its value during entire scan operation.

Mode Details ConfigurationMode-1 ATPG without targetting reset faults TDR_bit=1, RESET=1Mode-2 ATPG targetting reset faults TDR_bit=1,

RESET=0(capture)Mode-3 ATPG targetting functional reset cone

coverageTDR_bit=0, RESET=X

Table 2‑1 Modes of Operation with Async-SE

Figure 2‑2 Waveforms for Async_SE Operation

The waveforms in 2-2 shows a window after the clock pulses and before asserting SE, where allglitches in the combinations logic has settled before the logic is made transparent for flop reset pin.

3. Glitches Due to Reconvergence on Scan-enable Cone

Figure 3‑1 Async-SE updated for SE Reconvergence

The async-SE logic discussed earlier can still create glitches during capture, if there is anyreconvergence on SE pin, as shown in Figure 2-4(a). SE is typically used to control various pin-muxing and other muxing logic which can get triggered simultaneously, the moment SE is asserted.

To avoid this issue, another qualifying signal is added which allows any transition excited by SE-assertion to settle down, before making the functional-reset cone transparent. In order to avoidanother top-level pin for this functionality, we have reused 1 of the scan-in pins which are unusedduring the capture phase.

Figure 3‑2 Waveforms for Async_SE after adding Another Qualifier Pin

The waveforms in Figure 3‑2 shows a 2-stage approach that allows any glitch arising from clock-pulsing or SE-assertion to settle down before the logic is made transparent for flop reset pin.

4. Glitches Due to Reconvergence on Async-SE Cone

Figure 4‑1 Reset-Ripples Created due to Same Async-SE controlling Cascaded Resets

In case the output of a flop driven by async_SE feeds the functional reset cone of another flop, therecan be ripple effect when async-SE is asserted. The 1st flop would get a reset, once async-SE isasserted. This would make the functional-reset logic of 2nd flop to be re-evaluated and update theoutput of 2nd flop (this behavior was not expected though, during pattern generation).

As the ATPG tools work on a static view of the design, these issues are not detectable during patterngeneration. This can lead to simulation failures when actual timing data is applied. Sometimes theripple effect is seen to manifest only at silicon, while the glitch was not seen during timingsimulations.

Figure 4‑2 Async-SE Split within TCU Based on 1-cold Decoded Testpoints

In order to avoid the ripple-reset scenario, the async-SE logic is split so that a unique async-SEsignal is generated for cascaded reset cases. The async-SE is gated by testpoints which are 1-colddecoded, so that only 1 of the flops are at ‘0’, while others are at logic ‘1’.

5. Glitches Due to Reconvergence on Reset Mux

There can be cases where we get a glitch on the reset pin even after taking care of thereconvergence in the SE and Async_SE pins. These glitches can arise due to reconvergence in thereset-mux itself, if the logic gets broken in combinational gates during synthesis

Figure 5‑1 Reset Mux broken into Combinational Gates Resulting in Glitches

In order to avoid these glitches, we need to ensure that the reset mux gets preserved as a mux andis never broken into AND-OR gates.

It is recommended that the reset muxing is always done using a mux-instantiation code in the RTLrather than a combinational statement. The synthesis team can add-in rules to ensure that thesemuxes are further preserved as mux during the entire Synthesis/BE cycle.

X assign muxed_rst = (async_se) ? test_rst : func_rst;

a dft_reset_mux mux_inst (.a(func_rst), .b(test_rst), .sel(async_se), .x(muxed_rst) );

As the mux is a single library cell, there will not be any glitch inside the mux logic. There should beno special requirement to use any balanced or glitchless muxes for reset muxing.