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PROCESSORS FOR THE CONNECTED WORLDYour application is unique, so why isn’t your processor?
RISC-V PROCESSOR VERIFICATIONChallenges and Strategies
RISC-V ISA
Free to use, modern and open instruction set
architecture (ISA)
Originally designed to support research and
education, now standard for industry
implementations under RISC-V Foundation
No patents
CODIX PROCESSOR IP CORES
RISC-V VERIFICATION CHALLENGES
1 RISC-V ISA standard many RISC-V HW architecture variants:
Base is only integer instruction set (" I ")
Can be enhanced by extensions: integer multiplication and division ("M"), atomic instructions for handling real-time concurrency ("A"), IEEE floating point ("F") with double-precision ("D") and quad-precision ("Q")
Can have compressed instructions (“C")
Can have different size of the registers, i.e. 32 or 64 bits.
We do not verify only 1 processor but many of its variants with enabled/disabled extensions!
2 FACTORS FOR MINIMIZING COST AND RISC
1. Automated generation of the processor, its SDK and its UVM-
based verification environment.
2. Verification strategies favoring reuse.
VERIFICATION AUTOMATION
UNIQUE AUTOMATION TECHNOLOGY
Processor ModelingSoftware analysis
SDK Synthesis RTL Synthesis Verification
Codix
Microarchitecture
Codix Cycle Accurate
ModelsCodix RTL ModelsCA Simulator, Profiler, Debugger
Application(s)/Programs(s)
C/C++ Compiler
Assembler
Linker
IA Simulator, Profiler, DebuggerCodix Instruction
Accurate Models
Codix CodAL Models
Codix Instruction Set
AUTOMATION VS. VERIFICATION
Fewer bugs - once the tool generating RTL is debugged, then certain
types of bugs no longer occur.
Verification environment generation –from the high-level IA and CA
CodAL models.
Reference model updates - as well as new RTL (which serves in
verification as DUT), reference models from IA model in C/C++ can
be generated.
Test generation - random assembler programs generator tool
integrated in Codasip Studio.
UNIQUE AUTOMATION TECHNOLOGY
Processor ModelingSoftware analysis
SDK Synthesis RTL Synthesis Verification
Codix
Microarchitecture
Codix Cycle Accurate
ModelsCodix RTL ModelsCA Simulator, Profiler, Debugger
Application(s)/Programs(s)
C/C++ Compiler
Assembler
Linker
IA Simulator, Profiler, DebuggerCodix Instruction
Accurate Models
Codix CodAL Models
Codix Instruction SetReference Models
UVM
Verification
AUTOMATION: FEWER BUGS
Many bugs that can be introduced by writing RTL manually can be
avoided with generated RTL:
‘Fat finger’ errors
Logical errors – interrupts handling, decoding logic, bit-width conversions,
pipeline control, ALU operations, write-back and fetch logic, etc.
Connectivity errors –instantiation and wiring of components.
Readability of the generated code – links to CodAL make life easier
RTL generator has been made robust by years of use
AUTOMATION: UVM GENERATION
AUTOMATION: TESTS
Generated ISA tests can cover most of the processor functionality
SUMMARY
Automation in generating RTL, UVM verification environments,
reference models and tests (programs) can rapidly improve
productivity in the development of RISC-V cores.
We do not spend a valuable time on code writing but rather on real
debugging and exploring corner cases!
STRATEGIES FAVORING
REUSE
REUSE OF NON-GENERATED PARTS
Following items should be reusable across RISC-V variants:
Test constraints (restrictions to random assembler generator)
Directed tests (hand-written tests that target specific usually
micro-architectural features)
Assertions
Coverage points
EXAMPLE: FULL DESIGN
Bk5 model from Codasip64b+I+M+F+C
RTL, reference model, UVM verification environment,
ISA tests
GENERATE
Directed tests, assertions, coverage points
MISMATCHES FOUND, MODEL MUST BE FIXED
RESULTS OK BUT COVERAGE NOT 100%
RESULTS OK,COVERAGE 100%VERIFICATION
FINISHED
EXAMPLE: SUB-DESIGN REUSE
Bk5 sub-model64b+I+M
RTL, reference model, UVM verification environment,
ISA tests
GENERATE
COPY directed tests,
assertions, coverage points from full design
RESULTS OK BUT COVERAGE NOT 100%
RESULTS OK,COVERAGE 100%VERIFICATION
FINISHED
MISMATCHES FOUND, MODEL MUST BE FIXED (not expected, everything is debugged)
EXAMPLE: NEW EXTENSION
Bk5 extended model
64b+I+M+F+C+?
RTL, reference model, UVM verification environment,
ISA tests
GENERATE
COPY directed tests,
assertions, coverage points
from full design + add newconnected to extension
MISMATCHES FOUND, MODEL MUST BE FIXED (only extension-specific parts)
RESULTS OK BUT COVERAGE NOT 100%
RESULTS OK,COVERAGE 100%VERIFICATION
FINISHED
SUMMARY
Automation in generating RTL, UVM verification environments,
reference models and tests (programs) can rapidly improve
productivity in the development of RISC-V cores.
We do not spend a valuable time on code writing but rather on real
debugging and exploring corner cases!
When verifying a simpler variant of a most complex RISC-V core or
when adding a user-extension, we can highly reuse existing manually
written parts of the verification environment.
Thank you for your attention!
www.codasip.com
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