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RECENT PROGRESS IN 3D/MULTILAYER MMIC TECHNOLOGY

RECENT PROGRESS IN 3D/MULTILAYER MMIC TECHNOLOGY

Kenjiro NISHIKAWA and Ichihiko TOYODA*

NTT Network Innovation Labs. *NTT Electronics Corporation

1-1 Hikari-no-oka, Yokosuka, Kanagawa, 239-0847 Japan

Tel: +81-468-59-3464, Fax: +81-468-59-2106, [email protected]

Abstract

This paper focuses on the recent progress in 3D/multilayer MMIC technology to assess future trends in MMICs and their applications. Highly integrated multifunctional MMICs and cost-effective high performance MMICs using 3D/multilayer structure have been proposed by several organizations recently. This paper briefly summarizes these approaches. The masterslice 3DMMIC technology developed at NTT Laboratories and its applications are then described.

1. Introduction

The demands placed on wireless communication services are increasing steadily, especially with regard to higher data rates. In the coming 21st century, many wireless communication services are expected to grow rapidly to support the growth in multimedia. The services include broadband wireless access systems called “last mile” (MMDS, LMDS, LMCS, and MVDS)[1], point-to-point digital radio links[2], satellite communication systems (VSAT and DBS)[3], wireless local area network (WLAN), and intelligent transportation systems (automotive radar and ETC)[4]. These systems and services are being, deployed in the several-gigahertz to millimeter-wave band and require MMICs that are cost effective and quick to reach the market; i.e., quick production and distribution. However, the cost of current MMICs is excessive due to low integration levels, complex design procedures, and high risks. Furthermore, the development turn-around-time (TAT) of MMICs is very long because the semiconductor fabrication process takes several months. The three-dimensional (3D) MMIC technology developed at NTT Laboratories has gone a long way toward resolving these problems[5]-[9]. The masterslice 3DMMIC technology, which is an effective extension of the 3DMMIC technology, offers a semi-custom MMIC and reduces the development time of multifunctional MMICs[6],[7].

This paper focuses on the recent progress in 3D/multilayer MMIC technology to discuss future trends of MMICs and their applications. Many approaches using 3D/multilayer structure is briefly summarized. Then the masterslice 3DMMIC technology developed at NTT Laboratories and its applications are described.

2. Recent developed thin-film multilayer technology

The thin-film multilayer technology very effectively realizes miniaturization and high integration levels, resulting in great cost reductions. This technology also isolates passive components from the conductive Si wafers, resulting in high frequency Si ICs. We have reported the polyimide-based masterslice 3DMMIC technology on GaAs and Si substrates for S-band to V-band use[5]-[7]. We have also demonstrated the BCB-based 3DMMIC technology [8], which offers greatly reduced fabricated TAT and can be applied to InP devices due to its low fabrication temperature and short process time. Table 1 summarizes recently reported thin-film multilayer IC technologies. There are two trends. One is the focus on miniaturization and high integration levels. The other target is high Q on-chip inductors (or low loss passive circuits) integrated on standard Si wafers. Both goals will achieve high performance microwave/RF ICs at much lower costs. The thin-film multilayer technology has become more popular due to its great potential in realizing cost-effective MMICs.

FET

MIM

cap.

R

semiconductor wafer

FET

MIM

cap.

R

polyimide

2nd-level ground metal

2.5 µm

X 4

3. NTT Masterslice 3DMMIC technology

1 X 2 mm

1.5 X 2 mm

2 X 2 mm

1 X 1.5 mm

1.5 X 1.5 mm

2 X 1.5 mm

1 X 1 mm

1.5 X 1 mm

2 X 1 mm

The masterslice 3DMMIC technology provides a semi-custom MMIC similar to a gate-array LSI and effectively reduces the MMIC development TAT. Figure 1 shows the basic structure of the masterslice 3DMMIC. Transistors, resistors, and lower electrodes of MIM capacitors are formed on the substrate and arranged in a matrix in order to construct a footprint of the masterslice MMICs. This footprint is called the “master array”. The second-level ground metal is formed on top of the passivation film and selectively covers most of the wafer surface. Four layers of thin polyimide films and Au metals are stacked on the second-level metal in order to form the 3D passive structure. Since the ground metal covers unused devices and shunt capacitors, there is enough space to create three-dimensional transmission lines on it. This structure offers several advanced features. Miniature transmission lines and structure stacking effectively reduces the circuit area. The structure also forms a multilayer broadside coupler, which provides tight (3dB) and broadband coupling in a small area. The coupler can be used to create miniature passive circuits, such as a quadrature hybrid and a balun, which usually occupy large areas using the conventional two-dimensional structure. Another feature of the new structure is its simple circuit design. Circuit designs based on the structure are free from parasitic loss because of the narrow strip conductor width and the thin polyimide film thickness. The distance between adjacent line segments of 3h (h: distance between strip conductor and ground plane of a transmission line) is wide enough to practically eliminate the undesired coupling effect. The inductance of each tiny via is also negligible. Therefore, 3DMMIC designs flow straight from circuit schematic to layout, while conventional 2DMMIC designs require frequent iterations layout to schematic, in order to achieve the minimum chip area. As a result, each function block, such as amplifiers and mixers, can be easily integrated to yield a multifunctional MMIC chip.

400

W

100

W

200

W

2 k

W

1 k

W

50 µm

FET

C

C

C

RF

IF

LO

RF front-

end amp.

2-stage

LO amp.

mixer

Figure 2 shows top views of some of the master arrays provided by the NEL 3DM300 foundry service. Each master array consists of identical unit cells. For instance, the largest master array is 2 ( 2 mm and includes 18 unit cells; the smallest is 1 ( 1 mm and includes two unit cells. Figure 3 shows details of the unit cell. It includes four 50-(m FETS, four 100-( resistors, two 200-( resistors, two 400-( resistors, four 1-k( resistors, two 2-k( resistors, and the lower electrodes of three MIM capacitors. If some of the FETs are connected, 50-, 100-, 150-, and 200-(m FETs and diodes become available. Serial and/or parallel connection of the resistors is possible. The area of the upper metal determines the capacitance of the MIM capacitors. Higher capacitance is provided by the parallel connection of the capacitors. These master arrays allow us to develop circuits of different integration levels, such as single-function and multifunction circuits, on a single wafer.

4. Application of the Masterslice 3DMMIC

4.1 Quick development

We designed a down-converter, an amplifier, and a mixer using the above-mentioned master arrays

RF front-end amp

.

mixer

2-stage LO

amp

.

[7]. The amplifier and mixer are miniature MMICs in themselves. Furthermore, because they are laid out on the same footprint (identical unit cells), each circuit can be stored as a component in a function block library and easily integrated in other multifunctional MMICs such as a down-converter. This is the most significant innovation of the masterslice 3DMMIC technology. Figure 4 shows a block diagram and a microphotograph of a recently developed prototype down-converter. It consists of a two-stage LO amplifier, an RF front-end amplifier, and a single-end mixer. The amplifier and mixer, designed using a small master array, are placed on a 2 ( 2-mm master array. Since there are extra unit cells on the master array as shown in Fig. 4(b), it is easy to add more functions to the chip; for instance, amplifiers for increasing conversion gain or lowering LO power, and mixers for balanced or image-rejection configurations. Circuit design and fabrication conventionally require one or two months and two or three months, respectively. The down-converter was designed around well-established function blocks. The design procedure is very fast: only one or two weeks. Highly integrated multifunctional MMICs can thus be easily and quickly produced by using well-established single-function circuits and prefabricated masterslice wafers.

4.2 Cost-effective MMIC development

Fig. 5 shows the methodology proposed for MMIC development based on the 3D/multilayer MMIC process [9]. To reduce the process cost and risk, this methodology divides the MMIC fabrication process into the device process and the metal patterning process. This means each manufacturer can focus on his own area of specialized process technology and designers can select the most suitable combination of device process and 3D/multilayer process to match the latest consumer demand. The proposed methodology offers the designers excellent flexibility in choosing the device and patterning processes that suit their application. This approach means that designers lead MMIC development, while the conventional method allows the process group to assert leadership. To encourage the adoption of the proposed approach, several issues, such as the interface and guarantees of device performance, must be resolved. Table 2 summarizes the variation in key RF parameters of a 0.15-(m GaAs pHEMT [26] fabricated through the cooperation of Matsushita/Panasonic and NTT Electronics. The most substantial variation occurs in device internode capacitance, Cds while the difference of Cgd (Cgs) is small due to existence of the SiO2 film between drain (source) and gate electrode established in the ordinary device process [26]. The other variations are smaller than the standard deviation in fabrication uniformity. A V-band balanced doubler (5-dBm output with more than 35-dB fundamental signal suppression at 31.5 to 37.5 GHz) [27] and a wideband LNA (more than 10-dB gain and less than 2-dB NF at 0.8 to 5.8 GHz) shown in Fig. 6 have been fabricated using the proposed approach.

5. Conclusion

This paper shows recent progress in 3D/multilayer MMIC technology and details our masterslice 3DMMIC technology. The 3D/multilayer MMIC technology is considered to be essential in achieving low cost microwave/millimeter-wave MMICs and equipment. The masterslice 3DMMIC technology, developed by NTT, has great potential in realizing cost-effective, highly integrated MMICs.

Acknowledgement

The authors would like to thank Drs. H. Mizuno, K. Araki, K. Asai, and Y. Imai for their encouragement. They would also like to thank their many colleagues at NTT Laboratories and NTT Electronics Corporation.

References

[1] T. Whitaker, et al., “GaAs MMICs go the last mile,” Compound Semiconductor, Fall II, pp. 22-30, 1998.

[2] H. H. Meinel, “The market for short-haul line-of-sight millimeterwave transmission links,” in 1996 IEEE MTT-S International Microwave Symposium Dig., pp. 487-489, June 1996.

[3] B. A. Pontano, “Satellite Communications: Services, Systems & Technologies,” in 1998 IEEE MTT-S International Microwave Symposium Dig., pp. 1-4, June 1998.

[4] R. Dixit, “Microwave and Millimeter-wave Applications in Automotive Electronics,” in 1996 IEEE MTT-S International Microwave Symposium Dig., pp. 31-33, June 1996.

[5] I. Toyoda, et al., “Highly Integrated Three-dimensional MMIC Single-chip Receiver and Transmitter,” IEEE Trans. Microwave Theory Tech., vol. 44, no. 12, pp. 2431-2437, Dec. 1996.

[6] I. Toyoda, et al., “Three-dimensional Masterslice MMIC on Si Substrate,” IEEE Trans. Microwave Theory Tech., vol. 45, no. 12, pp. 2524-2529, Dec. 1997.

[7] I. Toyoda, et al., “Quick Development of Multifunctional MMICs by Using Three-Dimensional Masterslice MMIC Technology,” IEICE Trans. Electron., vol. E82-C, no. 11, pp. 1951-1959, Nov. 1999.

[8] K. Nishikawa, et al., “A Compact V-band 3-D MMIC Single-chip Down-converter Using Photosensitive BCB Dielectric Film,” IEEE Trans. Microwave Theory Tech., vol. 47, no. 12, pp. 2512-2518, Dec. 1999.

[9] K. Kamogawa, et al., “New Methodology for Microwave/Millimeter-wave MMIC Development,” in 2000 IEEE MTT-S International Microwave Symposium Dig., pp.1913-1916, June 2000.

[10] K. Saito, et al., “A Thick-Cu Process for Add-on Interconnections Using Photosensitive Varnish for Thick Interlayer Dielectric,” in 2000 Int. Interconnect Technology Conference Dig., pp. 123-125, 2000.

[11] H. Q. Tserng, et al., “Embedded transmission- Line (ETL) MMIC for Low-cost High-density Wireless Communication Applications,” IEEE Trans. Microwave Theory Tech., vol. 45, no. 12, pp. 2540-2548, Dec. 1997.

[12] N. Ono, et al., “60-GHz-band Monolithic HEMT Amplifiers Using BCB Thin Film Layers on GaAs Substrate,” in 1998 Asia-Pacific Microwave Conf. Proc., pp. 567-570, Dec. 1998.

[13] H. Sakai, et al., ”A Novel Millimeter-wave IC on Si Substrate Using Flip-chip Bonding Technology,” in 1994 IEEE MTT-S International Microwave Symposium Dig., pp. 1763-1766, June 1994.

[14] H. Sakai, et al., ”A Millimeter-wave Flip-chip IC Using Micro-bump Bonding Technology,” in 1996 IEEE ISSCC Digest of Technical Paper, pp. 408-409, Feb. 1996.

[15] K. Takahashi, et al., ”An Advanced Millimeter- wave Flip-chip IC Integrating Different Kinds of Active Devices,” in 1996 IEEE MTT-S International Microwave Symposium Dig., pp. 1619-1622, June 1996.

[16] H. Yano, et al., “Ku-band Si MOSFET Monolithic Amplifiers With Low-loss On-chip Matching Networks,” in 1999 IEEE RFIC Symposium Dig., pp. 127-130, June 1999.

[17] J. Kim, et al., ” Millimeter-wave Silicon MMIC Interconnect and Coupler Using Multilayer Polyimide Technology,” IEEE Trans. Microwave Theory Tech., vol. 48, no. 9, pp. 1482-1487, Sept. 2000.

[18] L. Larson, et al., “Si/SiGe HBT Technology for Low-cost Monolithic Microwave Integrated Circuits,” in 1996 IEEE ISSCC Digest of Technical Paper, pp. 80-81, Feb. 1996.

[19] M. Case, “SiGe MMICs and Flip-chip MICs for Low-cost Microwave Systems,” in 1997 IEEE RFIC Symposium Dig., pp. 117-120, June 1997.

[20] R. Volant, et al., “Fabrication of High Frequency Passives on BiCMOS Silicon Substrate,” in 2000 IEEE MTT-S International Microwave Symposium Dig., pp.209-212, June 2000.

[21] J. Burghartz, et al., “Integrated RF and Microwave Components in BiCMOS Technology,” IEEE Trans. Electron Devices, vol. 43, no. 9, pp. 1559-1570, Sept. 1996.

[22] R. Groves, et al., “Temperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-germanium/BiCMOS Technology,” IEEE Journal of Solid-state Circuits, vol. 32, no.9, pp. 1455-1459, Sept. 1997.

[23] B. Kim, et al., “Monolithic Planar RF Inductor and Waveguide Structures on Silicon with Performance Comparable to those in GaAs MMIC,” in Tech. Dig. Int. Electron Devices Meeting, 1995, pp. 717-720.

[24] T. Gokdemir, et al., “Multilayer Passive Components for Uniplanar Si/SiGe MMICs,” in 1997 IEEE RFIC Symposium Dig., pp. 233-236, June 1997.

[25] J. Rogers, et al., “A High Q On-chip Cu Inductor Post Process for Si Integrated Circuits,” in 1999 Int. Interconnect Technology Conference Dig., pp. 239-241, 1999.

[26] H. Takenaka, et al., “0.15 m T-shaped Gate Fabrication for GaAs MODFET Using Phase Shift Lithography,” IEEE Trans. Electron Devices, Vol. 43, No. 2, pp.238-244, Feb. 1996.

[27] B. Piernas, et al., “A Broadband and Miniaturized V-band PHEMT Frequency Doubler,” IEEE Microwave and Guided Wave Letters, vol. 10, no. 7, pp. 276-278, July 2000.

Table 1 Recent reports on thin-film multilayer microwave/RFIC technologies

Organization�

Film material�

Total film thickness�

Film layer number�

Metal�

Substrate�

Device�

Application, target�

Ref.�

NTT�

Polyimide�

10 m�

4�

Au, Al�

GaAs, Si�

MESFET, PHEMT, BJT�

Low cost,

Miniaturization,

High frequency

Operation of Si MMIC�

[5],[6],

[9]�

BCB�

10 m�

4�

Au�

GaAs�

MESFET�

[8]�

PBO�

20 m�

1�

Cu�

Si�

CMOS�

High Q inductor,

Low loss�

[10]�

TI / Triquint�

Polyimide�

25 m�

1�

Au�

GaAs�

PHEMT�

Low cost, PA, LNA�

[11]�

Toshiba�

BCB�

10 m�

1�

Au�

GaAs�

PHEMT�

MM-wave MMIC�

[12]�

Matsushita�

SiO2�

9 m�

1�

Au, AlSiCu�

Si�

Low cost MM-wave IC�

[13]�

BCB�

26 m�

1�

Au�

Si, Glass�

[14],[15]�

NEC�

Polyimide+SiON�

6 m�

1�

Al�

Si�

MOSFET�

High frequency operation,

Low cost�

[16]�

UCLA�

Polyimide�

27 m�

2�

TiAl�

Si�

MM-wave Silicon MMIC�

[17]�

HRL�

BCB�

13 m�

1�

Au, AlCu�

Si�

SiGe HBT (IBM)�

High frequency operation,

Low cost�

[18]�

Polyimide�

13 m�

1�

Au, AlCu�

Si�

SiGe HBT (IBM)�

[19]�

IBM�

Polyimide�

15 m�

1�

AlCu�

Si�

SiGe HBT�

High frequency operation,

Low cost�

[20]�

SiO2�

10.2 m�

4�

AlCu�

Si�

BiCMOS�

High Q inductor�

[21]�

SiO2�

5.8 m�

3�

AlCu�

Si�

SiGe HBT�

[22]�

Samsung�

Polyimide�

10 m�

1�

Al�

Si�

BiCMOS�

High Q inductor, Low loss�

[23]�

King’s college London�

Polyimide�

6 m�

3�

Al�

Si�

High Q inductor, Low loss�

[24]�

Carleton Univ.�

Polyimide�

10 m�

1�

Cu�

Si�

High Q inductor�

[25]�

Fig. 1 Basic structure of 3DMMIC

Fig. 2 Master arrays

Fig. 3 Unit cell design

Block diagram

Microphotograph

Fig. 4 Prototype down converter

Fig. 5 Cost effective MMIC development based on 3D/multilayer MMIC process

Table 2 Device parameter variation after 3D fabrication

Wg = 100 m�

Difference (%)�

fmax (GHz)�

-6.51�

fT (GHz)�

-9.21�

Cgd (fF)�

7.63�

Cds (fF)�

20.3�

[email protected] (dB)�

-5.21�

� �

(a) Frequency doubler (1.43 ( 1.26 mm) (b) Wideband LNA (1.52 ( 1,17 mm)

Fig. 6 Fabricated 3DMMICs.