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FDM

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hannel Shielded Gate Pow

erTrench ® MO

SFET

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Semiconductor Components Industries, LLC, 2016 Publication Order Number: December, 2016, Rev. 1.1 FDMS004N08C/D

1

FDMS004N08C N-Channel Shielded Gate PowerTrench® MOSFET 80 V, 126 A, 4.0 mΩFeatures

Shielded Gate MOSFET Technology

Max rDS(on) = 4.0 mΩ at VGS = 10 V, ID = 44 A

Max rDS(on) = 10.4 mΩ at VGS = 6 V, ID = 22 A

50% Lower Qrr than Other MOSFET Suppliers

Lowers Switching Noise/EMI

MSL1 Robust Package Design

100% UIL Tested

RoHS Compliant

General DescriptionThis N-Channel MV MOSFET is produced using ON Semiconductor’s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized to minimise on-state resistance and yet maintain superior switching performance with best in class soft body diode.

ApplicationsPrimary DC-DC MOSFET

Synchronous Rectifier in DC-DC and AC-DC

Motor Drive

Solar

MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Ratings UnitsVDS Drain to Source Voltage 80 VVGS Gate to Source Voltage ±20 V

ID

Drain Current -Continuous TC = 25 °C (Note 5) 126

A -Continuous TC = 100 °C (Note 5) 80 -Continuous TA = 25 °C (Note 1a) 18 -Pulsed (Note 4) 637

EAS Single Pulse Avalanche Energy (Note 3) 486 mJ

PDPower Dissipation TC = 25 °C 125

WPower Dissipation TA = 25 °C (Note 1a) 2.5

TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C

RθJC Thermal Resistance, Junction to Case 1.0°C/W

RθJA Thermal Resistance, Junction to Ambient (Note 1a) 50

Device Marking Device Package Reel Size Tape Width QuantityFDMS004N08C FDMS004N08C Power 56 13 ’’ 12 mm 3000 units

G

S

S

S

D

D

D

D

5

6

7

8

3

2

1

4

Bottom Top

Pin 1S

GS

S

D

DD

D

Power 56

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erTrench ® MO

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2

Electrical Characteristics TJ = 25 °C unless otherwise noted.

Off Characteristics

On Characteristics

Dynamic Characteristics

Switching Characteristics

Drain-Source Diode Characteristics

Symbol Parameter Test Conditions Min. Typ. Max. Units

BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 80 VΔBVDSS ΔTJ

Breakdown Voltage TemperatureCoefficient ID = 250 μA, referenced to 25 °C 40 mV/°C

IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 μAIGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA

VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 2.0 3.1 4.0 V ΔVGS(th) ΔTJ

Gate to Source Threshold VoltageTemperature Coefficient ID = 250 μA, referenced to 25 °C -8.3 mV/°C

rDS(on) Static Drain to Source On ResistanceVGS = 10 V, ID = 44 A 3.4 4.0

mΩVGS = 6 V, ID = 22 A 5.2 10.4VGS = 10 V, ID = 44 A, TJ = 125 °C 5.8 6.5

gFS Forward Transconductance VDS = 5 V, ID = 44 A 98 S

Ciss Input CapacitanceVDS = 40 V, VGS = 0 V,f = 1 MHz

3035 4250 pFCoss Output Capacitance 940 1315 pFCrss Reverse Transfer Capacitance 27 40 pFRg Gate Resistance 0.1 1.1 2.3 Ω

td(on) Turn-On Delay TimeVDD = 40 V, ID = 44 A,VGS = 10 V, RGEN = 6 Ω

17 30 nstr Rise Time 6 12 nstd(off) Turn-Off Delay Time 25 40 nstf Fall Time 4 10 nsQg Total Gate Charge VGS = 0 V to 10 V

VDD = 40 V, ID = 44 A

39 55 nCQg Total Gate Charge VGS = 0 V to 6 V 25 34 nCQgs Gate to Source Charge 13 nCQgd Gate to Drain “Miller” Charge 7 nCQoss Output Charge VDD = 40 V, VGS = 0 V 55 nCQsync Total Gate Charge Sync. VDS = 0 V, ID = 44 A 35 nC

VSD Source to Drain Diode Forward VoltageVGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2

VVGS = 0 V, IS = 44 A (Note 2) 0.8 1.3

trr Reverse Recovery TimeIF = 22 A, di/dt = 300 A/μs

26 41 nsQrr Reverse Recovery Charge 48 76 nCtrr Reverse Recovery Time

IF = 22 A, di/dt = 1000 A/μs19 31 ns

Qrr Reverse Recovery Charge 108 174 nCNotes:1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.3. EAS of 486 mJ is based on starting TJ = 25 °C; N-ch: L = 3 mH, IAS = 18 A, VDD = 80 V, VGS =10 V. 100% test at L = 0.1 mH, IAS = 57 A.4. Pulsed Id please refer to Fig 11 SOA graph for more details.5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.

G DF

DS

SF SS

G DF

DS

SF SS

50 °C/W when mounted on a 1 in2 pad of 2 oz copper

125 °C/W when mounted on a minimum pad of 2 oz copper.

FDM

S004N08C

N-C

hannel Shielded Gate Pow

erTrench ® MO

SFET

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3

Typical Characteristics TJ = 25 °C unless otherwise noted.

Figure 1.

0 1 2 3 4 50

50

100

150

200

250

300

VGS = 6 V

VGS = 5.5 V

VGS = 8 V

PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX

VGS = 5 V

VGS = 10 V

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

On Region Characteristics Figure 2.

0 50 100 150 200 250 3000

1

2

3

4

5

VGS = 5.5 V

PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 6 V

VGS = 8 V

VGS = 5 V

VGS = 10 V

Normalized On-Resistance vs. Drain Current and Gate Voltage

Figure 3. Normalized On Resistance

-75 -50 -25 0 25 50 75 100 125 1500.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

ID = 44 AVGS = 10 V

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)

vs. Junction TemperatureFigure 4.

4 5 6 7 8 9 100

5

10

15

20

25

TJ = 125 oC

ID = 44 A

TJ = 25 oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS(

on),

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E (m

Ω) PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

On-Resistance vs. Gate to Source Voltage

Figure 5. Transfer Characteristics

3 4 5 6 7 8 90

60

120

180

240

300

TJ = 150 oC

VDS = 5 V

PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX

TJ = -55 oC

TJ = 25 oC

I D, D

RA

IN C

UR

REN

T (A

)

VGS, GATE TO SOURCE VOLTAGE (V)

Figure 6.

0.0 0.2 0.4 0.6 0.8 1.0 1.20.001

0.01

0.1

1

10

100300

TJ = -55 oC

TJ = 25 oC

TJ = 150 oC

VGS = 0 V

I S, R

EVER

SE D

RA

IN C

UR

REN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Source to Drain Diode Forward Voltage vs. Source Current

FDM

S004N08C

N-C

hannel Shielded Gate Pow

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SFET

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4

Figure 7.

0 8 16 24 32 400

2

4

6

8

10ID = 44 A

VDD = 50 V

VDD = 40 V

V GS,

GA

TE T

O S

OU

RC

E VO

LTA

GE

(V)

Qg, GATE CHARGE (nC)

VDD = 30 V

Gate Charge Characteristics Figure 8.

0.1 1 10 801

10

100

1000

10000

f = 1 MHzVGS = 0 V

CA

PAC

ITA

NC

E (p

F)

VDS, DRAIN TO SOURCE VOLTAGE (V)

Crss

Coss

Ciss

Capacitance vs. Drain to Source Voltage

Figure 9. Unclamped Inductive Switching Capability

0.001 0.01 0.1 1 10 100 10001

10

100

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS,

AVA

LAN

CH

E C

UR

REN

T (A

)

Figure 10.

25 50 75 100 125 1500

25

50

75

100

125

150

VGS = 6 V

RθJC = 1.0 oC/W

VGS = 10 V

I D, D

RA

IN C

UR

REN

T (A

)

TC, CASE TEMPERATURE (oC)

Maximum Continuous Drain Current vs Case Temperature

Figure 11. Forward Bias Safe Operating Area

0.1 1 10 100 5000.1

1

10

100

1000

CURVE BENT TO MEASURED DATA

10 μs

100 ms/DC10 ms1 ms

100 μs

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS LIMITED BY rDS(on)

SINGLE PULSETJ = MAX RATEDRθJC = 1.0 oC/WTC = 25 oC

Figure 12.

10-5 10-4 10-3 10-2 10-1 110

100

1000

10000

100000SINGLE PULSERθJC = 1.0 oC/WTC = 25 oC

P(PK

), PE

AK

TR

AN

SIEN

T PO

WER

(W)

t, PULSE WIDTH (sec)

Single Pulse Maximum Power Dissipation

Typical Characteristics TJ = 25 °C unless otherwise noted.

FDM

S004N08C

N-C

hannel Shielded Gate Pow

erTrench ® MO

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5

Figure 13.

10-5 10-4 10-3 10-2 10-1 10.001

0.01

0.1

12

SINGLE PULSE

DUTY CYCLE-DESCENDING ORDER

r(t),

NO

RM

ALI

ZED

EFF

ECTI

VE T

RA

NSI

ENT

THER

MA

L R

ESIS

TAN

CE

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5 0.2 0.1 0.05 0.02 0.01

NOTES:ZθJC(t) = r(t) x RθJCRθJC = 1.0 oC/W

Duty Cycle, D = t1 / t2Peak TJ = PDM x ZθJC(t) + TC

PDM

t1t2

Junction-to-Case Transient Thermal Response Curve

Typical Characteristics TJ = 25 °C unless otherwise noted.

FDM

S004N08C

N-C

hannel Shielded Gate Pow

erTrench ® MO

SFET

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6

Dimensional Outline and Pad Layout

ON Semiconductor and the ON Logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

C

L

L

C

PKG

PKG

5.10

6.15

TOP VIEW

SIDE VIEW

1 4

8 5

A

B

NOTES: UNLESS OTHERWISE SPECIFIED

A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,

ISSUE A, VAR. AA,.

B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.

MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.

C. ALL DIMENSIONS ARE IN MILLIMETERS.

D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.

E. IT IS RECOMMENDED TO HAVE NO TRACES OR

VIAS WITHIN THE KEEP OUT AREA.

5.85

5.65

5.00

4.80

OPTIONAL DRAFT

ANGLE MAY APPEAR

ON FOUR SIDES

OF THE PACKAGE

(0.50)

(0.52)

SEE

DETAIL C

BOTTOM VIEW

0°-12°

0.35

0.15

C

SEATING

PLANE

DETAIL C

SCALE: 2:1

0.05

0.00

1 2 3 4

8 7 6 5

0.76

0.51

0.51

0.31

(8X)

3.81

0°-12°

0.35

0.15

0.30

0.05

SEE

DETAIL B

DETAIL B

SCALE: 2:1

(0.34)

1.27

0.10 C A B

3.96

3.61

3.48

+0.30

-0.10

0.44±0.10

0.08 C

0.10 C

1.10

0.90

8X

(0.30)

(2X)

1.27

3.81

1.27

6.61

3.91

4.52

1.27

1 2 3 4

8 567

LAND PATTERN

RECOMMENDATION

0.77

0.61

KEEP OUT

AREA

5.10

3.75

0.20

+0.10

-0.15

(8X)

6.25

5.90

5.20

4.80

PQFN8 5X6, 1.27P

CASE 483AE

ISSUE A

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ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patentcoverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customerapplication by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classificationin a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. Thisliterature is subject to all applicable copyright laws and is not for resale in any manner.

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