Putting the Pieces TogetherCOMP375 Computer Architecture and

Organization

“On the plains of hesitation lie the

blackened bones of countless millions

who at the dawn of victory lay down to

rest, and in resting died.”

Adlai E. Stevenson

gestalt(gesh-TALT) noun

Shape or pattern; most often used in psychology to describe a theory or approach which aims to see something as a whole rather than breaking it into separate parts

wordsmith.org

Simple CPU

CPU with Cache

CPU with Virtual Memory

Detail of Microcode Store

Microcode Control

Multiple Registers

Interrupts

bus

→

IR

IR

adr

→

bus

res

ult

→

bus

bus

→

A

L

U

bus

→

opr

nd

bus

→

PC

PC

→

bus

bus

→

R1

R1

→

bus

bus

→

R2

R2

→

bus

bus

→

MA

R

bus

→

M

B

R

M

B

R

→

bus

Int

save

addr

→

bus

Int

new

PC

→

bus

A

L

U

fun

Mem

func

X X

X X write

X X wait

Inventor of Microcode

• Maurice Wilkes invented microcode

• Builder and designer of the EDSAC, one of the first computers with an internally stored program

• Introduced the concept of program libraries

• “I can remember the exact instant when I realized

that a large part of my life from then on was going

to be spent in finding mistakes in my own

programs.”

Basic Computer Components

CPU

I/O Controller

I/O Device

MemoryBus

Cache

Basic Computer Components

CPU

cache I/O Controller

I/O Devices

MemoryBus

I/O Controller

I/O Device

Basic Computer Components

CPU

cache I/O Controller

I/O Device

MemoryBus

I/O Controller

I/O Device

I/O Device

I/O Controller Functionality• Interface translation

– connection, voltage

– protocol

– clocking

• Addressing

• Multiplexing

• Buffering

• Error detection and correction

• Control of multiple steps

When is the COMP375 final exam?

A. Monday, December 9 at 10:30am

B. Monday, December 9 at 1:00 pm

C. Tuesday, December 10 at 1:00 pm

D. Tuesday, December 10 at 10:30 am

E. Wednesday, December 11 at 10:30am

Memory Hierarchy

Steps in Accessing Memory - 1

• Compute effective address

• Split effective address into page number and offset

• Use page number as an index into the page table. (Check if too big.)

• If Resident bit is clear, generate a page fault.

• if Resident bit is set, get page address from the page table.

Steps in Accessing Memory - 2

• Concatenate page address with offset to create the physical address

• For direct L1 cache, get the middle bits of the physical address to determine which line to check

• Check the tag value of the specified line to see if it matches the upper bits of the physical address

• If there is a match, return the specified value from the cache

Steps in Accessing Memory - 3

• If the tag field does not match, check the second level cache

• For n-way set associative L2 cache, get the middle bits of the physical address to determine which set to search

• Search the tag values of all n lines in the specified set to see if any match the upper bits of the physical address

• If there is a match, return the specified value from the cache

Steps in Accessing Memory - 4

• If none of the n tag fields for the set match the upper bits of the physical, then determine which of the lines in the specified set of the L2 cache is the oldest. This line will hold the new data

• If this line is dirty, write this block to RAM

• Get the physical address data from RAM

• Copy the block of data from RAM into the L1 and L2 caches. Send the CPU the data requested

Intel Performance

Architectural

Improvements

0.0

1000.0

2000.0

3000.0

4000.0

5000.0

6000.0

7000.0

8000.0

1987 1989 1991 1993 1995 1997 1999 2001 2002 2003

Clock

Architecture

Incentive for Dual Core• Intel reports that underclocking a single core

by 20 percent saves half the power while sacrificing just 13 percent of the performance.

Source: IEEE Spectrum April, 2008

Layers

• Applications

• Middleware – other CS classes

• High level languages

• Machine Language – COMP375

• Microcode

• Logic circuits

• Gates – COMP180 or ELEN327

• Transistors

• Silicon structures

Final Questions

• Memory Hierarchy

• Assembler program

• Microcode table

• How long to read X bytes from a disk

• How long to transfer X bytes over a bus

• Cache mapping fields

• Appropriate RAID and number of disks

very similar to the Exams

Final Exam

• The final exam is on Monday, December 9 at 10:30 in McNair 129

• You are allowed one 8 ½ x 11" page of notes

• The exam is cumulative covering material from the entire semester

• Practice final exam on Blackboard under course materials

Final Exam

Monday, December 9, 2019

10:30 am to 12:30 pm