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Project Mid Semester Implementing a compressor in software and decompression in hardware Presents by - Schreiber Beeri Yavich Alon Guided by – Porian Moshe 11.1.2011

Project Mid Semester

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Project Mid Semester. 11.1.2011. Implementing a compressor in software and decompression in hardware. Presents by - Schreiber Beeri Yavich Alon Guided by – Porian Moshe. Reminder. Gym Control Room. Gym. Compressed data (Wireless). ❤. ❤. 142. 132. ❤. ❤. 170. 79. ❤. ❤. - PowerPoint PPT Presentation

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Page 1: Project Mid Semester

Project Mid Semester

Implementing a compressor in software and decompression in hardware

Presents by - Schreiber Beeri

Yavich Alon

Guided by – Porian Moshe

11.1.2011

Page 2: Project Mid Semester

Reminder

142❤

Compressed data(Wireless)

Gym

132❤

170❤ 79❤

130❤ 127❤

Gym Control Room

Page 3: Project Mid Semester

Transmitter Compresses the dataReceiver extracts and displays

the data

Reminder (Cont.)

Page 4: Project Mid Semester

TOP ARCHITECTURE

Page 5: Project Mid Semester

VGA

Display

HostMatlab

UART RX

UART TX

Message

Decoder

RAM

MU

XMessage

Encoder

RAM DEC

Display Controlle

r

RunLen Decoder

CRC

IS42S16400 SDRAM

SDRAM Controller

Arbiter

Mem Write

Mem Read

REG

ISTER

S

Packet TX

Packet RX

Ext. Clk

PLL

ResetD’ bouncer

Ext. Reset

Sys.

ClkSys.

Rst

FPGA – Cyclone II

TX

RX

VESA

11

5,2

00K

Bit/se

c

800x600Done

Implemented,not

integratedUpdate

RequiredNot Implemented

Page 6: Project Mid Semester

MICRO ARCHITECTURE

Page 7: Project Mid Semester

DATA

Ad

dr

DATA

COLOR

DATA

Data&Valid

Message Decoder

RAM

DEC

Mem Write

Arbiter

SDRAM Controlle

r Mem Read

RunLen DecoderREGISTER

S

VGA Display

TX PACKPLL

Reset Debounc

er

Resets

SDARM

UART

Matlab

UART RXP

RAM Controlle

r

Display Controlle

r

FIFO(dual clock

)

UART TXP

REG Controlle

r

Addr REG

TYPE REG

CheckSum

Len REG

UART RXD

UART TXD from UART TX

VALID

DATA

REG CRC STATUS

CRC_ERR FROM MSG_DEC MP

REGS

RES

ET

Sta

tus

REQ

VALIDCRC_ERR

DATA

WR

EN

WR_addr

RD_adress

Type

DATA

DATA

REQ

REQ

EN

EN

REQ

AC

K

REQ

REQ

Adress

ACK VA

LID

DATA RX

_RD

Y t

o

MEM

REA

D

RX

_RD

Y f

rom

M

EM

RE

AD

DATA

_RD

Y t

o

ME

M R

EA

D

DATA

_RD

Y f

rom

M

EM

RE

AD

REP

VALID

DATA

COLOR CO

L_EN

DATA

RGB

UART TXD to UART TX

50MHZ

40MHZ (VESA)133MHZ (SDRAM)

1 bit8 bits

10 bits16 bits22 bits

Line legend

Data &

Control

Data &

Control

MSG_OK

Num Pixels

n_p

ix

40MHz

CheckSum & Valid

CRC Statu

s

FIFO

FULL

EM

PT

Y

DATA

&

Valid

REQ

Page 8: Project Mid Semester

Method of OperationProject Directory Structure

The work method established in the project was assisted with these tools:◦SVN◦Code review◦Coding Guidelines◦Excel assignment file

Page 9: Project Mid Semester

Excel assignment fileModel / IP / TB Assignments Responsibility Synthised

AlreadyStart Date Done Date / Expected Status

UART TX&RX Generator   Beeri --- 16.11.2010 16.12.2010 DONE

UART RX

Delete HALFBIT_ST State, by counting until the middle of the bit Alon YES 17.11.2010 22.12.2010 DONE

Add '5' to sample_cnt at IDLE_ST Alon YES 6.1.2011 8.1.2011 Open

Fix drifting problem (2 stop bits are needed by Matlab to send correct value) Alon YES 22.12.2010 1.1.2011 Open

UART TX

Add 'data_valid' port from FIFO Alon

YES

24.12.2010 1.1.2011 DONE

Check if missing stop bit at special FIFO situation Beeri 6.1.2011 14.1.2011 Open

dout_i should be implemented using SR Alon 1.1.2011 20.10.2011 Open

Use ShiftRegister Alon 24.12.2010 1.1.2011 DONE

Use external FIFO Alon 27.11.2010 20.12.2010 DONE

UART TB Add many test to the regression Alon --- 27.11.2010 1.1.2011 Open

MessagePack Decoder

CRC - Change interface. WHEN waste too many logic Beeri

YES 19.11.2010

22.12.2010 DONE

Remove CRC output port Beeri 22.12.2010 DONE

Change blk_pos range to automatic function Beeri 1.1.2011 Open

init_sof_eof_proc : See how it looks like after synthesis, then consult about it with Moshe Beeri 22.12.2010 DONE

MessagePack Encoder

init_sof_eof_proc : See how it looks like after synthesis, then consult about it with Moshe Beeri

YES 27.11.2010

19.12.2010 DONE

Change blk_pos range to automatic function Beeri 1.1.2011 Open

Fix CRC Process Beeri 27.12.2011 DONE

Replace UART interface with FIFO interface Beeri 20.12.2010 DONE

UART&MP TB

Add Regresion to Macro File Beeri --- 20.12.2010 1.1.2011 OPEN

Re-run after UART and MP changes Beeri --- 20.11.2010 22.12.2010 Re-Opened

Page 10: Project Mid Semester

UART’s Test Bench

UART Generat

or

UART RX

Message Pack

Decoder

RAM

Message Pack

Encoder

CheckSum

UART TX

UART Comparat

or

FIFOCheckSum

This will be shown using Matlab and DE2 board

Page 11: Project Mid Semester

Maximum Current FrequencyAccording to Quartus Timing

Analyzer: 150MHz, in this implementation

Pin

Signal route through FPGA

Logic

Page 12: Project Mid Semester

Current Implemented IPsUART Rx, Tx

◦Noise-proof◦5-8 Data Bits◦Enable / Disable Parity Bit◦Odd / Even Parity Bit◦Parity & Stop bit Error◦System clock and UART transmission

clock is set by generic parameter

Start Bit

5-8 Data Bits

Stop Bit

Parity Bit (Optional

)

Page 13: Project Mid Semester

UART TX’s FSM

IDLE

TX

reset

fifo_empty p

os_c

nt

=

dat

abits

+ p

arityb

it

+ 1

REGDATA

fifo_Din_Valid

not fifo_em

pty

1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

Shift Register

Data – A2 Hexdout

Page 14: Project Mid Semester

Current Implemented IPsMessage Pack Encoder

◦Encodes a message from registers, RAM and CRC block

◦Generic block sizeMessage Pack Decoder

◦Decodes a message into registers, RAM, and compares CRC

◦Generic block size

Page 15: Project Mid Semester

Current Implemented IPsCheckSum Block

◦Calculates Signed / Unsigned Checksum

◦Generic input and output size◦Comfortable handshakedata_valid

reset_checksumreq_checksum

checksum_valid

Page 16: Project Mid Semester

Current Implemented IPsGeneric MUX

◦Generic input, selectorsGeneric Decoder

◦Generic selectors

Page 17: Project Mid Semester

Current Implemented IPsGeneric RAM

◦Generic input / output size (Under Development)

Generic FIFO◦Generic FIFO size, data width

SDRAM Controller◦IS42S16400 Model

Written in pure VHDL.Independent  in the FPGA’s vendor

Page 18: Project Mid Semester

RAM – Different ImplementationsFirst Implementation:

Resources:8209 DFF8192 MUX

And more…

Page 19: Project Mid Semester

RAM – Different ImplementationsCurrent Implementation:

Resources:5 DFF4 MUX

1 Decoder2 Sync RAM

Din_validAddr_in

Addr_out_valid

Addr_outData_in

Dout_valid

Data_out

Page 20: Project Mid Semester

Current Implemented Simulation ModelsUART Generator

◦Generates UART transmission from text file

◦Generic UART parameters: Enable / Disable Parity bit Even / Odd parity bit Various transmission rates Generic delay between files transmission

UART Comparator◦Compares received UART transmission

to text file

Page 21: Project Mid Semester

Simulation MethodVarious Macro (DO) files, each

one execute the simulation with different generic parameter.

Validate wave against expected signals

Automatic software validation of actual data against expected data

Page 22: Project Mid Semester

UART Simulations:Pass/Fail

Description Test

Num

ODD/EVEN

PARITY

Deviation %

RX BAUD.

TX BAUD.

CLK MHz

Pass x x 0 115200 115200 133 1

Pass x x 4 115200 110592 133 2

Pass x x 5 115200 120960 133 3

Fail x x 5 115200 109440 133 4

Pass ODD V 0 115200 115200 133 5

Pass ODD V 5 115200 109440 133 6

Pass ODD V 5 115200 120960 133 7

Pass EVEN V 0 115200 115200 133 8

Pass EVEN V 4 115200 110592 133 9

Pass EVEN V 5 115200 120960 133 10One Kbyte data transfer has been simulated

TX RXGen CMP

Page 23: Project Mid Semester

Pass/Fail

Description Test Num

ODD/EVEN

PARITY

Deviation %

RX BAUD.

TX BAUD.

CLK MHz

Pass x x 0 115200 115200

33 11

Pass x x 5 115200 109440

33 12

Pass x x 5 115200 120960

33 13

Fail x x 6 115200 108288

33 14

Pass ODD V 0 115200 115200

33 15

Pass ODD V 5 115200 109440

33 16

Pass ODD V 5 115200 120960

33 17

Pass EVEN V 0 115200 115200

33 18

Pass EVEN V 5 115200 109440

33 19

Pass EVEN V 5 115200 120960

33 20

UART Simulations (Cont.):

One Kbyte data transfer has been simulated

TX RXGen CMP

Page 24: Project Mid Semester

DocumentationsDone:

◦SDRAM Controller◦UART RX, TX

To do:◦MessagePack + Checksum◦RAM◦FIFO◦MUX◦Decoder

Page 25: Project Mid Semester

Schedule To do… Date Num.

Theoretical self-instruction 1.10 – 16.10 1

Run length algorithm implementation

17.10 – 23.10 2

SDRAM Controller implementation 24.10 – 30.10 3

Architecture definition 31.10 – 15.11 4

Project Characterization presentation 16.11 5

Full characterization of all blocks 17-1.12 6

Implement UART RX-MP & TB 2.12-8.12 7

Implement UART TX-MP & TB 9-15.12 8

Prepare Mid. Presentation 16-27.12 9

Done

Done

Done

Done

DonePartia

l

Done

Done

Done

Page 26: Project Mid Semester

Schedule To do… Date Num.

(1)Implement Display Controller & TB

(2)Update Debouncer

11.1-26.1 10

Exams!!! Prepare documentation to existing models, end of semester presentation, and final semester A

report

27.1-22.2 11

Present end of semester presentation

23.2 12