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Problem sets/ EE382 Project: Starting with Verilog 2012 - EE382 - 16905 Veynu Narasiman Carlos Villavieja

Problem sets/ EE382 Project: Starting with Verilog

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Problem sets/ EE382 Project: Starting with Verilog. 2012 - EE382 - 16905 Veynu Narasiman Carlos Villavieja. Course website. http://www.ece.utexas.edu/~patt/12s.382N/. Problem Sets. The course has two different parts: Small set of problems - individual ALU design ALU implementation - PowerPoint PPT Presentation

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Page 1: Problem sets/ EE382 Project: Starting with Verilog

Problem sets/ EE382 Project:Starting with Verilog

2012 - EE382 - 16905Veynu NarasimanCarlos Villavieja

Page 2: Problem sets/ EE382 Project: Starting with Verilog

Course website

• http://www.ece.utexas.edu/~patt/12s.382N/

Page 3: Problem sets/ EE382 Project: Starting with Verilog

Problem Sets

• The course has two different parts:– Small set of problems - individual• ALU design • ALU implementation• Datapath design for several x86 instructions• Control logic design

– The project - groups of 3 people• Build a 1 wide-issue in-order x86 processor running a

limited set of instructions• A set of instructions will be published in the course

website

Page 4: Problem sets/ EE382 Project: Starting with Verilog

Tools location

Machines in ECE:http://www.ece.utexas.edu/it/remote_linux.cfmForget about sunservers

Tools Path:/usr/local/packages/synopsys_2011/vcs-mx/bin/vcs

Page 5: Problem sets/ EE382 Project: Starting with Verilog

Some documentation

• /usr/local/packages/synopsys_2011/vcs-mx/doc/help_vcs.txt

• /usr/local/packages/synopsys_2011/vcs-mx/doc/• /usr/local/packages/synopsys_2011/vcs-mx/

doc/UserGuide/• /usr/local/packages/synopsys_2011/vcs-mx/

doc/UserGuide/pdf/• /usr/local/packages/synopsys_2011/vcs-mx/

doc/UserGuide/pdf/mvsim_native.pdf

Page 6: Problem sets/ EE382 Project: Starting with Verilog

Let's start

Setting up the environment:

Load the compiler modules•module load synopsys/vcs•module initadd synopsys/vcs

Page 7: Problem sets/ EE382 Project: Starting with Verilog

High level diagram

LatchD

Wen

Q

Qbar

Source code at : http://www.ece.utexas.edu/~patt/12s.382N/tools/vcs_manual.html

Page 8: Problem sets/ EE382 Project: Starting with Verilog

DWen Q

QbarWen

D

S

R

D Wen D S R

0011

0101

1100

1110

1011

Q Qbar

X0X1

X1X0

Page 9: Problem sets/ EE382 Project: Starting with Verilog

Compiling and Running

• cat master /home/projects/courses/spring-12/ee382n-16905/lib/time-v /home/projects/courses/spring-12/ee382n-16905/lib/lib1

d-latch.v

• vcs –debug_all -f master• You will have a binary file ./simvRun and generate the timing info• ./simv

-v: only modules instantiated are compiled

Page 10: Problem sets/ EE382 Project: Starting with Verilog

Visualization tool - dve

• ssh –x [email protected]• Or connecting through VNC – see instructions

on the course webpage• dve • File – Open Database - .dump.vpd file

Page 11: Problem sets/ EE382 Project: Starting with Verilog

Starting dve

Page 12: Problem sets/ EE382 Project: Starting with Verilog

Waveform result

Page 13: Problem sets/ EE382 Project: Starting with Verilog

Debug – step by step

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