PFC-CCMICE1PCS01/G

Standalone Power FactorCorrect ion (PFC) Control ler inCont inuous Conduct ion Mode(CCM)

N e v e r s t o p t h i n k i n g .

Prel iminary Datasheet, Version 1.0, 23 Oct 2002P

re

l im

i na

ry

Da

t a

Power Management & Supply

Edition 2002-10-23

Published by Infineon Technologies AG,St.-Martin-Strasse 53,D-81541 München

© Infineon Technologies AG 1999.All Rights Reserved.

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted char-acteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regardingcircuits, descriptions and charts stated herein.Infineon Technologies is an approved CECC manufacturer.

Information

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PFC-CCM

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PFC-CCMICE1PCS01/G

Preliminary Data

Standalone Power Factor Correction(PFC) Controller in ContinuousConduction Mode (CCM)

P-DIP-8-4

ICE1PCS01P-DIP-8-4

ICE1PCS01GP-DSO-8-3

Product Highlights• Wide Input Range• Output Power Controllable by External Sense

Resistor• Programmable Operating Frequency• Output Under-Voltage Detection• Fast Output Dynamic Response during Load

Features• Ease of Use with Few External Components• Supports Wide Range• Average Current Control• External Current and Voltage Loop Compensation

for Greater User Flexibility• Programmable Operating/Switching Frequency

(50kHz - 250kHz)• Max Duty Cycle of 97% at 125kHz• Trimmed Internal Reference Voltage (5V+2%)• VCC Under-Voltage Lockout• Cycle by Cycle Peak Current Limiting• Over-Voltage Protection• Open Loop Detection• Output Under-Voltage Detection• Brown-Out Protection• Enhanced Dynamic Response• Unique Soft-Start to Limit Start Up Current• Fulfills Class D Requirements of IEC 1000-3-2

DThICsigextoswThanfreconaThsupeun(5Ththdio

Preliminary Datasheet

Type Ordering Code

ICE1PCS01

ICE1PCS01G

90 ... 265 VAC EMI-FilterPFC

A

Typical

SWITCH

FREQ

ICOMP

ISE

GATE

escriptione ICE1PCS01/G is a 8-pin wide input range controllerfor active power factor correction converters. It is de-ned for converters in boost topology, and requires fewternal components. Its power supply is recommendedbe provided by an external auxiliary supply which willitch on and off the IC.e IC operates in the CCM with average current control,d in DCM only under light load condition. The switchingquency is programmable by the resistor at pin 4. Bothmpensations for the current and voltage loop are exter-l to allow full user control.ere are various protection features incorporated to en-re safe system operation conditions. Examples areak current limitation, brown-out protection and outputder voltage detection. The internal reference is trimmedV+2%) to ensure precise protection and control level.e device has an unique soft-start function which limits

e start up current thus reducing the stress on the boostde.

3 23 Oct 2002

Package

P-DIP-8-4

P-DSO-8-3

Voltage LoopCompensation

Protection Unit

VariableOscillator

Current LoopCompensation

PWM LogicDriver

ICE1PCS01/ICE1PCS01G-Controller

VCC

uxiliary Supply VOUT

Application

RampGenerator

VSENSE

VCOMP

NSE GND

NonlinearGain

PFC-CCMICE1PCS01/G

Table of Contents Page

Preliminary Data

Preliminary Datasheet 4 23 Oct 2002

1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.3 Start-up (Soft-Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.4 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4.1 Brown-Out Protection (BOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4.2 Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4.3 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83.4.4 Open Loop Protection / Input Under Voltage Protect (OLP) . . . . . . . . . . 93.4.5 Output Under Voltage Detection (OUV) . . . . . . . . . . . . . . . . . . . . . . . . . . 93.4.6 Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.5 Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.6 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.6.1 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.6.2 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.6.3 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93.6.4 Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.7 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.8 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.8.1 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.8.2 Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.9 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.2 Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.3 Variable Frequency and PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . 134.3.4 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.3.5 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.3.6 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144.3.7 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PFC-CCMICE1PCS01/G

Pin Configuration and Functionality

Preliminary Data

1 Pin Configuration and Functionality1.1 Pin Configuration

Figure 1 Pin Configuration (top view)

1.2 Pin Functionality

GND (Ground)The ground potential of the IC.

ICOMP (Current Loop Compensation)Low pass filter and compensation of the current controlloop. The capacitor which is connected at this pinintegrates the output current of OTA2 and averages thecurrent sense signal.

ISENSE (Current Sense Input)The ISENSE Pin senses the voltage drop at theexternal sense resistor (R1). This is the input signal forthe average current regulation in the current loop. It isalso fed to the peak current limitation block.During power up time, high inrush currents cause highvoltage drop at R1, driving currents into pin 3 whichcould be beyond the absolute maximum ratings.Therefore a series resistor (R2) of around 220Ω isrecommended in order to limit this current into the IC.

FREQ (Frequency Setting)This pin allows the setting of the operating switchingfrequency by connecting a resistor to ground. Thefrequency range is from 50kHz to 250kHz.

VSENSE (Voltage Sense/Feedback)The output bus voltage is sensed at this pin via aresistive divider. The reference voltage for this pin is5V.

VCOMP (Voltage Loop Compensation)This pin provides the compensation of the outputvoltage loop with a compensation network to ground(see Figure 2). This also gives the soft start functionwhich controls an increasing AC input current duringstart-up.

VCC (Power Supply)The VCC pin is the positive supply of the IC and shouldbe connected to an external auxiliary supply. Theoperating range is between 10V and 21V. The turn-onthreshold is at 11V and under voltage occurs at 10V.There is no internal clamp for a limitation of the powersupply.

GATEThe GATE pin is the output of the internal driver stage,which has a capability of 1.5A source and sink current.Its gate drive voltage is clamped at 11V (typically).

Pin Symbol Function

1 GND IC Ground

2 ICOMP Current Loop Compensation

3 ISENSE Current Sense Input

4 FREQ Switching Frequency Setting

5 VCOMP Voltage Loop Compensation

6 VSENSE VOUT Sense (Feedback) Input

7 VCC IC Supply Voltage

8 GATE Gate Drive Output

1

6

7

8

4

3

2

5

GATEGND

ICOMP

ISENSE

VCC

VSENSE

FREQ VCOMP

Package P-DIP-8-4 / P-DSO-8-3

Preliminary Datasheet 5 23 Oct 2002

PFC-CCMICE1PCS01/G

Representative Block diagram

Preliminary Data

2 Representative Block diagram

Figure 2 Representative Block diagram

ICE

1PC

S01

/G

85 ..

. 265

VA

C

Vou

t

auxi

liary

sup

ply

300n

sC

21.

5V

-1.4

3x

OT

A3

2.5V

ISE

NS

E

GA

TE

VS

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SE

VC

C

FR

EQ

C1

VC

OM

P

OT

A2

ICO

MP

5V

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lt

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LOV

CC 0.8V

GN

D

PW

MC

ompa

rato

r

Ram

p G

ener

ator

Var

iabl

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scill

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r-cu

rren

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ompa

rato

r

Deg

litch

er

PW

M L

ogic

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e D

river

unde

rvol

tage

lock

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open

-loop

pro

tect

Vol

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Blo

ck

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t

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k C

urre

nt L

imit

Cur

rent

Loo

p

Non

linea

rG

ain

C3

C4

OT

A1

5V

+/−

25µA

, 40

µS

+/−5

0µA

1mS

R1

R5

L1

C2

R3

R4

C3

C5

C4R

6

R2

S2

Vin

D1

Fau

lt

4.75

V5.

25V

1 V

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rent

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pam

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C C

LK

200n

s

R S R S

Pro

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Logi

c

C1

RF

I Filt

erD

2 ...

D5

Preliminary Datasheet 6 23 Oct 2002

PFC-CCMICE1PCS01/G

Preliminary Data

Functional Description3 Functional Description

3.1 General

The ICE1PCS01/G is a 8 pin control IC for power factorcorrection converters. It comes in both DIP and DSOpackages and is suitable for wide range line inputapplications from 85 to 265 VAC. The IC supportsconverters in boost topology and it operates incontinuous conduction mode (CCM) with averagecurrent control.The IC operates with a cascaded control; the innercurrent loop and the outer voltage loop. The innercurrent loop of the IC controls the sinusoidal profile forthe average input current. It uses the dependency ofthe PWM duty cycle on the line input voltage todetermine the corresponding input current. This meansthe average input current follows the input voltage aslong as the device operates in CCM. Under light loadcondition, depending on the choke inductance, thesystem may enter into discontinuous conduction mode(DCM). In DCM, the average current waveform will bedistorted but the resultant harmonics are still lowenough to meet the Class D requirement of IEC 1000-3-2.The outer voltage loop controls the output bus voltage.Depending on the load condition, OTA1 establishes anappropriate voltage at VCOMP pin which controls theamplitude of the average input current.The IC is equipped with various protection features toensure safe operating condition for both the systemand device. Important protection features are namelyBrown-out protection, Current Limitation and OutputUnder-voltage Protection.

3.2 Power Supply

An internal under voltage lockout (UVLO) blockmonitors the VCC power supply. As soon as it exceeds11V and the voltage at pin 6 (VSENSE) is >0.8V, the ICbegins operating its gate drive and performs its Soft-Start as shown in Figure 3..

Figure 3 State of Operation respect to VCC

If VCC drops below 10V, the IC is off. The IC will thenbe consuming typically 200µA, whereas consuming10mA during normal operation.The IC can be turned off and forced into standby modeby pulling down the voltage at pin 6 (VSENSE) to lowerthan 0.8V. The current consumption is reduced to 2mAin this mode.

3.3 Start-up (Soft-Start)

Figure 4 and 5 show the operation of OTA1 duringstartup. It sources a constant 10µA into thecompensation network at pin 5 (VCOMP). The voltageat this pin rises linearly and so does the amplitude ofthe input current. As soon as the output voltage VOUTreaches 80% of its rated level, the startup procedure isfinished and the normal voltage control takes over. Innormal operation, the IC operates with a highermaximum current at OTA1 and therefore with a highervoltage loop gain in order to improve the dynamicbehavior of the device..

Figure 4 Soft Start Circuit

Figure 5 Soft Start with controlled current

The advantage of this technique is a soft-start functionwith lower stress for the boost diode but without the riskof audible noise.

VCC

VVSENSE> 0,8 V

VVSENSE< 0,8 V

11 V

10 V

t

OFFSoftstart

Open loop/Standby

NormalOperation

IC'sState

OFF

VVSENSE> 0,8 V

NormalOperation

VCOMP

C5C4

VSENSE

OTA15V

ICE1PCS01/G

C3

Open-LoopProtect (OLP)

0.8V

R3 + R4R4

x VOUT )(

10µA duringSoft Start

R6

S1

4.0V

Soft Start

Soft Start Normal Operation

av(IIN)

VOUT < 80% rated V OUT > 80% rated

t

Preliminary Datasheet 7 23 Oct 2002

PFC-CCMICE1PCS01/G

Functional Description

Preliminary Data

3.4 System Protection

The IC provides several protection features in order toensure the PFC system in safe operating range.Depending on the input line voltage (VIN) and outputbus voltage (VOUT), Figure 6 and 7 show the conditionswhen these protections are active.

Figure 6 VIN Related Protection Features

Figure 7 VOUT Related Protection Features

The following sections describe the functionality ofthese protection features.

3.4.1 Brown-Out Protection (BOP)Brown-out occurs when the input voltage VIN fallsbelow the minimum input voltage of the design (i.e. 85Vfor universal input voltage range) and the VCC has notentered into the VCCUVLO level yet. For a system withoutBOP, the boost converter will increasingly draw ahigher current from the mains at a given output powerwhich may exceed the maximum design values of theinput current. The ICE1PCS01/G limits internally thecurrent drawn from the mains and therefore also limitsthe input power. The difference of input and outputpower will result in decreasing output voltage. If thecondition prolongs, the decreasing VOUT will terminatein output under voltage condition (OUV, 50% of rated),and the IC will be shut down (See section 3.4.5).Figure 8 shows the occurrence of BOP in respect to theISENSE voltage.

Figure 8 BOP, SOC and PCL Protection as functionof VISENSE

The VIN threshold for BOP to occur is dependent on thevoltage at ISENSE and thus the output power. Therated output power with a minimum VIN (VINMIN) is

Due to the internal parameter tolerance, the maximumpower with VINMIN before BOP occurs is

And the BOP takes over the normal operation underrated output power latest at an input voltage of

3.4.2 Soft Over Current Control (SOC)The IC is designed not to support any output powerthat corresponds to a voltage lower than -0.7V at theISENSE pin. A further increase in the inductor current,which results in a lower ISENSE voltage, will activatethe Soft Over Current Control (SOC). This is a softcontrol as it does not directly switch off the gate drivelike the PCL. It acts on the nonlinear gain block to resultin a reduced PWM duty cycle.

3.4.3 Peak Current Limit (PCL)The IC provides a cycle by cycle peak current limitation(PCL). It is active when the voltage at pin 3 (ISENSE)reaches -1.05V. This voltage is amplified by OP1 by afactor of -1.43 and connected to comparator C2 with areference voltage of 1.5V as shown in Figure 9. Adeglitcher with 300ns after the comparator improvesnoise immunity to the activation of this protection

t

VINMIN(1)

VIN (VAC)

VCC > VCCUVLO

NormalOperation IC OFFBOP

VCC<VCCUVLO

(1) VINMIN where BOP activates depends on the output power

IC’sState

t

VOUT

PCL / SOC

16%

50%

100%

OLP OLPOUV

105%

OVP

VOUT,Rated

VISENSE-0.6V -0.7V -1.05V

NormalOperation

SOC PCL

POUT(rated)

BOPIC’sState

0

(BOP occurs at VISENSE = -0.6V Max)

POUT(max)

POUT rated( ) VINMIN0.6

R1 2⋅-------------------×=

POUT max( ) VINMIN0.7

R1 2⋅-------------------×=

VBOPMAX POUT rated( ) R1 2⋅0.7

-------------------×=

Preliminary Datasheet 8 23 Oct 2002

PFC-CCMICE1PCS01/G

Functional Description

Preliminary Data

.

Figure 9 Peak Current Limit (PCL)

3.4.4 Open Loop Protection / Input UnderVoltage Protect (OLP)

Whenever VSENSE voltage falls below 0.8V, orequivalently VOUT falls below 16% of its rated value, itindicates an open loop condition (i.e. VSENSE pin notconnected) or an insufficient input voltage VIN fornormal operation. In this case, most of the blocks withinthe IC will be shutdown. It is implemented usingcomparator C3 with a threshold of 0.8V as shown in theIC block diagram in Figure 2.

3.4.5 Output Under Voltage Detection (OUV)In the event of main interrupt or brown-out condition,the PFC system is not able to deliver the rated outputpower. This will cause the output voltage VOUT to dropbelow its rated value. The IC provides an output undervoltage detection that checks if VOUT is falling below50% of its rated value. Comparator C4 as shown in thedevice block diagram (Figure 2) senses the voltage atpin 6 (VSENSE) with a reference of 2.5V. If comparatorC4 trips, the IC will be shut down as in OLP. The IC willbe ready to restart if there is sufficient VIN to pull VOUTout of OLP.

3.4.6 Over-Voltage Protection (OVP)Whenever VOUT exceeds the rated value by 5%, theover-voltage protection OVP is active as shown inFigure 7. This is implemented by sensing the voltage atpin VSENSE with respect to a reference voltage of5.25V. A VSENSE voltage higher than 5.25V willimmediately reduce the output duty cycle, bypassingthe normal voltage loop control. This results in a lowerinput power to reduce the output voltage VOUT.

3.5 Frequency Setting

The switching frequency of the PFC converter can beset with an external resistor R5 at FREQ pin. The pinvoltage VFREQ is typically 2.5V. The correspondingcapacitor for the oscillator is integrated in the deviceand the R5/frequency relationship is given at the

“Electrical Characteristic ” section. Therecommended operating frequency range is from50kHz to 250kHz. As an example, a R5 of 33kΩ at pinFREQ will set a switching frequency FSW of 125kHztypically.

3.6 Average Current Control

3.6.1 Complete Current LoopThe complete system current loop is shown in Figure10.

Figure 10 Complete System Current Loop

It consists of the current loop block which averages thevoltage at pin ISENSE, resulted from the inductorcurrent flowing across R1. The averaged waveform iscompared with an internal ramp in the ramp generatorand PWM block. Once the ramp crosses the averagewaveform, the comparator C1 turns on the driver stagethrough the PWM logic block. The Nonlinear Gainblock defines the amplitude of the inductor current. Thefollowing sections describe the functionality of eachindividual blocks.

3.6.2 Current Loop CompensationThe compensation of the current loop is done at theICOMP pin. This is the OTA2 output and a capacitor C3has to be installed at this node to ground (see Figure10). Under normal mode of operation, this pin gives avoltage which is proportional to the averaged inductorcurrent. This pin is internally shorted to 5V in the eventof IC shuts down when OLP and UVLO occur.

3.6.3 Pulse Width Modulation (PWM)The IC employs an average current control scheme incontinuous conduction mode (CCM) to achieve thepower factor correction.

ISENSE

ICE1PCS01/G

R1

R2

IINDUCTOROP1

1.43x

Current Limit

300nsC2

Deglitcher

Turn OffDriver

1.5VFull-waveRectifier

RS

ICE1PCS01/G

VoutL1

C2

R3

R4

GateDriver

D1From

Full-waveRetifier

GATE

R1R2

OTA2

ICOMP

5V

Current LoopCompensation

Current Loop

NonlinearGain

+/−50µ A1mS

C3S2

Fault

ISENSE

C1

PWMComparator

PWM Logic

Q

Input FromVoltage Loop

voltage

proportional to

averaged

Inductor current

Preliminary Datasheet 9 23 Oct 2002

PFC-CCMICE1PCS01/G

Functional Description

Preliminary Data

Assuming the voltage loop is working and outputvoltage is kept constant, the off duty cycle DOFF for aCCM PFC system is given as

From the above equation, DOFF is proportional to VIN.The objective of the current loop is to regulate theaverage inductor current such that it is proportional tothe off duty cycle DOFF, and thus to the input voltageVIN. Figure 11 shows the scheme to achieve theobjective.

Figure 11 Average Current Control in CCM

The PWM is performed by the intersection of a rampsignal with the averaged inductor current at pin 5(ICOMP). The PWM cycle starts with the Gate turn offfor a duration of TOFFMIN (200ns typ.) and the ramp iskept discharged. The ramp is then allowed to rise afterTOFFMIN expires. The off time of the boost transistorends at the intersection of the ramp signal and theaveraged current waveform. This results in theproportional relationship between the average currentand the off duty cycle DOFF.Figure 12 shows the timing diagrams of TOFFMIN and thePWM waveforms.

Figure 12 Ramp and PWM waveforms

3.6.4 Nonlinear Gain BlockThe nonlinear gain block controls the amplitude of theregulated inductor current. The input of this block is thevoltage at pin VCOMP. This block has been designedto support the wide input voltage range (85-265VAC).

3.7 PWM Logic

The PWM logic block prioritizes the control inputsignals and generates the final logic signal to turn onthe driver stage. The speed of the logic gates in thisblock, together with the width of the reset pulse TOFFMIN,are designed to meet a maximum duty cycle DMAX of97% at the GATE output under 125kHz of operation.In case of high input currents which result in PeakCurrent Limitation, the GATE will be turned offimmediately and maintained in off state for the currentPWM cycle. The signal Toffmin resets (highest priority,overriding other input signals) both the current limitlatch and the PWM on latch as illustrated in Figure 13.

Figure 13 PWM Logic

3.8 Voltage Loop

The voltage loop is the outer loop of the cascadedcontrol scheme which controls the PFC output busvoltage VOUT. This loop is closed by the feedbacksensing voltage at VSENSE which is a resistive dividertapping from VOUT. The pin VSENSE is the input ofOTA1 which has an internal reference of 5V. Figure 14shows the important blocks of this voltage loop.

3.8.1 Voltage Loop CompensationThe compensation of the voltage loop is installed at theVCOMP pin (see Figure 14). This is the output of OTA1and the compensation must be connected at this pin toground. The compensation is also responsible for thesoft start function which controls an increasing ACinput current during start-up.

DOFF

VIN

VOUT--------------=

t

ave(IIN) at ICOMPramp profile

GATEdrive

TOFFMIN

200ns

VCREF(1)

VRAMP

PWM

rampreleased

PWM cycle

(1) VCREF is a function of V ICOMP

t

G1

RS

L1

RS

L2

Peak Current Limit

Current LoopPWM on signal

Toffmin200ns

Current LimitLatch

PWM onLatch

HIGH =turn GATE on

Q

Q

Preliminary Datasheet 10 23 Oct 2002

PFC-CCMICE1PCS01/G

Functional Description

Preliminary Data

Figure 14 Voltage Loop

3.8.2 Enhanced Dynamic ResponseDue to the low frequency bandwidth of the voltageloop, the dynamic response is slow and in the range ofabout several 10ms. This may cause additional stressto the bus capacitor and the switching transistor of thePFC in the event of heavy load changes.The IC provides therefore a “window detector” for thefeedback voltage VVSENSE at pin 6 (VSENSE).Whenever VVSENSE exceeds the reference value (5V)by +5%, it will act on the nonlinear gain block which inturn affect the gate drive duty cycle directly. Thischange in duty cycle is bypassing the slow changingVCOMP voltage, thus results in a fast dynamicresponse of VOUT.

3.9 Output Gate Driver

The output gate driver is a fast totem pole gate drive. Ithas an in-built cross conduction currents protectionand a Zener diode Z1 (see Figure 15) to protect theexternal transistor switch against undesirable overvoltages. The maximum voltage at pin 8 (GATE) istypically clamped at 11V.

Figure 15 Gate Driver

The output is active HIGH and at VCC voltages belowthe under voltage lockout threshold VCCUVLO, the gatedrive is internally pull low to maintain the off state.

VCOMP

VSENSE

C5C4

R6

OTA15V

VIN

Av(I IN )Nonlinear

Gain

t

ICE1PCS01/G

VoutL1

C2

R3

R4

Gate DriverCurrent Loop

+PWM Generation

D1FromFull-wave

Retifier

GATE

GATE

ExternalMOSZ1

VCC

Gate DriverPWM LogicHIGH to turnon LV

* LV: Level Shift

ICE1PCS01/G

Preliminary Datasheet 11 23 Oct 2002

PFC-CCMICE1PCS01/G

Electrical Characteristics

Preliminary Data

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destructionof the integrated circuit.

4.2 Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VCC -0.3 22 V

FREQ Voltage VFREQ -0.3 7 V

ICOMP Voltage VICOMP -0.3 7 V

ISENSE Voltage VISENSE -24 7 V

VSENSE Voltage VVSENSE -0.3 7 V

VCOMP Voltage VVCOMP -0.3 7 V

GATE Voltage VGATE -0.3 22 V Clamped at 11.5V if driveninternally.

Junction Temperature Tj -40 150 °C

Storage Temperature TS -55 150 °C

Thermal ResistanceJunction-Ambient for DSO-8-3

RthJA (DSO) - 185 K/W P-DSO-8-3

Thermal ResistanceJunction-Ambient for DIP-8-4

RthJA(DIP) - 90 K/W P-DIP-8-4

ESD Protection VESD - 2 kV Human Body Model1)

1) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

Parameter Symbol Limit Values Unit Remarks

min. max.

VCC Supply Voltage VCC VCCUVLO 21 V

Junction Temperature TJCon -40 150 °C

Preliminary Datasheet 12 23 Oct 2002

PFC-CCMICE1PCS01/G

Electrical Characteristics

Preliminary Data

4.3 Characteristics

4.3.1 Supply SectionNote: The electrical characteristics involve the spread of values guaranteed within the specified supply voltage

and junction temperature range TJ from – 40 °C to 150°C.Typical values represent the median values,which are related to 25˚C. If not otherwise stated, a supply voltage of VCC =15V is assumed .

4.3.2 Variable Frequency Section

4.3.3 Variable Frequency and PWM Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

VCC Turn-On Threshold VCCon 10.5 11.0 11.5 V

VCC Turn-Off Threshold/Under Voltage Lock Out

VCCUVLO 9.5 10.0 10.5 V

VCC Turn-On/Off Hysteresis VCChy 0.5 V

Start Up CurrentBefore VCCon

ICCstart 200 µA VVCC=VVCCon -0.1V

Operating Current with active GATE ICCHG 10.5 mA R5 = 33kΩCL= 4.7nF

Operating Current with inactive GATE ICCH 10 mA R5 = 33kΩVVCOMP= 0V, VVSENSE= 5V,VICOMP= 6.4V

Operating Current during Standby ICCStdby 2 mA R5 = 33kΩVVSENSE= 0.5V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Switching Frequency (Typical) FSW125 125 kHz R5 = 33kΩ

Switching Frequency (Min.) FSWmin 50 kHz R5 = 82kΩ

Switching Frequency (Max.) FSWmax 250 kHz R5 = 15kΩ

Voltage at FREQ pin VFREQ 2.5 V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Max. Duty Cycle DMAX 97 % At FSW = 125kHz

Min. Duty Cycle DMIN 0 % VVCOMP= 0VVVSENSE= 5VVICOMP= 6.4V

Min. Off Time TOFFMIN 200 ns

Preliminary Datasheet 13 23 Oct 2002Preliminary Data

PFC-CCMICE1PCS01/G

Electrical Characteristics

Preliminary Data

4.3.4 System Protection Section

4.3.5 Current Loop Section

4.3.6 Voltage Loop Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

Open Loop Protection (OLP)VSENSE Threshold

VOLP 0.8 V

Peak Current Limitation (PCL)ISENSE Threshold

VPCL -1.05 V

Soft Over Current Control (SOC)ISENSE Threshold

VSOC -0.7 V

Output Under Voltage Detection (OUV)VSENSE Threshold

VOUV 2.5 V

Output Over-Voltage Protection (OVP) VOVP 5.25 V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

OTA2 Transconductance Gain Gm2 1 mS

OTA2 Max. Source/Sink CurrentUnder Normal Operation

IOTA2 +/- 50 µA

ICOMP Voltage during OLP VICOMPF 5 V VVSENSE= 0.5V

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

OTA1 Transconductance Gain Gm1 40 µS

OTA1 Max. Source/Sink CurrentUnder Normal Operation

IOTA1 +/- 25 µA

OTA1 Max. Source/Sink CurrentUnder Soft Start

IOTA1 +/- 10 µA

OTA1 Reference Voltage VOTA1 4.9 5.0 5.1 V

Enhanced Dynamic ResponseVSENSE High ThresholdVSENSE Low Threshold

VHiVLo

5.254.75

VV

VCOMP Voltage during OLP VVCOMPF 0.2 V VVSENSE= 0.5V

Preliminary Datasheet 14 23 Oct 2002

PFC-CCMICE1PCS01/G

Electrical Characteristics

Preliminary Data

4.3.7 Driver Section

Parameter Symbol Limit Values Unit Test Condition

min. typ. max.

GATE Low Voltage VGATEL - - 1.2 V VCC = 5 VIGATE = 5 mA

- - 1.5 V VCC = 5 VIGATE = 20 mA

- 0.8 - V IGATE = 0 A

- 1.6 2.0 V IGATE = 20 mA

-0.2 0.2 - V IGATE = -20 mA

GATE High Voltage VGATEH - 11.5 - V VCC = 20VCL = 4.7nF

- 10.5 - V VCC = 11VCL = 4.7nF

- 7.5 - V VCC = VVCCoff + 0.2VCL = 4.7nF

Rise Time tR 20 - ns VGATE = 2V ... 9VCL = 4.7nF

Fall Time tF 20 - ns VGATE = 2V ... 9VCL = 4.7nF

Preliminary Datasheet 15 23 Oct 2002Preliminary Data

PFC-CCMICE1PCS01/G

Outline Dimension

Preliminary Data

5 Outline Dimension

Figure 16 P-DIP-8-4 Outline Dimension

Figure 17 P-DSO-8-3 Outline Dimension

Dimensions in mm

P-DIP-8-4(Plastic Dual In-Line Package)

Dimensions in mm

P-DSO-8-3(Plastic Dual Small Outline)

Preliminary Datasheet 16 23 Oct 2002

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