PPAP qual results PCN15321-rev2 - NXP … · Appendix 3 Temperature ... -TEST @ RH 3 units per Voltage level. 4 voltage ... TLS. TM Freescale . Microsoft PowerPoint - PPAP_qual_results_PCN15321-rev2

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Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t

he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony

are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,

ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ

Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks

of Freescale Semiconductor, Inc. All other product or service names are the property

of their respective owners. © 2011 Freescale Semiconductor, Inc.

► Freescale was informed thru a customer quality issue that an unexpected reset was generated when some cQuest devices wake up from stop mode. The Quest/cQuest (MM912F634CVx) is an integrated single package solution that integrates an HCS12 microcontroller with a SMARTMOS analog control IC (Calango).

► Root cause investigation identified a design issue on the analog die (Calango), where Stop Mode Wake-Up generates a Reset and set WUR bit into RSR register. After a transition from Stop mode to Normal mode due to a wake up event, the device may generate a Reset. If this occur, WUR bit into RSR register is set until reading of RSR register. This behavior will affect parts with VDD in stop mode below LVR in normal mode.

TM

Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore

and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a

Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.

All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.

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►The issue is impacting other dual die devices with Calango die embedded, ie. MM912G634 (CQUEST48K, QUICKSILVER 48) and MM912H634 (QUICKSILVER 64).

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• Root cause has been identified

− During the transition from stop mode to normal mode, the monitoring of LVR

(Low Voltage Reset) of normal mode is activated too early.

• Qualification of the design change has been completed.

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RevC low voltage reset management

is based on bias OK signal and fixed

delay only � issue if bias OK is

established (more than 3 us) before

the lvr (normal mode) is high the IC

will see low voltage reset activated

RevD low voltage reset management

is based only on filtered low voltage

reset (normal mode) � no lvr

transition before lvr normal mode is

established

Change list: 1. Use LVR normal rising edge to change

LVR Mux selection from stop to normal

mode.

2. Add RC filter at LVR Normal mode- use

RC (200k, 1.35pF) spare devices. New Metal wires

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• Change impacts Metal1, Via1, Metal2, Via2,

Metal3.

• Metal4, passivation and polyimide are the same

• No change in die size

3. M3 test points added on critical wires.

4.Change revision Id

Pad PTB0 –PIN#26 Pad PTB1 –PIN#27

Title: Qualification strategy on QUEST and CQUEST32K (MM912F634DVxAx)

Ambient Operating Temperature range: Grade 2 (-40°C to 105°C)

Name: QUEST/CQUEST32K

Customer PN: Various

The qualification on the MM912F634DVxAx (D-version) was performed based on the changes comparedto the previously successfully qualified part: MM912F634CVxAx (C-version). The difference betweenthese two product revisions are the design changes on the analog die. No changes were performed on the

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these two product revisions are the design changes on the analog die. No changes were performed on themicrocontroller or the package.

Qualification stressing was performed on:- Quest: 912F634DVxAE/R2 (exposed pad version)- cQuest32k: 912F634DVxAP/R2 (non-exposed pad version)

Objective:Qualification Results for Calango P2.5 + CrowntailFreescale PN:

Part Name:

Calango P2.5 (analog die) in dual die product

cQuest32k/Quest

MM912F634

Customer

Name(s):

PN(s):

Various Plan or Results:

Revision # & Date:Results

2.0 ; 12 September 2012

Technology:

Package:

SmartMOS8MV

LQFP 48 7x7 mm Exposed pad/ LQFP 48 7x7 mm (non-

exposed pad) Design Engr:

Phone #:

Arlette Marty -R16192

+ 33-561191003 QUARTZ Tracking #:218288/218289

Fab / Assembly /

Final Test Sites:

CHD for Calango, ATMC for Crowntail and TJN for

Assy/Test

Product Engr:

Phone #:

Y.H. Zhang - B11287

+86-22-85684630 (Signature/Date shown below may

be electronic)

Maskset#:

Rev#:

Calango P2.3/P2.4 (old): 4M91W/5M91W

Calango P2.5 (new): 6M91W

Crowntail: 4M33G

Prod. Package

Engr:

Phone #:

Garry Ge - B17616

+86-22-85684585

PPE Approval (for

DIM/BOM results)

Signature & Date:

Die Size (in mm)

W x L x T

M91W: 1984 x 3188 - Calango

M33G: 2030 x 2390 - Crowntail

NPI PRQE:

Phone #:Ylva Adner - R48929

+498992103- 683

NPI PRQE Approval

Signature & Date:

Ylva Adner

17Sep2012

Part Operating

Temp. Grade: Grade 2 -40°C to +105°C Trace/DateCode:

LOT A

Wafer :

Assy :

LOT B

Wafer :

Assy :

LOT C

Wafer :

Assy :

CAB Approval

Signature & Date:

9/17/2012

12110645M

Target Dates

Test Start:

Test Finish: Test Program Name:

Customer Approval

Signature & Date:

This testing is performed by TJN Freescale Reliability Lab unless otherwise noted in the Comments.

GROUP A - ACCELERATED ENVIRONMENTAL STRESS TESTS

Stress Test Reference Test Conditions

End Point

Requirements/ Acceptance

Minimum Sample

Size(Note 1)

# of Lots

Total Units

including

spares

Results

Lot ID-(#Rej/SS)

NA=Not Applicable

Comments(Note 2)

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Acceptance

criteria(Note 1) spares NA=Not Applicable

(Note 2)

PC

JESD22-

A113

J-STD-020

Preconditioning (PC) :PC required for SMDs only.

MSL 3 @ 260°C, +5/-0°C

TEST @ R All surface mount devices prior to TC. See previous qualification results

HAST

JEDEC

JESD22

-A101 or

A110

Biased HAST 130°C/85%RH for 96hours TEST @ RH 0 0 0 NA/ See previous qualification results

UHST

JEDEC

JESD22

-A102,A118

or A101

Unbiased HAST 130°C/85%RH for 96

hours

TEST @ R 0 0 0 N/A See previous qualification results

TC

JESD22-

A104

AEC Q100-

Appendix 3

Temperature Cycle (TC):PC before TC (for SMDs only): Required

TC = -50°C to 150°C for 500 cycles. 1000

cycles performed for information only.

TEST @ H 77 1 lot Quicksilver 77 PASS

0/77

Performed on Quicksilver. Results:

Pass 0/77 1000TC

HTSL

JESD22-

A103High Temperature Storage Life (HTSL):150°C for 1000hrs

TEST @ RH 0 0 0 N/A See previous qualification results

TEST GROUP B - ACCELERATED LIFETIME SIMULATION TESTS

Stress TestReferenc

eTest Conditions

End Point

Requireme

nts/

Acceptance

criteria

Minimum

Sample Size

(Note 1)

# of Lots

Total Units

including

spares

Results

Lot ID-(#Rej/SS)

NA=Not Applicable

Comments

(Note 2)

HTOL

JESD22-

A108

High Temperature

Operating Life (HTOL):

Ta = 125°C for 408hrs .

TEST

@RHC

77 1 77 PASS

0/77

Lot A: cQuest32k

ELFR

AEC

Q100-

008

Early Life Failure Rate

ELFR):

TEST @ RH 0 0 0 N/A See previous

qualification results

TEST GROUP C - PACKAGE ASSEMBLY INTEGRITY TESTS

Stress TestReferenc

eTest Conditions

End Point

Requireme

nts

Minimum

Sample Size

(Note 1)

# of Lots

Total Units

including

spares

Results

Lot ID-(#Rej/SS)

NA=Not Applicable

Comments

(Note 2)

WBS

AEC

Q100-

001

Wire Bond shear (WBS) Cpk = or >

1.67

0 0 0 N/A See previous


WBP

MilStd88

3-

Wire Bond Pull (WBP):

Cond. C or D

Cpk = or >

1.67



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WBP 3-

2011

Cond. C or D 1.67 qualification results

SD

JESD22-

B102

Solderability (SD):

8hr.(1 hr. for Au-plated leads)

Steam age prior to test.

If production burn-in is done,

samples must also undergo

burn-in prior to SD.

>95% lead

coverage of

critical

areas



PDJESD22-

B100

Physical Dimensions(PD):

PD per FSL 98A drawing

Cpk = or >

1.67



DIM

&

BOM

Dimensional (DIM):

PPE to verify PD results

against valid 98A drawing.

BOM Verification (BOM):

PPE to verify qual lot ERF

BOM is accurate.

See previous


TEST GROUP E - ELECTRICAL VERIFICATION TESTS

Stress Test Reference Test ConditionsEnd Point

Requirements

Minimum

Sample Size

(Note 1)

# of Lots

Total Units

including

spares

Results

Lot ID-(#Rej/SS)

NA=Not Applicable

Comments

(Note 2)

TEST

Freescale

48A

Pre- and Post Functional /

Parametrics (TEST):

Test software shall meet

requirements of AEC-Q100-007.

Testing performed to the limits of

device specification in temperature

and limit value.

0 Fails All All All BI requirement: 125C/12hrs

prior to test

HBM

AEC-Q100-

002

ElectroStatic Discharge/

Human Body Model Classification

(HBM):

Required :

Test @

- LIN (DGND, PGND, AGND, and

LGND shorted) : 8000V

- VS1, VS2, VSENSE, Lx: 4000V

- HSx: 3000V

- All other Pins: 2000V

See AEC-Q100-002 for

classification levels.

-TEST @ RH 3 units per

Voltage level. 4

voltage levels.

2 24 PASS

0/24

Lot A: cQuest32k

Lot B: Quest

Performed in TLS.

MM

AEC-Q100-

003


Machine Model Classification

m(MM):

Required :

TEST @ RH 3 units per

Voltage level

2 6 PASS

0/6

Lot A: cQuest32k

Lot B: Quest

Performed in TLS.

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MM Required :

Test @ 200V

See AEC-Q100-003 for

classification levels.

CDM

AEC-Q100-

011


Charged Device Model

Classification (CDM):

Test @ 500, 750V

TEST @ RH

Corner pins

=/> 750V;

All other pins

=/> 500V

3 units per

Voltage level. 2

Voltage levels

2 12 PASS

0/12

Lot A: cQuest32k

Lot B: Quest

LU

JESD78

plus

AEC-Q100-

004

Latch-up (LU):

Test per JEDEC JESD78 with the

AEC-Q100-004 requirements.

Ta= Maximum operating

temperature

Vsupply = Maximum operating

voltage

TEST @ RH 6 2 12 PASS

0/12

Lot A: cQuest32k

Lot B: Quest

Performed in TLS.

ED

AEC-Q100-

009,

Freescale

48A spec

Electrical Distribution (ED) TEST @ RHC

Cpk = or >

1.67

30 2 60 PASS Lot A: Quest

Lot B: cQuest32k

Two different wafer lots of

Calango used.

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Documents

PPAP qual results PCN15321-rev2 - NXP … · Appendix 3 Temperature ... -TEST @ RH 3 units per Voltage level. 4 voltage ... TLS. TM Freescale . Microsoft PowerPoint - PPAP_qual_results_PCN15321-rev2