04/19/23 1

Power Management for Chip-level

Multiprocessing Processors

Kai Ma

04/19/23 2

Background

To get better performance

1. Scale frequency (fast)

2. On-chip resource replication (parallel) Chip-MultiProcessing vs Simultaneous MultiThreading

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SMT vs CMP

SMT CMP

Technique Duplicate resources on one core

Duplicate cores on one die

Target Instruction level parallelism

Thread level parallelism

Implementation Basically redesign Reuse proven design

Area Small transistor increase

Proportionately to core number

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Other justification for CMP

Memory wall, ILP wall, Power wall Higher cache coherency circuitry rate Signal integrity Future: Many cores (many specialized cores )

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Power management for CMP

Reduce operating costs for energy and cooling Prolong battery life for portable and embedded systems Reduce cooling requirement Meet scalable performance target Heat dissipation and hotspot

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Outline

1. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

Canturk Isci*, Alper Buyuktosunoglu*, Chen-Yong Cher*, Pradip Bose* and Margaret Martonosi

*IBM T.J. Watson Research Center Department of Electrical Engineering

Yorktown Heights Princeton University

2. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

Radu Teodorescu and Josep Torrellas

Department of Computer Science University of Illinois at Urbana-Champaign

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Outline

An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget

1. Contribution

2. Global Power Management

3. Global Power Management Policies: core modes, power and performance matrix

4. Experimental Result and Evaluation

5. Conclusion

6. Critique

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Contribution

Introduce a global power management

Develop a static power management analysis tool

Evaluate different policies for CMP power management

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Global Power Management

Monitor the power and set working mode of each core

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Global Power Management Policies

Priority: Slow down the core runs low priority task

PullhiPushLo: Speedup the low power core and slow down the high power core.

MaxBIPS: Predict and choose power mode combination

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Core Power Modes

Underlying mechanism: DVFS Overhead: Order of microseconds Performance Degradation: Elapsed execution time for

benchmark

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Power and BIPS Matrices

Power BIPS

Turbo 1 1*(500/507)

Eff1 1*0.95^3 1*0.95*(500/513)

Eff2 1*0.85^3 1*0.85*(500/520)

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Experimental Methodology

SPEC CPU2000 benchmark A trace-based CMP analysis tool is incorporated with

IBM’s Turandot simulator Mode switch (500ns) and Statistics collection (50ns) During mode switch, no instruction execution, power is

consumed

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Static vs Dynamic

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Policy and Budget Curve

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Power Saving

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Power Management Result

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Trends under CMP Scaling

The difference between MaxBIPS and oracle decreases with core number increasing

Increasing core numbers has smaller impact on MaxBIPS

CMP scales favor static per-core management over chip-wide DVFS

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Conclusion

Global management is preferred

Dynamic management is preferred

MaxBIPS is efficient

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Critique

MaxBIPS: Prediction is superlinearly dependent on the number of modes and core

Power performance estimation matrix: transition penalty

Not consider temperature

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Outline

Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors

1. Background 2. Contribution 3. Algorithm 4. System Implementation 5. Evaluation 6. Conclusion 7. Critique

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Background

For CMP, with-in die process variation impacts:

Static power consumption

Maximum frequency

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Contribution

Propose variation-aware algorithms for application scheduling

Complement these algorithms with variation-aware DVFS

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CMP Configuration

High level frequency and DVFS policy

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Algorithms

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Linear Programming

A technique for optimization of a linear objective function, subject to linear equality and linear inequality constraints

c and b are known vectors, A is a known matrix, x represents variables vector

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Power Mode Selection: LinOpt TP : average throughput N: core number i : from 1 to N a(i) : constant depends on the thread and core v(i): core voltage b(i) and c(i): constants introduced to approximate power-voltage relation

Object function:

Constraints:

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Power Mode Selection: SAnn

Use annealing algorithm to solve the power mode selection problem

SAnn searches all possible combination of core voltage

Compare to LinOpt: More accurate but more costly

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System Implementation

Algorithm runs on a core or a power management unit At OS scheduling interval, OS assigns threads to cores by using

VarF&AppIPC Every 10ms, the LinOpt algorithm runs and sets the cores to correct

power

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Profiling for Implementation

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Evaluation Methodology

Variation:Varius model Power: SESC + Wattch+HotLeakage Temperature: HotSpot Critical Path Model:

1.Calculation path delay: Multiplier like unit

2.Memory: SRAM

3.Interconnection: Cacti

4.Gate delay: Alpha-power law

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Workload

SPEC

Run different applications on different cores

12 billion instructions

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Metrics

Total power Average frequency of active cores Throughput Energy delay-square product (consider Time-to-solution

and energy consumption) Weighted throughput: application’s IPC normalized to the

application’s IPC at reference conditions

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Evaluation

Power and frequency variation on one die

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Uniform Frequency & No DVFS

As the thread number increases, there is no less used core for thread mapping

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NoUniform Frequency & No DVFS

Different cores run at different frequencies, by selecting less used core, they may end up with lower frequency ones.

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NoUniFreq+DVFS

Throughput:

VarF&AppIPC+LinOpt is effective

Power:

throughput gains are high when power targets are low

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LinOpt Granularity

Deviation between power consumed and power target decreases as interval between LinOpt run increases

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Conclusion

With-in die variation substantially impacts static power consumed and maximum frequency

Variation-aware algorithms are proposed and analyzed, LinOpt is efficient

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Critique

How to decouple thread mapping and power mode selection

Static power consumption and dynamic power consumption should be discussed separately

Thread mapping takes place once, thread migration should be considered

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Comparison

MICRO UIUC

Objective Manage CMP processor power

Manage CMP processor power

Core 8 homogeneous Cores (POWER4 like)

20 inhomogeneous Cores (Alpha 21264 like)

Policy Global, Dynamic Global, Dynamic

Algorithm MaxBIPS LinOpt

Methodology Simulation (Turandot) Simulation (SESC)

Benchmark SPEC CPU2000 SPEC

Controller Ad-hoc Ad-hoc