PNX85500 Single Chip LCD TV System · PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame Rate Converter Colin Osborne / Ralf Karge PNX85500 Single Chip LCD TV System

PNX85500 Single Chip LCD TV Systemwith integrated 120Hz HD Frame Rate Converter

Colin Osborne / Ralf KargePNX85500 Single Chip LCD TV SystemHot Chips 2009August, 25, 2009

25-Aug-2009PNX85500 / HotChips / C.Osborne, R. Karge

2

Presentation Outline

Introduction

System Integration– More TV System on a Chip– PNX85500 TV Solution

Design Challenges– Architecture– Memory Bandwidth and Latency– Verification and Emulation

High-lighted Features

Conclusions


3

Introducing the TV550 System

TV550 System comprises the world’s first Digital TV SoC in C045: PNX85500

• Channel demodulators, networking (USB, HDMI, Ethernet, SD card reader), 120 Hz, H.264 HD decoding, advanced Picture Quality Algorithms, etc.

Extremely high level of functional integration

• Full application (networking, H.264 HD decoding, advanced gfx, FRC, …) all on 2x16-bit DDR2 footprint!

Smallest memory requirement for the total system

• Avoid expensive EMI protection with built-in spread-spectrum on both LVDS as well as DDR interfaces

Drives industry’s lowest cost-of-ownership/bill-of-material

• Minimize upfront development costs and time-to-market for global rollout• One development, one PCB line, one test set up

Enables development for global chassis roll out thanks to low system costs


4

Introduction




Conclusions


5

TV550 System Integration

CVBS,Y/C,

RGB L/R

L/R

L,R

YCbCr

NXPPNX8543

MIPS32@300 MHzPixel OSD, TV Control,

HDMI,USB,PC-AVI

DDR2256MB

FLASH128 MB

PNX8543

LVDS-2

CVBS

SPDIF

L,R

Audio Amplifier

DVB-C Channel Decoder

TDA10024

TunerTDA18272

SPDIF

RGB, HV

L/R

PCMCIA

NXPTFA9810

32 bitDDR2-666

TS

Low -IFAnalog IF IP

TDA8296CVBS/SIF

Ethernet MAC

DVB-T Channel Decoder

TDA10048

Silicon Tuner

SwitchTDA9996

CI+

HDMISwitch

HD 1080p 100/120Hz 50/60Hz

NXPPNX5120Frame Rate Conversion

PNX85500

32 bitDDR2-666

DDR2128MB

http://www.amazon.co.jp/%E6%9D%B1%E8%8A%9D-TOSHIBA-SD%E3%82%AB%E3%83%BC%E3%83%89-2GB-%E3%80%90%E6%B5%B7%E5%A4%96%E3%83%91%E3%83%83%E3%82%B1%E3%83%BC%E3%82%B8%E3%80%91/dp/B001AN84OU/ref=sr_1_5?ie=UTF8&s=electronics&qid=1242300097&sr=8-5�


6

TV550 System Integration

CVBS,Y/C,

RGB L/R

L/R

L,R

YCbCr

NXPPNX8543

MIPS32@300 MHzPixel OSD, TV Control,

HDMI,USB,PC-AVI

DDR2256MB

FLASH128 MB

PNX8543

LVDS-2

CVBS

SPDIF

L,R

Audio Amplifier

DVB-C Channel Decoder

TDA10024

TunerTDA18272

SPDIF

PCMCIA

NXPTFA9810

32 bitDDR2-666

TS

Low -IFAnalog IF IP

TDA8296CVBS/SIF

Ethernet MAC

DVB-T Channel Decoder

TDA10048

Silicon Tuner

SwitchTDA9996

CI+

HDMISwitch

HD 1080p 100/120Hz 50/60Hz

NXPPNX5120Frame Rate Conversion

RGB, HV

L/R

PNX85500

32 bitDDR2-666

DDR2128MB

NXPPNX85500

http://www.amazon.co.jp/%E6%9D%B1%E8%8A%9D-TOSHIBA-SD%E3%82%AB%E3%83%BC%E3%83%89-2GB-%E3%80%90%E6%B5%B7%E5%A4%96%E3%83%91%E3%83%83%E3%82%B1%E3%83%BC%E3%82%B8%E3%80%91/dp/B001AN84OU/ref=sr_1_5?ie=UTF8&s=electronics&qid=1242300097&sr=8-5�


7

TV550 – FRC 120Hz FULL HDDVB-T, CI+, PAL/SECAM, IP

TV550

HDMI DIGITAL

AUDIO OUT

DIGITAL

AUDIO IN

HDMI

TFA9810

HDMI

HDMI

PNX8550x

DDR2

128 MB

FLASH

64 MB

CI+

Ethernet

PHY

TDA9996

switch

USB

DDR2

128 MB

TDA18272

Si Tuner


8

TV550 – FRC 120Hz FULL HDDMB-T/ATSC/ISDB-T, PAL/SECAM/NTSC, IP

TV550

HDMI DIGITAL

AUDIO OUT

DIGITAL

AUDIO IN

HDMI

TFA9810

HDMI

HDMI

PNX8550x

DDR2

128 MB

FLASH

64 MB

Ethernet

PHY

TDA9996

switch

USB

TDA18272

Si Tuner

DDR2

128 MB

Channel

Demod

Optional China CI+


9

LVDS_TX

MIPS24K

CAI

MIP

S24K

–C

ontrol Netw

ork

Video Scaler (1)

VideoComposition

Pipe (1)

RW

RW

RW

SPDIF

GPIO

AV

DS

P –

Control N

etwork

HDMI_RX

Audio Decoding

Audio Processor

USBRW

AV-DSPRW

I2C

VideoInput Processor

VideoComposition

Pipe (2)R

DENC

Interrupts

RW

I2SR

BRIDGE

R

2D DrawingRW

Digital VideoDecoder

RWRW

RW

W

Transport Stream Input

PC_AVIRW

FrameRate

Converter

RWW

ETHERNET RW

Video Scaler (2)RW

FLASH_CTRL

W

ChannelDecode

MCU_DDR(32bit)

RW

MPEG DemuxRW

PC_AVI

RW

A

A

R DMA Read

W DMA Write

Key

Scatter/GatherDMA

RW

PC_AVI

MEM_ARB

RTC

GFX_SCALERRW

SPI RW

SD CardRW

R/W

Control Network

RW

PNX85500 Block Diagram

UART

JTAG

RESET

CLOCKS

Interrupts

SYS_CTRL

DM

A N

etwork

DMA Network

Generic Control and InterconnectDigital Broadcast / Transport StreamAudio ProcessingVideo Processing and Graphics


10

Introduction




Conclusions


11

Organizational Complexity

World-wide multi-site project

– UK, Netherlands, Germany, France, India, Israel, USA

Number of IPs– Approx 100 IP blocks

(85% NXP-internal)

Compute infra metrics– 15 TBytes of disk

space– 3 TBytes of RAM for

SoC Integration

CaenSouthampton HamburgChicago

San Jose Eindhoven Haifa Bangalore


12

Integrating many different functions

AnalogueStandardsDecoder

MIPS24K

Digital AudioDecoder

AudioPost -Processing

AudioPresentation

ConnectivityInterfaces

Audio andVideo

Capture

MPEGDemux &

Descrambler

MPEG/H.264Video Decoder

FlexibleVideo Decoder

GraphicsRendering

Picture QualityProcessing

VideoPresentation

Auto PictureControl

Frame RateConversion

Function Examples

Established HW functions Analogue audio/video decoding

High performance HW functions Video scaling & composition

Control processing Generic operating system

Flexible DSP Audio & video feature processing

High performance DSP Motion Accurate Picture Processing


13

Challenging Bandwidth and Latency Needs

AudioProcessor

Digital VideoDecoder

MIPS24K

Critical

EmbeddedControl CPU

Critical Tolerant

FRC Co-processor

Tolerant

FRCProcessor

Critical Tolerant

AVDSPProcessor

Critical

Memory Subsystem with Arbitration and Buffering

Video Comp.Pipe(s)

Tolerant

VideoScaler(s)

Tolorant

Cost pressure only allows 2 x 16 DDR2-1066

• Limiting gross bandwidth to 4.2 Gbytes/sec• Originally the TV550 system was expected to need 64-bit DDR interface

Requiring high-bandwidth and low-latency

• Processors for flexible processing: requiring low-latency to minimise cache miss penalty • Hardware traffic mostly predictable: requiring high-bandwidth

Innovative solutions

• Processors supported by specific arbitration settings in infrastructure• Hardware units and VLIW pre-fetch memory accesses• Local caches/buffers• Video streaming between IP functions


14

Assuring fast Silicon Bring -UpExtensive suite of verification methods

Various abstraction levels in simulation of– IP functionality and connectivity– SoC infrastructure performance

Emulation of representative Software and Hardware

– 300 million gates of IC emulation capacity– System tuning and performance sign-off– 300 - 400 k frames of HD video before

tape out

Advance system software developmentEmulation

All main use-cases had been brought up on the emulator before silicon– Software was ready when silicon arrived– Arbitration and tuning settings had been verified=> Very rapid silicon bring -up


15

PNX85500 Silicon

• TSMC's 45nm Low Power (LP) process technology

• 27 mm Flip Chip BGA Package

• Power Consumption < 7 Watt

• No active cooling required


16

Introduction




Conclusions


17

Complex SoC made up by Complex IPsExample: Video Scaler

VCARMPEG Artefact

Reduction

STDIDe-interlacer

TNRTemporal Noise

Reduction

PCORProjection data for film detector

AHSCHorizontal scaler


18

Complex SoC made up by Complex IPsExample: Video Composition Pipe

PCTIPeaking-based Color Transient Improvement

VSHRVideo Sharpening

SKCRSkin-tone Control

BSKYBlue-Sky

Enhancement

DI2D2-Dimensional

Backlight Dimming


19

Motion Accurate Picture Processing Film Judder Cancellation + Motion Blur Reduction

24 Hz film

A B

Original Movie24 frames per second

A A A BBTypical TVat 50 or 60 framesper second(with ‘movie judder’)

A PNX85500 outputat 120 framesper second; aftermovie judder removal

2 3 4 5 B 7 8 9 10

High quality smooth, natural-looking motion- analysed and created- in real-time, for HD video content- at 120 frames per second


20

Improved Picture Quality at Reduced Power2D Local Dimming Processing

Video input

Video outputBacklight output Perceived outputVideo on backlight

+ =

PNX85500

Histogram

FRC Processor Image Analysis Backlight calculation

Reduce LCD TV’s backlight power by about 50%

Significant increase of contrast and black level

Histogram measurement and pixel processing done in HW-IP

Flexible processing of VLIW processor for image analysis and backlight calculation

VideoGain


21

Introduction




Conclusions


22

ConclusionsPNX85500: the world’s first DTV SoC in 45nm•Very high level of integration •Award-winning 120 Hz processing in front-end TV SoC•Enabling global chassis, single platform

Performance critical•Iterative analysis and optimisation through design cycle•Solving challenging demands on memory latency

Verification challenge•Very high level of integration creates challenges in interdependency and complexity•Extensive use of prototyping using emulation and FPGA

First silicon arrived in Q1 2009 •Successful customer demonstrations within 2 weeks of first silicon!

What’s next?•Higher integration levels, lower system cost•Improved picture quality, increased frame rates and resolution•New video features


23

Questions


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Documents

PNX85500 Single Chip LCD TV System · PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame Rate Converter Colin Osborne / Ralf Karge PNX85500 Single Chip LCD TV System