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Ing. Ing. Zbyn Zbyn ě ě k Bure k Bure š š , Ph.D. , Ph.D. zbynek zbynek . . bures bures @ @ unob unob . . cz cz Mgr. Vojt Mgr. Vojt ě ě ch ch Krm Krm í í č č ek ek vojtec@ vojtec@ ics ics . . muni muni . . cz cz PIC12F629 / 675 Timers PIC12F PIC12F 629 / 675 629 / 675 Timers Timers

PIC12F 629 / 675 PIC12F629 / 675 Timers - is.muni.cz · PIC12F629 / 675 Timers PIC12F 629 / 675. Package. Block diagrams of pins. ... To A/D Converter CLK modes are XT HS, Enable

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Ing. Ing. ZbynZbyněěk Burek Burešš, Ph.D., Ph.D.

zbynekzbynek..buresbures@@unobunob..czczMgr. VojtMgr. Vojtěěch ch KrmKrmííččekek

vojtec@[email protected]

PIC12F629 / 675

Timers PIC12FPIC12F629 / 675629 / 675

Timers Timers

PackagePackage

Block diagrams of pinsBlock diagrams of pins

Timer0 Timer0 -- featuresfeatures

8 bit timer / counter,8 bit timer / counter,

readable and writable,readable and writable,

programmable 8 bit programmable 8 bit prescalerprescaler,,

internal or external clock,internal or external clock,

interrupt on overflow from interrupt on overflow from

0xff 0xff --> 0x00.> 0x00.

Timer0 Timer0 -- block diagramblock diagram

Registers Registers –– Timer0Timer0

Registers Timer0 (cont.)Registers Timer0 (cont.)

Registers summaryRegisters summary

Timer1 Timer1 -- featuresfeatures

16 bit timer / counter,16 bit timer / counter,

readable and writable,readable and writable,

programmable 2 bit programmable 2 bit prescalerprescaler,,

internal or external clock,internal or external clock,

synchronous and asynchronous operations,synchronous and asynchronous operations,

optional external enable bit optional external enable bit

wake up after overflow,wake up after overflow,

interrupt on overflow from interrupt on overflow from

0xffff 0xffff --> 0x0000> 0x0000

Timer1 Timer1 -- block diagramblock diagram

Registers Timer1Registers Timer1

Registers Timer1 (cont.)Registers Timer1 (cont.)