1

Phase-Synchronization Early Epileptic SeizureDetector VLSI Architecture

Karim Abdelhalim, Vadim Smolyakov, Roman GenovDepartment of Electrical and Computer Engineering

University of Toronto, Toronto, CanadaEmail: {karim, svadim, roman}@eecg.utoronto.ca

Abstract—A low-power VLSI processor architecture that com-putes in real time the magnitude and phase-synchronization oftwo input neural signals is presented. The processor is a partof an envisioned closed-loop implantable microsystem for adap-tive neural stimulation. The architecture uses three CORDICprocessing cores that require shift-and-add operations but nomultiplication. The 10-bit processor synthesized and prototypedin a standard 1.2V 0.13µm CMOS technology utilizes 41,000logic gates. It dissipates 3.6µW per input pair, and provides1.7kS/s per-channel throughput when clocked at 2.5MHz. Thepower scales linearly with the number of input channels or thesampling rate. The efficacy of the processor in early epilepticseizure detection is validated on human intracranial EEG data.

Index Terms—Early seizure detection, bivariate digital signalprocessing, biomedical processor, bivariate processing, phase-synchronization, energy-band extraction.

I. I NTRODUCTION

OVER 50 million people worldwide suffer from epilepsy.Approximately one-third of those with epilepsy do not

react well to currently available pharmacological treatmentssuch as antiepileptic drugs [1]. Electrical stimulation hasshown positive results in reducing the frequency of seizures insuch patients with refractory epilepsy [1], [2]. Typically, thestimulation pulses are applied continuously and periodically,which can result in suboptimal treatment efficacy, shorten thebattery life, increase the size of the device and increase the costof the therapy as additional surgical operations are required forbattery replacement [2]. Automated identification of optimaltime instances when an electrical stimulus should be appliedcan help address these issues [3], [4]. In many cases, seizurescan be detected prior to the clinical onset of the seizure. Ithas been widely hypothesized that anticipation of ictal events(i.e., seizures) is critically important for a proper control ofseizures [5], [6]. This is based on the assumption and someevidence [7], [8] that it is easier to stop a seizure by electricalstimulation before or early in its development than when ithas already fully developed.

Over the last two decades, extensive research has beenconducted on prediction and early detection of seizures usinga variety of different methods. Univariate algorithms, whichinvolve computations on a single input, have been used topredict seizures. Such methods include computing wavelettransforms [4], energy of signal bands [9], correlation di-mensions [10] and computing the Lyapunov exponent [11].These univariate algorithms lack spatial specificity because

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Fig. 1. Closed-loop neural recording and stimulation systemfor epilepticseizure detection and control.

they only rely on one recording. This issue can be addressedthrough bivariate or multivariate algorithms which operate ontwo or more inputs, respectively [12]. Seizure prediction anddetection algorithms that use bivariate or multivariate measuresto quantify synchronization among two or more neural signalshave been shown to yield superior accuracy [5], [13], [14].

Neurons initiate electrical oscillations that are containedin multiple frequency bands such as alpha (8-12Hz), beta(13-30Hz) and gamma (40-80Hz) and have been linked to awide range of cognitive and perceptual processes [15]. It hasbeen shown that before and during a seizure the amount ofsynchrony between these oscillations from neurons locatedindifferent regions of the brain changes significantly [5]. Thus,the amount of synchrony between multiple neural signals is astrong indicator in predicting or detecting seizures [5], [13].To quantify the level of synchrony between two neural signals,a phase locking value (PLV) can be computed that accuratelymeasures the phase-synchronization between two signal sitesin the brain [5], [16].

Existing VLSI systems that perform signal processing onneural signals typically employ univariate algorithms. Theseinvolve computations on a single input, such as computingspike thresholds [17], correlation integrals [18], autoregres-sive parameters [19], extracting energy bands [20], RMS,maximum-minimum, line-length and nonlinear energy [21]and analog wavelet filtering [4]. More computationally inten-sive techniques that use inputs from multiple recording sitessuch as computing the phase-synchronization, the correlationindex and the similarity index between neural signals, havebeen used to develop more accurate seizure prediction and

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Fig. 2. Top-level block diagram of two analog neural recording channelsand the digital phase-synchronization epileptic early seizure detector.

detection algorithms [5], [13], [16], [22], [23], [24], buttodate have only been implemented in software.

We present a low-power digital phase-synchronization pro-cessor VLSI architecture that efficiently performs compu-tationally intensive phase-locking value (PLV) estimation.This paper extends on an earlier report of the principle anddemonstration in [25], and offers a more detailed analysisof the architecture and seizure prediction sensitivity resultsin human EEG data. The VLSI architecture employs theCOrdinate Rotation DIgital Computer (CORDIC) algorithm[26]. The algorithm offers a hardware-efficient approach tocomputing trigonometric and vector functions, as it requiresonly shift-and-add operations for vector rotations. The VLSIarchitecture is to be integrated with neural recording and stim-ulation circuits [27] to implement a multi-channel implantableclosed-loop microsystem as shown in Figure 1. The phasesynchronization processor combines three CORDIC processorcores, which operate on vectors to compute the magnitude,phase and the phase-synchronization of two signals. The restof the paper is organized as follows. Section II discussesthe phase-synchronization algorithm. Section III presents theVLSI architecture of the processor. Section IV describes itsVLSI implementation. Section V contains simulation andexperimental results of early seizure detection by the phase-synchronization processor, in human EEG recordings.

II. PHASE-SYNCHRONIZATION ALGORITHM

For two oscillations,V0 and V1, when their instantaneousphase difference is locked to a constant value, synchronizationis present between the two signals. A number of methods existthat quantify the level of frequency-specific synchronizationbetween two neuroelectric signals, including mutual informa-tion and Shannon entropy [16]. Estimation of phase lockinghas emerged as a popular leading method of quantifying neuralsynchronization. Its effectiveness comes from the fact that itrelies on the phase information of a neural signal, separatelyfrom its magnitude. Thus, to quantify the amount of phaselocking between two neural signals requires the computationof the phase difference followed by the computation of aphase locking index. First, the Hilbert transform is appliedto both signalsV0 andV1 to compute their real and imaginary

components,

V0 = Re(V0) + jIm(V0), V1 = Re(V1) + jIm(V1) (1)

whereV0 and V1 are two sinusoidal continuous or discrete-time signals. The Hilbert transform is conventionally per-formed over the full band of frequencies in the neural spec-trum, and thus, a narrow-band bandpass filter should beapplied before the Hilbert transform to isolate the signal bandof interest [16].

The magnitude in the extracted frequency band can becomputed as

MAG(Vk) =√

(Re(Vk))2 + (Im(Vk))2 (2)

wherek=0,1. Next, the instantaneous phases are computed foreach channel

φk = arctanIm(Vk)

Re(Vk)(3)

and if phase-synchronization exists between the two channelsin the same frequency band then the difference in phase isequal to a constant

∆φ = φ1 − φ0 = constant. (4)

Numerous statistical tools exist that quantify the level ofphase-synchronization between two signals such as entropyin-dex, mutual information index and mean phase coherence [5].The hardware-efficient mean phase coherence in [5] wasselected, which uses a phase locking value (PLV) between0 and 1 to evaluate the amount of phase-synchronization. Thealgorithm defines PLV as

PLV =1

N

√

√

√

√(

N−1∑

i=0

sin(∆φi))2 + (

N−1∑

i=0

cos(∆φi))2 (5)

whereN is the length of the moving-average FIR filters and∆φi is the instantaneous phase difference between thei-thsamples of the two signals.

In summary, the PLV computation requires the Hilberttransform, arctan, addition, sine and cosine, moving-averagefiltering and lastly, the PLV magnitude. The arctan, sine/cosineand magnitude operators will be computed using the CORDICalgorithm while the moving-average filtering will be computedusing digital FIR filtering. Both the magnitude value in (2) andthe PLV value in (5) are used in this work for early detectionof epileptic seizures.

III. VLSI A RCHITECTURE

The architecture of the feedforward path of the system inFigure 1 for two channels is presented in Figure 2 and containsboth analog and digital components. After low-noise amplifi-cation of the neural signals by a low-power neural amplifier,narrow-band filter extracts the signal in the frequency bandofinterest.

The proposed analog front-end utilizes two stages of AC-coupled amplifiers with a gain of 1000V/V (60dB), andtuneable low-pass and high-pass filters to maintain a band-width between 0.1Hz and 5kHz. The capacitive feedbackarchitecture minimizes area and power dissipation allowing

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Fig. 3. Simulation results showing gain mismatch for two 16-tapFIR filtersprogrammed for all-pass and Hilbert response (N=number of taps) with ananalog bandpass filter at 30Hz.

for a large number of channels as was previously reported in[27] and [28]. The input-referred noise integrated over a 5kHzbandwidth is below 10µV. A fully differential architectureminimizes common-mode noise.

A bandpass filter is required as changes in magnitude andinstantaneous phase and phase difference occur in specificsignal bands [15]. Narrowband synchronization outperformsbroadband synchronization in recognizing the start of a seizureonset [16]. Utilizing the narrow bandwidth also puts lessconstraint on the input-referred noise and resolution of theanalog front-end and ADC, respectively, leading to smallerarea and lower power dissipation. A 2nd order analog bandpassfilter with a Q of 5 was used to extract the signal band ofinterest.

The bandpass filtered signal is then digitized by a low-powermedium resolution analog-to-digital converter (ADC). Next,each digitized signal is fed to a set of two 10-bit finite impulseresponse (FIR) filters. One FIR filter is configured to performthe Hilbert transform to shift the signal by 90 degrees, whilethe other FIR filter is an all-pass filter to ensure the digitaldelays of the two FIR filters are matched. To further savepower, this FIR filtering can also be efficiently performed inthe mixed-signal VLSI domain by incorporating it within theADC [29]. This is why the front-end FIR filtering is not con-sidered as a part of the phase-synchronization processor. Withthe high-Q bandpass filter, a FIR filter with 16 taps achievesa well matched magnitude response when programmed withthe coefficients for the all-pass and Hilbert response. Furtherdecreasing the number of taps of the FIR filters leads to gainmismatches between the all-pass and Hilbert filters as shownin Figure 3.

The rest of the computation is efficiently performed in thedigital domain by using the CORDIC algorithm. Samplingmore than one pair of analog channel outputs within a singleseizure prediction time window yields multivariate signalprocessing [30].

A. CORDIC Algorithm

Next, the phase locking value is computed using theCORDIC algorithm. The CORDIC algorithm has been demon-strated in a large number of applications, such as matrix com-putations (QRD and eigenvalue estimation), image processing(DCT) and digital communications (FFT, DDS) [26]. TheCORDIC algorithm operates on a vector of complex numbersby multiplying it by powers of two removing the requirementof complex multipliers and utilizing only adders, shiftersandmemory retrieval operations [26]. Using an iterative approach,CORDIC provides a high-accuracy, low-power and low-areacomputational algorithm at the cost of reduced speed. Twomodes were implemented in CORDIC: the rotational modewhich is used for computing sine and cosine, and the vectoringmode which is used to compute the magnitude and the phase.The two modes only differ in the directions of rotation [26].

The CORDIC algorithm involves iterations on three differ-ence equations as follows

for n = 1 : 16 (6)

x[n+ 1] = x[n] + y[n]2−(n−1)

y[n+ 1] = y[n]− sign(y[n])x[n]2−(n−1)

z[n+ 1] = z[n] + sign(y[n])arctan(2−(n−1))

To compute the magnitude and the phase using CORDIC, theinitial values must first be set. For the CORDIC equations, theinitial x[1] and y[1] would represent the real and imaginarycomponents of the signal, respectively, withy[1] set to 0.Over the next 16 clock cycles the procedure that computesmagnitude and phase is repeated whiley converges to 0. Thefinal valuex[16] represents a scaled magnitude and the finalvaluez[16] represents the phase. A look-up table that stores 16arctan values was used in the phase computation. Computingsine and cosine is similar except we initializex[1] to theCORDIC aggregate constant K, sety[1] to 0 and setz[1] tothe angle we want to compute. Alsoz converges to 0 insteadof y and the final output,x[16], represents the cosine of theangle, whilez[16] represents the sine of the angle.

B. CORDIC-based Processor VLSI Architecture

The VLSI architecture of the 10-bit phase-synchronizationand magnitude processor is shown in Figure 4. It uses threepipelined CORDIC cores and two moving-average FIR filters.The pipelined architecture allows the supply voltage to belowered to minimize power dissipation by using a lowerfrequency clock while maintaining a constant throughput.The first core receives the two digitized vectored signals,preprocesses them by extracting the quadrant of the angleand then simultaneously computes both the angle between 0and 90 degrees and the magnitude using a 16-bit CORDICcore configured in the vectoring mode. The angles are re-adjusted using the stored quadrant information to output anangle between 0 and 360 degrees. The difference between thetwo computed angles is transferred to the next stage.

The sine and cosine of the angle difference are computedusing a 16-bit CORDIC core configured in the rotational mode.The computed sine and cosine as well as the negative flags

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Fig. 4. VLSI architecture of the phase-synchronization processor.

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Fig. 5. Simulated PLV for different values ofN (length of the FIR filters)when the frequency of one input,VIN1, is held constant at 110Hz and thefrequency of the other input,VIN0, is swept from 70Hz to 150Hz.

are transferred to the two 32-tap moving-average FIR filters.Higher sensitivity for the PLV algorithm can be achievedby increasing the length of the FIR filters at a cost in areaand complexity. Lastly, the PLV is computed by extractingthe magnitude of the FIR averaged sine and cosine outputsusing a 16-bit CORDIC core configured in the vectoringmode. An output multiplexer can be configured to output theinstantaneous magnitude and phase of each channel, as well asthe phase difference and the PLV between two channels. EachCORDIC core requires 18 clock cycles which include oneclock cycle for pre-processing the angles, 16-clock cyclestoperform the CORDIC algorithm and one clock cycle to outputthe data and post-process the angles for a total latency of54 clock cycles to compute the PLV algorithm. The simulationresults in Figure 5 show how the PLV sensitivity improves withincreasing the length of the moving-average FIR filters.

IV. VLSI I MPLEMENTATION

The processor was designed and synthesized using a stan-dard 8-metal 0.13µm CMOS technology. It contains a totalof 41,366 gates and occupies an area of 0.178mm2. The firstmagnitude/phase CORDIC core occupies 20.6 percent of thearea, the second sine/cosine CORDIC core uses 12.8 percent,

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Fig. 6. (a) Experimentally measured magnitude of a sinusoidal inputcomputed by the phase-synchronization processor. (b) The correspondingrelative percent error.

the FIR moving-average filters occupy 57 percent, the thirdmagnitude CORDIC core utilizes 9 percent and pre-processingand the output MUX occupy 1 percent of the total core area.Accuracy and sensitivity of the PLV computation can be tradedfor area by reducing the length of the moving-average FIRfilters. A 4 times increase in the length of FIR filters yieldedan overall layout area increase of 1.8 times and an overallpower dissipation increase of 1.7 times.

The univariate magnitude and phase-estimation operationsand the bivariate phase difference and PLV-estimation opera-tions are all computed simultaneously for every sample andare time-multiplexed through a 10-bit output. The synthesizeddesign can operate at frequencies above 100MHz, which isbeyond the requirements of the intended application. Thismargin allows the ability to further reduce power dissipationby lowering the supply voltage.

V. RESULTS

A. Experimental Results

The phase-synchronization processor was prototyped in astandard 0.13µm CMOS technology and characterized experi-mentally. Two analog signals were digitized, sent through FIRfilters to obtain the Hilbert transform and its delayed version,and fed to the processor.

The experimentally measured magnitude extraction resultsare shown in Figure 6, when a sinusoid is applied as an inputto the processor. The maximum error is below 3.5 percentwith respect to the full scale when the input is between 0mVand 600mV. For a neural amplifier gain of 2,000V/V, thiscorresponds to a neural signal between 0µV and 300µV .

Next, two sinusoid inputs were set to 110Hz, with onesinusoid having its phase locked while adjusting the phaseof the other sinusoid. The measured phase difference betweenthis pair of inputs is shown in Figure 7. The maximum erroris approximately 1.5 percent.

The measured PLV between a pair of inputs is shown inFigure 8. The average PLV between the two inputs is computedwith one input held constant at 110Hz, while the other inputfrequency is swept from 60Hz to 160Hz. As expected, the

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Fig. 7. Experimentally measured phase difference between twoinputsinusoids. (b) The corresponding relative percent error.

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Fig. 8. Experimentally computed PLV when the frequency of one input,VIN1, is held constant at 110Hz and the frequency of the other input, VIN0,is swept from 60Hz to 160Hz.

computed PLV is near unity when the two signals have thesame frequency. When the second signal has its frequency setto 60Hz or 160Hz, the PLV drops to 0.45 and 0.4 respectively.The phase locking sensitivity can be further improved byincreasing the length of the moving-average FIR filters.

The experimentally measured power dissipation of the pro-cessor for a supply voltage of 0.85 and 1.15V operating atvarious clock frequencies is shown in Figure 9. For a 0.85Vsupply at 2.5MHz and 10MHz the processor dissipates 102µWand 412µW, respectively. For a 1.15V supply at 2.5MHz and10MHz the processor dissipates 231µW and 897µW, respec-tively. For only one pair of channels, operating at 1.7kS/sthe processor dissipates 3.6µW from a 0.85V supply. Atlower clock frequencies of 39kHz and 156kHz the processordissipates 4.6µW and 17.3µW, respectively, from a 1.15Vsupply and 2.4µW and 8.5µW, respectively, from a 0.85Vsupply.

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Fig. 9. Experimentally measured power dissipation at different operatingfrequencies.

TABLE IEEG DATABASE USED IN VERIFICATION OF THE

PHASE-SYNCHRONIZATION PROCESSOR. SEIZURE TYPES: SIMPLE

PARTIAL (SP), COMPLEX PARTIAL (CP), GENERALIZED TONIC-CLONIC

(GTC). SEIZURE LOCATION: HIPPOCAMPAL (H), NEOCORTICAL (NC).ELECTRODETYPES: DEPTH (D), STRIP (S), GRID (G).

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1 F 30 SP, CP, GTC H D, S I 10 98 60

2 M 17 SP, CP, GTC NC G, S I 10 30 44

3 M 10 SP, CP, GTC H D, S I 10 102 22

B. Simulated Human EEG Results

A Verilog-AMS model of the phase-synchronization proces-sor is too computationally complex to be used in early seizuredetection simulations. Instead, a Simulink model which haditsresolution and accuracy set to match the performance of theRTL-level implementation of the synthesized processor wasutilized.

The efficacy of the phase-synchronization processor inearly seizure detection was verified and validated on an EEGdatabase from the seizure prediction project at the Universityof Freiburg [31]. It consists of 222 hours of intracranial EEGrecording of three patients with a total of 30 seizures analyzedand labeled by certified epileptologists as summarized in TableI. The data was acquired by a Neurofile NT digital video EEGsystem with 128 channels, 512 Hz sampling rate, and a 16-bitanalog-to-digital converter via implanted depth, strip and gridelectrodes.

For each patient, three intracranial electrodes located intheproximity of an epileptic focus were used. For each electrodetype, a sub-set of contact pairs was selected for the PLVcomputation as follows. First, only the contact pairs of thesame electrode type were used as inputs to the PLV processor

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to suppress common-mode noise. Next, a reference electrodewas chosen for each electrode type as the contact furthest awayfrom the epileptic focus. Then, for each contact pair, the signalspectrum was separated into five frequency bands via high-Qbandpass filters: delta (0.5-4 Hz), theta (4-8 Hz), alpha (8-13Hz), a sub-band of beta (15-25 Hz) and gamma (30-48 Hz).Finally, a sub-set of contact pairs across all frequency bandswas selected by pairing each contact with the reference andobserving the channel magnitudes and the PLV within threehours of a clinical seizure onset.

The sensitivity, defined as the true positive rate (TPR), ofthe phase-synchronization algorithm was evaluated as a func-tion of seizure occurrence period (SOP ), seizure predictionhorizon (SPH), false positive rate (FPR) and maximum falsepositive rate (FPRmax) [22], [23], [24]. TheSOP is definedas the period of time in which only one seizure is to beexpected. It was varied between 5 and 40 minutes to accountfor the uncertainty in the seizure frequency. TheSPH was setto between 16 seconds and 5 minutes to allow enough timefor the therapeutic intervention, such as electrical stimulationor a warning signal to the patient.

Three early seizure detection methods were used in theanalysis of the EEG database: magnitude, PLV and combinedmagnitude with PLV detectors. The magnitude detector isactive when the amplitudes of both input channels within afrequency band of interest cross their corresponding thresh-olds. The PLV detector is triggered when the phase lockingvalue, integrated over an adjustable period of time, dropsbelow a certain threshold. The combined magnitude and PLVdetector output is formed by AND-ing the outputs of theindividual detectors. Each threshold detector, once triggered,remains active for the duration equal to the sum ofSOP andSPH time periods. All early seizure detection methods werecompared against the random detector.

The experimental results showed highest PLV activity inthe 15-25Hz frequency band. Figure 10 presents an exampleof an early seizure detection result computed by the phase-synchronization processor in the 15-25Hz frequency bandfor patient 2. The clinical seizure onset is characterized byan increase in the magnitude and a marked fluctuation (adrop in this case) in the PLV before the seizure. The phaselocking value reaches 1 during the seizure reflecting thesynchronized firing of neurons. Similar early seizure detectoroutputs generated by the processor are observed in the 15-25Hz frequency band of patient 3 as shown in Figure 11. Themagnitude and PLV thresholds are adjusted for each patient toachieve the highest sensitivity in early detection of seizures.

Figures 12(a) and 12(b) show the variation of the sensitivitywith FPR andSOP , respectively, for patient 2 in the Uni-versity of Freiburg data set. Each plot compares the sensitivityof the three detectors in comparison to a random detector. Thesensitivity plot in Figure 12(a) shows that the best detector, thePLV detector, achieves 66 percent sensitivity with FPR of 0.65FP/hr,SOP of 30 minutes, andSPH of less than 5 minutes.

The sensitivity plot in Figure 12(b) shows that when theFPRmax is increased to 1.2/hr, the true positive rate reaches100 percent for a seizure occurrence period greater than

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(e)EARLY DETECTION

Fig. 10. Early seizure detection results example for patient2. (a), (b) Twoinput intracranial EEG signals recorded on electrodes 13 and 23, respectively.(c), (d) Magnitude of the signals shown in (a), (b), respectively, after theyare bandpass filtered in the 15Hz to 25Hz frequency range, computed by theprototyped phase-synchronization processor. (e) Integrated PLV between thetwo inputs in the 15Hz to 25Hz frequency band computed by the prototypedphase-synchronization processor.

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(c)

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µ

EARLY DETECTION

Fig. 11. Early seizure detection results example for patient3. (a), (b).Two input intracranial EEG signals recorded on EEG electrodes 1 and 2,respectively. (c), (d) Magnitude of the signals shown in (a), (b), respectively,after they are bandpass filtered in the 15Hz to 25Hz frequencyrange,computed by the prototyped phase-synchronization processor. (e) IntegratedPLV between the two inputs in the 15Hz to 25Hz frequency band computedby the prototyped phase-synchronization processor.

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10 minutes. By increasing theFPRmax to 1.2 FP/hr-2.0 FP/hrdepending on a patient,TPR approaches 100 percent for allpatients. TheFPRmax could not always be made constant byvarying the thresholds; therefore, the averageFPRmax ratesare shown for each early detection method in Figure 12(b).

The sensitivity results in early seizure detector are compara-ble to previously reported software-based bivariate predictionalgorithms [22], [23], [24] as summarized in Table II (withthe exception of [22] which results in 100 percent TPR atFPR=1/hr versus 100 percent TPR at FPR=1.2/hr performanceyielded by the presented phase-synchronization processorar-chitecture). All of the listed algorithms have been tested onthe same benchmark data set from the University of Freiburg,but the presented algorithm is the only one that has beenimplemented as a low-power implantable integrated circuit.Recent integrated circuit seizure detector implementations[19], [20], [32] achieve a high TPR for a given set of patientseizure data, but have not been tested on publicly availablebenchmarking human seizure data sets such as the one fromUniversity of Freiburg and have lower detection-to-seizure-onset times as shown in Table II.

C. Experimental Human EEG Results

Two-electrode intracranial EEG data from patient 1 fromUniversity of Freiburg database was loaded onto a dual-channel Tektronix AFG3252 arbitrary waveform generator andfed into the phase-synchronization processor chip. A bandpassfilter filtered the inputs to 15-25Hz frequency band. Two 8-bit ADCs and four 16-tap FIR filters (two all-pass and twoHilbert filters) digitized and applied a 90 degree phase shift,respectively, to the two signals. The processor simultaneouslycomputed both magnitudes, the phase difference and the PLVat 1.7kS/s dissipating 3.6µW from a 0.85V supply.

Two-electrode intracranial EEG seizure recordings frompatient 1 (electrode-40 and electrode-44) are shown in Figure13(a) and (b). Figure 13(c) shows the experimentally measuredmagnitude from electrode-40, while Figure 13(d) shows thethe experimentally measured magnitude from electrode-44.For both inputs, the experimentally measured magnitude wasobserved to increase during the seizure. Lastly, Figure 13(e)shows the experimentally measured PLV between the twoinputs. The PLV was observed to drop 15 seconds beforethe onset of the seizure displaying an early detection, thenincreasing during the seizure. Seizure data from other patientswere also fed into the processor. The magnitude was observedto increase before and during the seizure while a pronouncedfluctuation of PLV is observed before and during the seizure.

VI. CONCLUSIONS

A compact low-power signal processing VLSI architecturehas been presented that computes the phase locking value ontwo neuroelectrical signals and the instantaneous magnitudeon individual neural inputs. The signal processor is used inconjunction with a neural recording front-end and operatesin real time on frequency bands in the neural spectrum. Theprocessor occupies 0.178mm2 area and dissipates 3.6µWoperating on a pair of inputs sampled at 1.7kS/s from a 0.85V

0 0.2 0.4 0.6 0.8 10

0.1

0.2

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0.7

FALSE POSITIVE RATE (/HR)

TR

UE

PO

SIT

IVE

RA

TE

MAG DETECTOR

PLV DETECTOR

MAG+PLV DETECTOR

RND DETECTOR

(a)

0 0.1 0.2 0.3 0.4 0.5 0.60

0.2

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0.6

0.8

1

SEIZURE OCCURRENCE PERIOD (HOURS)

TR

UE

PO

SIT

IVE

RA

TE

MAG PREDICTOR, FPRmax=0.34/hr (avg)

PLV PREDICTOR, FPRmax=1.2/hr (avg)

MAG+PLV PREDICTOR, FPRmax=0.34/hr (avg)

RND PREDICTOR, FPRmax=0.44/hr (avg)

(b)

Fig. 12. Early seizure detection results for patient 2, showing (a) true positiverate vs. false positive rate plot with the seizure occurrence period held at30min, and (b) true positive rate vs. seizure occurrence period plot. For theabove detectors, MAG refers to magnitude, PLV refers to phaselocking value,and RND refers to random.

supply. Results from pre-recorded human intracranial EEGdata demonstrate the effectiveness of the processor in earlyseizure detection.

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8

TABLE IIPERFORMANCE COMPARATIVE ANALYSIS OF BIVARIATE SEIZURE DETECTION AND PREDICTION ALGORITHMS.

TPR vs FPR (%) TPR vs SOP (%) Avg. DetectionSeizure Detection and Prediction Methods for SOP=30min for FPR< 1.2/hr to-Seizure-onsetReference Method Type FPR=0/hr FPR=1/hr SOP=10m SOP=40m

[22]* Phase Locking Value Software 20 100 20 100 11 min[23]* Similarity Index Software 30 40 20 30 5 min[33]* Correlation Dimension Software 15 40 15 70 11 min[19] Event Threshold IC - 94 - - 8.5 s[20] SVM Classifier IC - 82 - - 7.5 s[32] Modulated Treshold IC - - - - 13.5 s

This Work* Phase Locking Value IC 33 66 33 100 59 s

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−5

0

5

−5

0

5

0

0.05

0.1

0

0.1

0.2

0 25 50 75 1000

0.5

1

(mV

)(m

V)

PLV

MA

G4

1M

AG

44

(a)

(b)

(c)

(d)

(e)

SEIZURE

TIME (s)EARLY DETECTION

EEG-41

EEG-44

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9

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Karim Abdelhalim (S’06) received the B.Eng. andM.A.Sc. degrees in Electrical Engineering from Car-leton University, in Ottawa, Canada, in 2005 and2007, respectively. His M.A.Sc. thesis focused onthe implementation of an ultra low power ADC forbiomedical applications.

He is currently working toward the Ph.D. degreein Electrical and Computer Engineering at the Uni-versity of Toronto. His research interests are in thearea of wireless closed-loop implantable SoCs forneural interfaces. From July 2010 to October 2010,

he worked as a mixed-signal design engineering intern at Broadcom Corp,Irvine, CA.

He is a recipient of the Alexander Graham Bell Canada Graduate Scholar-ship awarded by the Natural Sciences and Engineering Research Council ofCanada (NSERC) from 2007 to 2010. He has also held the OntarioGraduateScholarship (OGS) in 2005, the NSERC CGS-M in 2006 and the OntarioGraduate Scholarships in Science and Technology (OGSST) in2011. He alsoworked as a volunteer at the International Solid-State Circuits Conference(ISSCC) from 2008-2011.

Vadim Smolyakov (S’05) received the B.A.Sc. de-gree with honors in engineering science specializ-ing in electrical engineering from the University ofToronto, Toronto, ON, Canada in 2009, where he iscurrently pursuing the M.A.Sc. degree in electricaland computer engineering.

Mr. Smolyakov held numerous research assistantpositions within electrical and computer engineer-ing department at the University of Toronto. FromMay 2007 to August 2008, he worked as an ASICengineer on a video processing system-on-chip at

Silicon Optix Inc, Toronto, ON. From January 2011 to July 2011, he workedas a communication systems engineer on a cross-level optimization of asystem-on-chip OFDM receiver at MaxLinear Inc, Carlsbad, CA. His researchinterests include signal processing algorithms and VLSI architectures fordigital communications, multimedia and biomedical applications.

Mr. Smolyakov is a recipient of the Natural Sciences and EngineeringResearch Council of Canada (NSERC) post graduate scholarship as wellas the Ontario Graduate Scholarship (OGS). He has several publications ininternational conferences and a pending U.S. patent. He wasan instructor forthe Da Vinci Engineering Enrichment Program (DEEP) at the University ofToronto and a volunteer at the International Solid-State Circuits Conference(ISSCC) in 2010.

Roman Genov (SM’96-M’02) received the B.S.degree (first rank) in Electrical Engineering fromRochester Institute of Technology, NY in 1996, andthe M.S. and Ph.D. degrees in Electrical and Com-puter Engineering from Johns Hopkins University,Baltimore, MD in 1998 and 2002 respectively.

Dr. Genov held engineering positions at AtmelCorporation, Columbia, MD in 1995 and XeroxCorporation, Rochester, NY in 1996. He was avisiting researcher in the Laboratory of IntelligentSystems at Swiss Federal Institute of Technology

(EPFL), Lausanne, Switzerland in 1998 and in the Center for Biological andComputational Learning at Massachusetts Institute of Technology, Cambridge,MA in 1999. He is presently an Associate Professor in the Department ofElectrical and Computer Engineering at the University of Toronto, Canada.His research interests include analog and digital VLSI circuits, systemsand algorithms for energy-efficient signal processing with applications toelectrical, chemical and photonic sensory information acquisition, biosensorarrays, brain-silicon interfaces, parallel signal processing, adaptive computingfor pattern recognition, and implantable and wearable biomedical electronics.

Dr. Genov received Canadian Institutes of Health Research (CIHR) NextGeneration Award in 2005, Brian L. Barge Award for excellence in mi-crosystems integration in 2008, DALSA Corporation Award forexcellence inmicrosystems innovation in 2006 and 2009, and Best Paper Awardon sensorsand Best Student Paper Award, both atIEEE International Symposium onCircuits and Systemsin 2009. He is an Associate Editor ofIEEE Transactionson Biomedical Circuits and Systems, IEEE Transactions on Circuits andSystems-II: Express Briefsand IEEE Signal Processing Letters.