PCI Express Base r3.0 10Nov10

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PCI Express Base Specification Revision 3.0November 10, 2010

Revision1.0 1.0a 1.1 2.0 2.1

Revision HistoryInitial release. Incorporated Errata C1-C66 and E1-E4.17. Incorporated approved Errata and ECNs. Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. Incorporated Errata for the PCI Express Base Specification, Rev. 2.0 (February 27, 2009), and added the following ECNs: Internal Error Reporting ECN (April 24, 2008) Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) Resizable BAR Capability ECN (January 22, 2008, updated and approved by PWG April 24, 2008) Dynamic Power Allocation ECN (May 24, 2008) ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated June 4, 2007) Extended Tag Enable Default ECN (September 5, 2008) TLP Processing Hints ECN (September 11, 2008) TLP Prefix ECN (December 15, 2008)

DATE07/22/2002 04/15/2003 03/28/2005 12/20/2006 03/04/2009

3.0

Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs: Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol Multiplexing ECN (17 June 2010)

11/10/2010

PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail: administration@pcisig.com Phone: 503-619-0569 Fax: 503-644-6708 Technical Support techsupp@pcisig.com

DISCLAIMER This PCI Express Base Specification is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

Copyright 2002-2010 PCI-SIG

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

ContentsOBJECTIVE OF THE SPECIFICATION.................................................................................... 27 DOCUMENT ORGANIZATION ................................................................................................ 27 DOCUMENTATION CONVENTIONS ...................................................................................... 28 TERMS AND ACRONYMS........................................................................................................ 29 REFERENCE DOCUMENTS...................................................................................................... 36 1. INTRODUCTION ................................................................................................................ 37 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37 1.2. PCI EXPRESS LINK......................................................................................................... 39 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41 1.3.1. Root Complex........................................................................................................ 41 1.3.2. Endpoints .............................................................................................................. 42 1.3.3. Switch.................................................................................................................... 45 1.3.4. Root Complex Event Collector.............................................................................. 46 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 46 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 46 1.5. PCI EXPRESS LAYERING OVERVIEW .............................................................................. 47 1.5.1. Transaction Layer................................................................................................. 48 1.5.2. Data Link Layer .................................................................................................... 48 1.5.3. Physical Layer ...................................................................................................... 49 1.5.4. Layer Functions and Services............................................................................... 49 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 53 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 54 2.1.2. Packet Format Overview ...................................................................................... 56 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION ............................................... 58 2.2.1. Common Packet Header Fields ............................................................................ 58 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 61 2.2.3. TLP Digest Rules .................................................................................................. 65 2.2.4. Routing and Addressing Rules .............................................................................. 65 2.2.5. First/Last DW Byte Enables Rules........................................................................ 69 2.2.6. Transaction Descriptor......................................................................................... 71 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77 2.2.8. Message Request Rules ......................................................................................... 83 2.2.9. Completion Rules .................................................................................................. 97 2.2.10. TLP Prefix Rules ................................................................................................. 100 2.3. HANDLING OF RECEIVED TLPS .................................................................................... 104

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

2.3.1. Request Handling Rules...................................................................................... 107 2.3.2. Completion Handling Rules................................................................................ 120 2.4. TRANSACTION ORDERING ............................................................................................ 122 2.4.1. Transaction Ordering Rules ............................................................................... 122 2.4.2. Update Ordering and Granularity Observed by a Read Transaction ................ 126 2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 127 2.5. VIRTUAL CHANNEL (VC) MECHANISM ........................................................................ 128 2.5.1. Virtual Channel Identification (VC ID) .............................................................. 130 2.5.2. TC to VC Mapping .............................................................................................. 131 2.5.3. VC and TC Rules................................................................................................. 132 2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 133 2.6.1. Flow Control Rules ............................................................................................. 134 2.7. DATA INTEGRITY ......................................................................................................... 145 2.7.1. ECRC Rules ........................................................................................................ 145 2.7.2. Error Forwarding ............................................................................................... 149 2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 151 2.9. LINK STATUS DEPENDENCIES ...................................................................................... 151 2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 151 2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 153 3. DATA LINK LAYER SPECIFICATION .......................................................................... 155 3.1. DATA LINK LAYER OVERVIEW .................................................................................... 155 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 157 3.2.1. Data Link Control and Management State Machine Rules ................................ 158 3.3. FLOW CONTROL INITIALIZATION PROTOCOL .....