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PCI Express ® Base Specification Revision 3.0 November 10, 2010

PCI Express Base r3.0 10Nov10

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PCI Express Base Specification Revision 3.0November 10, 2010

Revision1.0 1.0a 1.1 2.0 2.1

Revision HistoryInitial release. Incorporated Errata C1-C66 and E1-E4.17. Incorporated approved Errata and ECNs. Added 5.0 GT/s data rate and incorporated approved Errata and ECNs. Incorporated Errata for the PCI Express Base Specification, Rev. 2.0 (February 27, 2009), and added the following ECNs: Internal Error Reporting ECN (April 24, 2008) Multicast ECN (December 14, 2007, approved by PWG May 8, 2008) Atomic Operations ECN (January 15, 2008, approved by PWG April 17, 2008) Resizable BAR Capability ECN (January 22, 2008, updated and approved by PWG April 24, 2008) Dynamic Power Allocation ECN (May 24, 2008) ID-Based Ordering ECN (January 16, 2008, updated 29 May 2008) Latency Tolerance Reporting ECN (22 January 2008, updated 14 August 2008) Alternative Routing-ID Interpretation (ARI) ECN (August 7, 2006, last updated June 4, 2007) Extended Tag Enable Default ECN (September 5, 2008) TLP Processing Hints ECN (September 11, 2008) TLP Prefix ECN (December 15, 2008)

DATE07/22/2002 04/15/2003 03/28/2005 12/20/2006 03/04/2009

3.0

Added 8.0 GT/s data rate, latest approved Errata, and the following ECNs: Optimized Buffer Flush/Fill ECN (8 February 2008, updated 30 April 2009) ASPM Optionality ECN (June 19, 2009, approved by the PWG August 20, 2009) Incorporated End-End TLP Changes for RCs ECN (26 May 2010) and Protocol Multiplexing ECN (17 June 2010)

11/10/2010

PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. Contact the PCI-SIG office to obtain the latest revision of this specification. Questions regarding the PCI Express Base Specification or membership in PCI-SIG may be forwarded to: Membership Services www.pcisig.com E-mail: [email protected] Phone: 503-619-0569 Fax: 503-644-6708 Technical Support [email protected]

DISCLAIMER This PCI Express Base Specification is provided as is with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

Copyright 2002-2010 PCI-SIG

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

ContentsOBJECTIVE OF THE SPECIFICATION.................................................................................... 27 DOCUMENT ORGANIZATION ................................................................................................ 27 DOCUMENTATION CONVENTIONS ...................................................................................... 28 TERMS AND ACRONYMS........................................................................................................ 29 REFERENCE DOCUMENTS...................................................................................................... 36 1. INTRODUCTION ................................................................................................................ 37 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 37 1.2. PCI EXPRESS LINK......................................................................................................... 39 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 41 1.3.1. Root Complex........................................................................................................ 41 1.3.2. Endpoints .............................................................................................................. 42 1.3.3. Switch.................................................................................................................... 45 1.3.4. Root Complex Event Collector.............................................................................. 46 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 46 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 46 1.5. PCI EXPRESS LAYERING OVERVIEW .............................................................................. 47 1.5.1. Transaction Layer................................................................................................. 48 1.5.2. Data Link Layer .................................................................................................... 48 1.5.3. Physical Layer ...................................................................................................... 49 1.5.4. Layer Functions and Services............................................................................... 49 2. TRANSACTION LAYER SPECIFICATION ..................................................................... 53 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 53 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 54 2.1.2. Packet Format Overview ...................................................................................... 56 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION ............................................... 58 2.2.1. Common Packet Header Fields ............................................................................ 58 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 61 2.2.3. TLP Digest Rules .................................................................................................. 65 2.2.4. Routing and Addressing Rules .............................................................................. 65 2.2.5. First/Last DW Byte Enables Rules........................................................................ 69 2.2.6. Transaction Descriptor......................................................................................... 71 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 77 2.2.8. Message Request Rules ......................................................................................... 83 2.2.9. Completion Rules .................................................................................................. 97 2.2.10. TLP Prefix Rules ................................................................................................. 100 2.3. HANDLING OF RECEIVED TLPS .................................................................................... 104

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

2.3.1. Request Handling Rules...................................................................................... 107 2.3.2. Completion Handling Rules................................................................................ 120 2.4. TRANSACTION ORDERING ............................................................................................ 122 2.4.1. Transaction Ordering Rules ............................................................................... 122 2.4.2. Update Ordering and Granularity Observed by a Read Transaction ................ 126 2.4.3. Update Ordering and Granularity Provided by a Write Transaction ................ 127 2.5. VIRTUAL CHANNEL (VC) MECHANISM ........................................................................ 128 2.5.1. Virtual Channel Identification (VC ID) .............................................................. 130 2.5.2. TC to VC Mapping .............................................................................................. 131 2.5.3. VC and TC Rules................................................................................................. 132 2.6. ORDERING AND RECEIVE BUFFER FLOW CONTROL ..................................................... 133 2.6.1. Flow Control Rules ............................................................................................. 134 2.7. DATA INTEGRITY ......................................................................................................... 145 2.7.1. ECRC Rules ........................................................................................................ 145 2.7.2. Error Forwarding ............................................................................................... 149 2.8. COMPLETION TIMEOUT MECHANISM ........................................................................... 151 2.9. LINK STATUS DEPENDENCIES ...................................................................................... 151 2.9.1. Transaction Layer Behavior in DL_Down Status............................................... 151 2.9.2. Transaction Layer Behavior in DL_Up Status ................................................... 153 3. DATA LINK LAYER SPECIFICATION .......................................................................... 155 3.1. DATA LINK LAYER OVERVIEW .................................................................................... 155 3.2. DATA LINK CONTROL AND MANAGEMENT STATE MACHINE ...................................... 157 3.2.1. Data Link Control and Management State Machine Rules ................................ 158 3.3. FLOW CONTROL INITIALIZATION PROTOCOL ............................................................... 160 3.3.1. Flow Control Initialization State Machine Rules ............................................... 160 3.4. DATA LINK LAYER PACKETS (DLLPS)........................................................................ 164 3.4.1. Data Link Layer Packet Rules ............................................................................ 164 3.5. DATA INTEGRITY ......................................................................................................... 169 3.5.1. Introduction......................................................................................................... 169 3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 169 3.5.3. LCRC and Sequence Number (TLP Receiver) .................................................... 182 4. PHYSICAL LAYER SPECIFICATION ............................................................................ 191 4.1. INTRODUCTION ............................................................................................................ 191 4.2. LOGICAL SUB-BLOCK ................................................................................................... 191 4.2.1. Encoding for 2.5 GT/s and 5.0 GT/s Data Rates ................................................ 192 4.2.2. Encoding for 8.0 GT/s and Higher Data Rates................................................... 200 4.2.3. Link Equalization Procedure for 8.0 GT/s Data Rate ........................................ 218 4.2.4. Link Initialization and Training.......................................................................... 226 4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 244 4.2.6. Link Training and Status State Rules.................................................................. 247 4.2.7. Clock Tolerance Compensation.......................................................................... 314 4.2.8. Compliance Pattern in 8b/10b Encoding............................................................ 317 4.2.9. Modified Compliance Pattern in 8b/10b Encoding ............................................ 318 4.2.10. Compliance Pattern in 128b/130b Encoding...................................................... 320 4.2.11. Modified Compliance Pattern in 128b/130b Encoding ...................................... 322

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

4.3. ELECTRICAL SUB-BLOCK ............................................................................................. 323 4.3.1. Electrical Specification Organization................................................................. 323 4.3.2. Interoperability Criteria for 2.5, 5.0, and 8.0 GT/s Devices .............................. 323 4.3.3. Transmitter Specification.................................................................................... 325 4.3.4. Receiver Specifications ....................................................................................... 359 4.3.5. Low Frequency and Miscellaneous Signaling Requirements ............................. 382 4.3.6. Channel Specification ......................................................................................... 387 4.3.7. Refclk Specifications ........................................................................................... 400 4.3.8. Refclk Specifications for 8.0 GT/s....................................................................... 408 5. POWER MANAGEMENT................................................................................................. 413 5.1. OVERVIEW ................................................................................................................... 413 5.1.1. Statement of Requirements.................................................................................. 414 5.2. LINK STATE POWER MANAGEMENT ............................................................................. 414 5.3. PCI-PM SOFTWARE COMPATIBLE MECHANISMS ......................................................... 419 5.3.1. Device Power Management States (D-States) of a Function.............................. 419 5.3.2. PM Software Control of the Link Power Management State.............................. 424 5.3.3. Power Management Event Mechanisms ............................................................. 429 5.4. NATIVE PCI EXPRESS POWER MANAGEMENT MECHANISMS ....................................... 436 5.4.1. Active State Power Management (ASPM) .......................................................... 436 5.5. AUXILIARY POWER SUPPORT ....................................................................................... 455 5.5.1. Auxiliary Power Enabling................................................................................... 455 5.6. POWER MANAGEMENT SYSTEM MESSAGES AND DLLPS............................................. 456 6. SYSTEM ARCHITECTURE ............................................................................................. 459 6.1. INTERRUPT AND PME SUPPORT ................................................................................... 459 6.1.1. Rationale for PCI Express Interrupt Model........................................................ 459 6.1.2. PCI Compatible INTx Emulation........................................................................ 460 6.1.3. INTx Emulation Software Model ........................................................................ 460 6.1.4. Message Signaled Interrupt (MSI/MSI-X) Support............................................. 460 6.1.5. PME Support....................................................................................................... 462 6.1.6. Native PME Software Model .............................................................................. 462 6.1.7. Legacy PME Software Model ............................................................................. 463 6.1.8. Operating System Power Management Notification........................................... 463 6.1.9. PME Routing Between PCI Express and PCI Hierarchies ................................ 463 6.2. ERROR SIGNALING AND LOGGING................................................................................ 464 6.2.1. Scope ................................................................................................................... 464 6.2.2. Error Classification ............................................................................................ 464 6.2.3. Error Signaling ................................................................................................... 466 6.2.4. Error Logging ..................................................................................................... 474 6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 478 6.2.6. Error Message Controls ..................................................................................... 480 6.2.7. Error Listing and Rules ...................................................................................... 481 6.2.8. Virtual PCI Bridge Error Handling.................................................................... 486 6.2.9. Internal Errors .................................................................................................... 488 6.3. VIRTUAL CHANNEL SUPPORT ...................................................................................... 489 6.3.1. Introduction and Scope ....................................................................................... 489

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

6.3.2. TC/VC Mapping and Example Usage................................................................. 489 6.3.3. VC Arbitration .................................................................................................... 491 6.3.4. Isochronous Support ........................................................................................... 500 6.4. DEVICE SYNCHRONIZATION ......................................................................................... 502 6.5. LOCKED TRANSACTIONS .............................................................................................. 503 6.5.1. Introduction......................................................................................................... 503 6.5.2. Initiation and Propagation of Locked Transactions - Rules............................... 504 6.5.3. Switches and Lock - Rules................................................................................... 505 6.5.4. PCI Express/PCI Bridges and Lock - Rules ....................................................... 506 6.5.5. Root Complex and Lock - Rules.......................................................................... 506 6.5.6. Legacy Endpoints................................................................................................ 506 6.5.7. PCI Express Endpoints ....................................................................................... 506 6.6. PCI EXPRESS RESET - RULES ....................................................................................... 506 6.6.1. Conventional Reset ............................................................................................. 507 6.6.2. Function-Level Reset (FLR)................................................................................ 510 6.7. PCI EXPRESS HOT-PLUG SUPPORT .............................................................................. 514 6.7.1. Elements of Hot-Plug.......................................................................................... 514 6.7.2. Registers Grouped by Hot-Plug Element Association ........................................ 520 6.7.3. PCI Express Hot-Plug Events............................................................................. 522 6.7.4. Firmware Support for Hot-Plug ......................................................................... 525 6.8. POWER BUDGETING CAPABILITY ................................................................................. 526 6.8.1. System Power Budgeting Process Recommendations......................................... 526 6.9. SLOT POWER LIMIT CONTROL ..................................................................................... 527 6.10. ROOT COMPLEX TOPOLOGY DISCOVERY ................................................................. 530 6.11. LINK SPEED MANAGEMENT ..................................................................................... 532 6.12. ACCESS CONTROL SERVICES (ACS) ........................................................................ 533 6.12.1. ACS Component Capability Requirements ......................................................... 533 6.12.2. Interoperability ................................................................................................... 538 6.12.3. ACS Peer-to-Peer Control Interactions.............................................................. 538 6.12.4. ACS Violation Error Handling ........................................................................... 539 6.12.5. ACS Redirection Impacts on Ordering Rules ..................................................... 540 6.13. ALTERNATIVE ROUTING-ID INTERPRETATION (ARI) .............................................. 542 6.14. MULTICAST OPERATIONS......................................................................................... 546 6.14.1. Multicast TLP Processing................................................................................... 546 6.14.2. Multicast Ordering.............................................................................................. 549 6.14.3. Multicast Capability Structure Field Updates.................................................... 549 6.14.4. MC Blocked TLP Processing .............................................................................. 550 6.14.5. MC_Overlay Mechanism .................................................................................... 550 6.15. ATOMIC OPERATIONS (ATOMICOPS) ....................................................................... 554 6.15.1. AtomicOp Use Models and Benefits ................................................................... 555 6.15.2. AtomicOp Transaction Protocol Summary......................................................... 555 6.15.3. Root Complex Support for AtomicOps................................................................ 557 6.15.4. Switch Support for AtomicOps............................................................................ 559 6.16. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ............................................... 559 6.16.1. DPA Capability with Multi-Function Devices.................................................... 560 6.17. TLP PROCESSING HINTS (TPH) ............................................................................... 561

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

6.17.1. Processing Hints ................................................................................................. 561 6.17.2. Steering Tags ...................................................................................................... 562 6.17.3. ST Modes of Operation ....................................................................................... 562 6.17.4. TPH Capability ................................................................................................... 563 6.18. LATENCY TOLERANCE REPORTING (LTR) MECHANISM .......................................... 564 6.19. OPTIMIZED BUFFER FLUSH/FILL (OBFF) MECHANISM ............................................ 570 7. SOFTWARE INITIALIZATION AND CONFIGURATION............................................ 575 7.1. CONFIGURATION TOPOLOGY........................................................................................ 575 7.2. PCI EXPRESS CONFIGURATION MECHANISMS ............................................................. 576 7.2.1. PCI 3.0 Compatible Configuration Mechanism ................................................. 577 7.2.2. PCI Express Enhanced Configuration Access Mechanism (ECAM).................. 578 7.2.3. Root Complex Register Block ............................................................................. 582 7.3. CONFIGURATION TRANSACTION RULES ....................................................................... 583 7.3.1. Device Number.................................................................................................... 583 7.3.2. Configuration Transaction Addressing............................................................... 584 7.3.3. Configuration Request Routing Rules................................................................. 584 7.3.4. PCI Special Cycles.............................................................................................. 585 7.4. CONFIGURATION REGISTER TYPES .............................................................................. 586 7.5. PCI-COMPATIBLE CONFIGURATION REGISTERS........................................................... 587 7.5.1. Type 0/1 Common Configuration Space ............................................................. 588 7.5.2. Type 0 Configuration Space Header................................................................... 595 7.5.3. Type 1 Configuration Space Header................................................................... 597 7.6. PCI POWER MANAGEMENT CAPABILITY STRUCTURE .................................................. 601 7.7. MSI AND MSI-X CAPABILITY STRUCTURES ................................................................ 603 7.7.1. Vector Control for MSI-X Table Entries............................................................. 603 7.8. PCI EXPRESS CAPABILITY STRUCTURE........................................................................ 604 7.8.1. PCI Express Capability List Register (Offset 00h) ............................................. 605 7.8.2. PCI Express Capabilities Register (Offset 02h) ................................................. 606 7.8.3. Device Capabilities Register (Offset 04h) .......................................................... 608 7.8.4. Device Control Register (Offset 08h) ................................................................. 613 7.8.5. Device Status Register (Offset 0Ah).................................................................... 620 7.8.6. Link Capabilities Register (Offset 0Ch).............................................................. 622 7.8.7. Link Control Register (Offset 10h) ..................................................................... 627 7.8.8. Link Status Register (Offset 12h) ........................................................................ 635 7.8.9. Slot Capabilities Register (Offset 14h) ............................................................... 638 7.8.10. Slot Control Register (Offset 18h) ...................................................................... 640 7.8.11. Slot Status Register (Offset 1Ah)......................................................................... 644 7.8.12. Root Control Register (Offset 1Ch) .................................................................... 646 7.8.13. Root Capabilities Register (Offset 1Eh) ............................................................. 647 7.8.14. Root Status Register (Offset 20h)........................................................................ 648 7.8.15. Device Capabilities 2 Register (Offset 24h) ....................................................... 649 7.8.16. Device Control 2 Register (Offset 28h) .............................................................. 654 7.8.17. Device Status 2 Register (Offset 2Ah)................................................................. 658 7.8.18. Link Capabilities 2 Register (Offset 2Ch)........................................................... 658 7.8.19. Link Control 2 Register (Offset 30h) .................................................................. 660 7.8.20. Link Status 2 Register (Offset 32h) ..................................................................... 6657

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

7.8.21. Slot Capabilities 2 Register (Offset 34h) ............................................................ 667 7.8.22. Slot Control 2 Register (Offset 38h) ................................................................... 667 7.8.23. Slot Status 2 Register (Offset 3Ah)...................................................................... 667 7.9. PCI EXPRESS EXTENDED CAPABILITIES....................................................................... 667 7.9.1. Extended Capabilities in Configuration Space................................................... 668 7.9.2. Extended Capabilities in the Root Complex Register Block............................... 668 7.9.3. PCI Express Extended Capability Header.......................................................... 669 7.10. ADVANCED ERROR REPORTING CAPABILITY ........................................................... 670 7.10.1. Advanced Error Reporting Extended Capability Header (Offset 00h)............... 672 7.10.2. Uncorrectable Error Status Register (Offset 04h).............................................. 673 7.10.3. Uncorrectable Error Mask Register (Offset 08h)............................................... 675 7.10.4. Uncorrectable Error Severity Register (Offset 0Ch) .......................................... 677 7.10.5. Correctable Error Status Register (Offset 10h).................................................. 679 7.10.6. Correctable Error Mask Register (Offset 14h)................................................... 680 7.10.7. Advanced Error Capabilities and Control Register (Offset 18h) ....................... 681 7.10.8. Header Log Register (Offset 1Ch) ...................................................................... 682 7.10.9. Root Error Command Register (Offset 2Ch) ...................................................... 683 7.10.10. Root Error Status Register (Offset 30h).......................................................... 684 7.10.11. Error Source Identification Register (Offset 34h) .......................................... 687 7.10.12. TLP Prefix Log Register (Offset 38h) ............................................................. 687 7.11. VIRTUAL CHANNEL CAPABILITY ............................................................................. 688 7.11.1. Virtual Channel Extended Capability Header (Offset 00h)................................ 690 7.11.2. Port VC Capability Register 1 (Offset 04h)........................................................ 691 7.11.3. Port VC Capability Register 2 (Offset 08h)........................................................ 692 7.11.4. Port VC Control Register (Offset 0Ch)............................................................... 693 7.11.5. Port VC Status Register (Offset 0Eh).................................................................. 694 7.11.6. VC Resource Capability Register ....................................................................... 695 7.11.7. VC Resource Control Register............................................................................ 697 7.11.8. VC Resource Status Register .............................................................................. 699 7.11.9. VC Arbitration Table .......................................................................................... 700 7.11.10. Port Arbitration Table .................................................................................... 701 7.12. DEVICE SERIAL NUMBER CAPABILITY ..................................................................... 703 7.12.1. Device Serial Number Extended Capability Header (Offset 00h) ...................... 704 7.12.2. Serial Number Register (Offset 04h)................................................................... 705 7.13. PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ............................ 705 7.13.1. Root Complex Link Declaration Extended Capability Header (Offset 00h) ...... 707 7.13.2. Element Self Description (Offset 04h) ................................................................ 708 7.13.3. Link Entries......................................................................................................... 709 7.14. PCI EXPRESS ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY ................... 713 7.14.1. Root Complex Internal Link Control Extended Capability Header (Offset 00h) 713 7.14.2. Root Complex Link Capabilities Register (Offset 04h)....................................... 714 7.14.3. Root Complex Link Control Register (Offset 08h).............................................. 717 7.14.4. Root Complex Link Status Register (Offset 0Ah)................................................ 719 7.15. POWER BUDGETING CAPABILITY ............................................................................. 720 7.15.1. Power Budgeting Extended Capability Header (Offset 00h).............................. 721 7.15.2. Data Select Register (Offset 04h) ....................................................................... 721

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

7.15.3. Data Register (Offset 08h) .................................................................................. 722 7.15.4. Power Budget Capability Register (Offset 0Ch)................................................. 724 7.16. ACS EXTENDED CAPABILITY .................................................................................. 725 7.16.1. ACS Extended Capability Header (Offset 00h) .................................................. 725 7.16.2. ACS Capability Register (Offset 04h) ................................................................. 726 7.16.3. ACS Control Register (Offset 06h) ..................................................................... 727 7.16.4. Egress Control Vector (Offset 08h) .................................................................... 729 7.17. PCI EXPRESS ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY ............................................................................................................................. 730 7.17.1. Root Complex Event Collector Endpoint Association Extended Capability Header (Offset 00h) ......................................................................................................................... 731 7.17.2. Association Bitmap for Root Complex Integrated Endpoints (Offset 04h)......... 732 7.18. MULTI-FUNCTION VIRTUAL CHANNEL CAPABILITY ................................................ 732 7.18.1. MFVC Extended Capability Header (Offset 00h)............................................... 733 7.18.2. Port VC Capability Register 1 (Offset 04h)........................................................ 734 7.18.3. Port VC Capability Register 2 (Offset 08h)........................................................ 736 7.18.4. Port VC Control Register (Offset 0Ch)............................................................... 737 7.18.5. Port VC Status Register (Offset 0Eh).................................................................. 738 7.18.6. VC Resource Capability Register ....................................................................... 738 7.18.7. VC Resource Control Register............................................................................ 740 7.18.8. VC Resource Status Register .............................................................................. 742 7.18.9. VC Arbitration Table .......................................................................................... 743 7.18.10. Function Arbitration Table ............................................................................. 743 7.19. VENDOR-SPECIFIC CAPABILITY ............................................................................... 745 7.19.1. Vendor-Specific Extended Capability Header (Offset 00h)................................ 746 7.19.2. Vendor-Specific Header (Offset 04h).................................................................. 747 7.20. RCRB HEADER CAPABILITY ................................................................................... 748 7.20.1. RCRB Header Extended Capability Header (Offset 00h)................................... 748 7.20.2. Vendor ID (Offset 04h) and Device ID (Offset 06h)........................................... 749 7.20.3. RCRB Capabilities (Offset 08h).......................................................................... 750 7.20.4. RCRB Control (Offset 0Ch) ................................................................................ 750 7.21. MULTICAST CAPABILITY ......................................................................................... 751 7.21.1. Multicast Extended Capability Header (Offset 00h) .......................................... 751 7.21.2. Multicast Capability Register (Offset 04h) ......................................................... 752 7.21.3. Multicast Control Register (Offset 06h) ............................................................. 753 7.21.4. MC_Base_Address Register (Offset 08h) ........................................................... 754 7.21.5. MC_Receive Register (Offset 10h)...................................................................... 754 7.21.6. MC_Block_All Register (Offset 18h) .................................................................. 755 7.21.7. MC_Block_Untranslated Register (Offset 20h).................................................. 756 7.21.8. MC_Overlay_BAR (Offset 28h) .......................................................................... 756 7.22. RESIZABLE BAR CAPABILITY .................................................................................. 757 7.22.1. Resizable BAR Extended Capability Header (Offset 00h).................................. 759 7.22.2. Resizable BAR Capability Register..................................................................... 760 7.22.3. Resizable BAR Control Register ......................................................................... 761 7.23. ARI CAPABILITY ..................................................................................................... 762 7.23.1. ARI Capability Header (Offset 00h) ................................................................... 763

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

7.23.2. ARI Capability Register (Offset 04h).................................................................. 763 7.23.3. ARI Control Register (Offset 06h) ...................................................................... 764 7.24. DYNAMIC POWER ALLOCATION (DPA) CAPABILITY ............................................... 765 7.24.1. DPA Extended Capability Header (Offset 00h).................................................. 765 7.24.2. DPA Capability Register (Offset 04h) ................................................................ 766 7.24.3. DPA Latency Indicator Register (Offset 08h)..................................................... 767 7.24.4. DPA Status Register (Offset 0Ch)....................................................................... 767 7.24.5. DPA Control Register (Offset 0Eh) .................................................................... 768 7.24.6. DPA Power Allocation Array ............................................................................. 768 7.25. LATENCY TOLERANCE REPORTING (LTR) CAPABILITY ........................................... 769 7.25.1. LTR Extended Capability Header (Offset 00h)................................................... 769 7.25.2. Max Snoop Latency Register (Offset 04h) .......................................................... 770 7.25.3. Max No-Snoop Latency Register (Offset 06h) .................................................... 770 7.26. TPH REQUESTER CAPABILITY ................................................................................. 771 7.26.1. TPH Requester Extended Capability Header (Offset 00h) ................................. 772 7.26.2. TPH Requester Capability Register (Offset 04h)................................................ 772 7.26.3. TPH Requester Control Register (Offset 08h) .................................................... 774 7.26.4. TPH ST Table (Starting from Offset 0Ch) .......................................................... 775 7.27. SECONDARY PCI EXPRESS EXTENDED CAPABILITY ................................................ 776 7.27.1. Secondary PCI Express Extended Capability Header (Offset 00h).................... 776 7.27.2. Link Control 3 Register (Offset 04h) .................................................................. 777 7.27.3. Lane Error Status Register (Offset 08h) ............................................................. 778 7.27.4. Lane Equalization Control Register (Offset 0Ch) .............................................. 778 A. ISOCHRONOUS APPLICATIONS................................................................................... 783 A.1. INTRODUCTION ............................................................................................................ 783 A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ........................................... 785 A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ............................. 786 A.2.2. Isochronous Payload Size ................................................................................... 787 A.2.3. Isochronous Bandwidth Allocation..................................................................... 787 A.2.4. Isochronous Transaction Latency....................................................................... 788 A.2.5. An Example Illustrating Isochronous Parameters.............................................. 789 A.3. ISOCHRONOUS TRANSACTION RULES ........................................................................... 790 A.4. TRANSACTION ORDERING ............................................................................................ 790 A.5. ISOCHRONOUS DATA COHERENCY ............................................................................... 790 A.6. FLOW CONTROL ........................................................................................................... 791 A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ....................................................... 791 A.7.1. Isochronous Bandwidth of PCI Express Links.................................................... 791 A.7.2. Isochronous Bandwidth of Endpoints ................................................................. 791 A.7.3. Isochronous Bandwidth of Switches ................................................................... 791 A.7.4. Isochronous Bandwidth of Root Complex........................................................... 792 A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ..................................................... 792 A.8.1. An Endpoint as a Requester................................................................................ 792 A.8.2. An Endpoint as a Completer ............................................................................... 792 A.8.3. Switches............................................................................................................... 793 A.8.4. Root Complex...................................................................................................... 794

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

B. C.

SYMBOL ENCODING ...................................................................................................... 795 PHYSICAL LAYER APPENDIX...................................................................................... 805 C.1. C.2. 8B/10B DATA SCRAMBLING EXAMPLE ......................................................................... 805 128B/130B DATA SCRAMBLING EXAMPLE ................................................................... 811

D. E.

REQUEST DEPENDENCIES............................................................................................ 815 ID-BASED ORDERING USAGE...................................................................................... 819 E.1. INTRODUCTION ............................................................................................................ 819 E.2. POTENTIAL BENEFITS WITH IDO USE .......................................................................... 820 E.2.1. Benefits for MFD/RP Direct Connect................................................................. 820 E.2.2. Benefits for Switched Environments ................................................................... 820 E.2.3. Benefits for Integrated Endpoints ....................................................................... 821 E.2.4. IDO Use in Conjunction with RO ....................................................................... 821 E.3. WHEN TO USE IDO ...................................................................................................... 821 E.4. WHEN NOT TO USE IDO .............................................................................................. 822 E.4.1. When Not to Use IDO with Endpoints ................................................................ 822 E.4.2. When Not to Use IDO with Root Ports ............................................................... 822 E.5. SOFTWARE CONTROL OF IDO USE............................................................................... 823 E.5.1. Software Control of Endpoint IDO Use.............................................................. 823 E.5.2. Software Control of Root Port IDO Use............................................................. 824

F. G.

MESSAGE CODE USAGE................................................................................................ 825 PROTOCOL MULTIPLEXING......................................................................................... 827 G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................... 830 G.2. PMUX PACKETS.......................................................................................................... 836 G.3. PMUX PACKET LAYOUT ............................................................................................. 837 G.3.1. PMUX Packet Layout for 8b10b Encoding ........................................................ 837 G.3.2. PMUX Packet Layout at 128b/130b Encoding................................................... 839 G.4. PMUX CONTROL ......................................................................................................... 842 G.5. PMUX EXTENDED CAPABILITY................................................................................... 842 G.5.1. PCI Express Extended Header (Offset 00h) ....................................................... 843 G.5.2. PMUX Capability Register (Offset 04h) ............................................................. 844 G.5.3. PMUX Control Register (Offset 08h) ................................................................. 845 G.5.4. PMUX Status Register (Offset 0Ch) ................................................................... 847 G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) ............................................ 850

ACKNOWLEDGEMENTS........................................................................................................ 853

11

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FiguresFIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 39 FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 41 FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 45 FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 47 FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 48 FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 53 FIGURE 2-2: SERIAL VIEW OF A TLP............................................................................................. 56 FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 57 FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 58 FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 59 FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 64 FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 66 FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 66 FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 68 FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 68 FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 69 FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 72 FIGURE 2-13: TRANSACTION ID.................................................................................................... 72 FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 74 FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 78 FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 78 FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 79 FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 80 FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 81 FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 81 FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 82 FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ......................... 83 FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 83 FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 84 FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ........................................................... 94 FIGURE 2-26: LTR MESSAGE ........................................................................................................ 96 FIGURE 2-27: OBFF MESSAGE ..................................................................................................... 97 FIGURE 2-28: COMPLETION HEADER FORMAT .............................................................................. 98 FIGURE 2-29: (NON-ARI) COMPLETER ID .................................................................................... 98 FIGURE 2-30: ARI COMPLETER ID................................................................................................ 99 FIGURE 2-31: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 105 FIGURE 2-32: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 107 FIGURE 2-33: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 112 FIGURE 2-34: VIRTUAL CHANNEL CONCEPT AN ILLUSTRATION .............................................. 129 FIGURE 2-35: VIRTUAL CHANNEL CONCEPT SWITCH INTERNALS (UPSTREAM FLOW) ............. 129 FIGURE 2-36: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 132 FIGURE 2-37: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 133

12

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 2-38: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY PROTECTION ........................................................................................................................ 148 FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 155 FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 157 FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED FRAMING ............................................................................................................................. 163 FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 164 FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 166 FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 166 FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 166 FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 166 FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 167 FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 167 FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 168 FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 169 FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS ............................................................................................................................................. 171 FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 173 FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 180 FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART.......................................................... 181 FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 185 FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER.......................................... 191 FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 192 FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 193 FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 193 FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 196 FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 197 FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 197 FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 198 FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 198 FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL ............................................................... 200 FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A BLOCK ................................................................................................................................. 201 FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 202 FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 205 FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 207 FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 207 FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 208 FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 208 FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 215 FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING ...................... 217 FIGURE 4-20: EQUALIZATION FLOW............................................................................................ 223 FIGURE 4-21: ELECTRICAL IDLE EXIT ORDERED SET .................................................................. 234 FIGURE 4-22: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE ........ 249 FIGURE 4-23: DETECT SUBSTATE MACHINE ............................................................................... 251 FIGURE 4-24: POLLING SUBSTATE MACHINE .............................................................................. 259

13

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 4-25: FIGURE 4-26: FIGURE 4-27: FIGURE 4-28: FIGURE 4-29: FIGURE 4-30: FIGURE 4-31: FIGURE 4-32: FIGURE 4-33: FIGURE 4-34: FIGURE 4-35: FIGURE 4-36: FIGURE 4-37: FIGURE 4-38: FIGURE 4-39: FIGURE 4-40: FIGURE 4-41: FIGURE 4-42: FIGURE 4-43: FIGURE 4-44: FIGURE 4-45: FIGURE 4-46: FIGURE 4-47: FIGURE 4-48: FIGURE 4-49: FIGURE 4-50: FIGURE 4-51: FIGURE 4-52: FIGURE 4-53: FIGURE 4-54: FIGURE 4-55: FIGURE 4-56: FIGURE 4-57: FIGURE 4-58: FIGURE 4-59: FIGURE 4-60: FIGURE 4-61: FIGURE 4-62: FIGURE 4-63: FIGURE 4-64: FIGURE 4-65: FIGURE 4-66: FIGURE 4-67: FIGURE 4-68: FIGURE 4-69: FIGURE 4-70:

CONFIGURATION SUBSTATE MACHINE .................................................................. 275 RECOVERY SUBSTATE MACHINE........................................................................... 296 L0S SUBSTATE MACHINE ...................................................................................... 303 L1 SUBSTATE MACHINE ........................................................................................ 305 L2 SUBSTATE MACHINE ........................................................................................ 306 LOOPBACK SUBSTATE MACHINE ........................................................................... 312 TRANSMITTER, CHANNEL, AND RECEIVER BOUNDARIES ...................................... 325 REQUIRED SETUP FOR CHARACTERIZING A 5.0 GT/S TRANSMITTER ..................... 326 ALLOWABLE SETUP FOR CHARACTERIZING A 2.5 GT/S TRANSMITTER ................. 326 TX TEST BOARD EXAMPLE.................................................................................... 327 SINGLE-ENDED AND DIFFERENTIAL LEVELS.......................................................... 329 FULL SWING SIGNALING VOLTAGE PARAMETERS SHOWING -6 DB DE-EMPHASIS 330 REDUCED SWING TX PARAMETERS ....................................................................... 330 MINIMUM PULSE WIDTH DEFINITION ................................................................... 331 FULL SWING TX PARAMETERS SHOWING DE-EMPHASIS ....................................... 332 MEASURING FULL SWING/DE-EMPHASIZED VOLTAGES FROM EYE DIAGRAM ...... 333 TX EQUALIZATION FIR REPRESENTATION ............................................................ 335 DEFINITION OF TX VOLTAGE LEVELS AND EQUALIZATION RATIOS ...................... 336 WAVEFORM MEASUREMENT POINTS FOR PRE-SHOOT AND DE-EMPHASIS ............ 337 VTX-FS-NO-EQ MEASUREMENT ................................................................................ 340 TXEQ COEFFICIENT SPACE TRIANGULAR MATRIX EXAMPLE ............................... 341 MEASURING VTX-EIEOS-FS AND VTX-EIEOS-RS ........................................................... 342 COMPLIANCE PATTERN AND RESULTING PACKAGE LOSS TEST WAVEFORM ........ 343 TRANSMITTER MARGINING VOLTAGE LEVELS AND CODES .................................. 344 PLOT OF TRANSMITTER HPF FILTER FUNCTIONS .................................................. 346 ALGORITHM TO REMOVE DE-EMPHASIS INDUCED JITTER ..................................... 347 EXAMPLE OF DE-EMPHASIS JITTER REMOVAL....................................................... 348 RELATION BETWEEN DATA EDGE PDFS AND RECOVERED DATA CLOCK ............. 350 DERIVATION OF TTX-UTJ AND TTX-UDJDD ................................................................ 350 PWJ RELATIVE TO CONSECUTIVE EDGES 1 UI APART .......................................... 351 DEFINITION OF TTX-UPW-DJDD AND TTX-UPW-TJ ........................................................ 352 TX, RX DIFFERENTIAL RETURN LOSS MASK ......................................................... 352 TX, RX COMMON MODE RETURN LOSS MASK ...................................................... 353 CALIBRATION CHANNEL VALIDATION .................................................................. 360 CALIBRATION CHANNEL SHOWING TMIN-PULSE ...................................................... 360 CALIBRATION CHANNEL |S11| PLOT WITH TOLERANCE LIMITS .............................. 361 SETUP FOR CALIBRATING RECEIVER TEST CIRCUIT INTO A REFERENCE LOAD ..... 362 SETUP FOR TESTING RECEIVER ............................................................................. 362 RECEIVER EYE MARGINS ...................................................................................... 365 SIGNAL AT RECEIVER REFERENCE LOAD SHOWING MIN/MAX SWING.................. 366 RX TESTBOARD TOPOLOGY................................................................................... 367 INSERTION LOSS GUIDELINES FOR CALIBRATION/BREAKOUT CHANNELS ............. 368 BEHAVIORAL CDR MODEL FOR RX MEASUREMENT ............................................ 369 TRANSFER FUNCTION FOR BEHAVIORAL CTLE .................................................... 370 LOSS CURVES FOR BEHAVIORAL CTLE ................................................................ 370 EQUATION AND FLOW DIAGRAM FOR 1-TAP DFE ................................................. 371

14

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 4-71: SETUP FOR CALIBRATING THE STRESSED VOLTAGE EYE ...................................... 372 FIGURE 4-72: LAYOUT FOR STRESSED VOLTAGE TESTING OF RECEIVER .................................... 374 FIGURE 4-73: LAYOUT FOR CALIBRATING THE STRESSED JITTER EYE ........................................ 375 FIGURE 4-74: SWEPT SJ MASK .................................................................................................... 376 FIGURE 4-75: LAYOUT FOR JITTER TESTING COMMON REFCLK RX ............................................ 377 FIGURE 4-76: LAYOUT FOR JITTER TESTING DATA CLOCKED REFCLK RX .................................. 377 FIGURE 4-77: EXIT FROM IDLE VOLTAGE AND TIME MARGINS ................................................... 381 FIGURE 4-78: A 30 KHZ BEACON SIGNALING THROUGH A 75 NF CAPACITOR ............................ 386 FIGURE 4-79: BEACON, WHICH INCLUDES A 2-NS PULSE THROUGH A 75 NF CAPACITOR ........... 386 FIGURE 4-80: SIMULATION ENVIRONMENT FOR CHARACTERIZING CHANNEL............................. 389 FIGURE 4-81: EXTRACTING EYE MARGINS FROM CHANNEL SIMULATION RESULTS ................... 392 FIGURE 4-82: MULTI-SEGMENT CHANNEL EXAMPLE .................................................................. 393 FIGURE 4-83: FLOW DIAGRAM FOR CHANNEL TOLERANCING..................................................... 394 FIGURE 4-84: TX/RX BEHAVIORAL PACKAGE MODELS .............................................................. 395 FIGURE 4-85: BEHAVIORAL TX AND RX S-PARAMETER FILE DETAILS ....................................... 395 FIGURE 4-86: DERIVATION OF JITTER PARAMETERS IN TABLE 4-26............................................ 398 FIGURE 4-87: EH, EW MASK ...................................................................................................... 398 FIGURE 4-88: REFCLK TEST SETUP ............................................................................................. 401 FIGURE 4-89: COMMON REFCLK RX ARCHITECTURE .................................................................. 402 FIGURE 4-90: REFCLK TRANSPORT DELAY PATHS FOR A COMMON REFCLK RX ARCHITECTURE 403 FIGURE 4-91: DATA CLOCKED RX ARCHITECTURE ..................................................................... 405 FIGURE 4-92: SEPARATE REFCLK ARCHITECTURE ...................................................................... 407 FIGURE 4-93: 8.0 GT/S COMMON REFCLK RX ARCHITECTURE WITH N, LIMITS ..................... 409 FIGURE 4-94: 8.0 GT/S DATA CLOCKED RX ARCHITECTURE WITH N, LIMITS ........................ 411 FIGURE 5-1: LINK POWER MANAGEMENT STATE FLOW DIAGRAM ............................................. 417 FIGURE 5-2: ENTRY INTO THE L1 LINK STATE ............................................................................ 425 FIGURE 5-3: EXIT FROM L1 LINK STATE INITIATED BY UPSTREAM COMPONENT ........................ 428 FIGURE 5-4: CONCEPTUAL DIAGRAMS SHOWING TWO EXAMPLE CASES OF WAKE# ROUTING . 431 FIGURE 5-5: A CONCEPTUAL PME CONTROL STATE MACHINE .................................................. 435 FIGURE 5-6: L1 TRANSITION SEQUENCE ENDING WITH A REJECTION (L0S ENABLED)................ 448 FIGURE 5-7: L1 SUCCESSFUL TRANSITION SEQUENCE ................................................................ 449 FIGURE 5-8: EXAMPLE OF L1 EXIT LATENCY COMPUTATION ..................................................... 450 FIGURE 6-1: ERROR CLASSIFICATION .......................................................................................... 465 FIGURE 6-2: FLOWCHART SHOWING SEQUENCE OF DEVICE ERROR SIGNALING AND LOGGING OPERATIONS ........................................................................................................................ 479 FIGURE 6-3: PSEUDO LOGIC DIAGRAM FOR ERROR MESSAGE CONTROLS .................................. 480 FIGURE 6-4: TC FILTERING EXAMPLE ......................................................................................... 490 FIGURE 6-5: TC TO VC MAPPING EXAMPLE ............................................................................... 491 FIGURE 6-6: AN EXAMPLE OF TRAFFIC FLOW ILLUSTRATING INGRESS AND EGRESS .................. 492 FIGURE 6-7: AN EXAMPLE OF DIFFERENTIATED TRAFFIC FLOW THROUGH A SWITCH ................ 493 FIGURE 6-8: SWITCH ARBITRATION STRUCTURE ......................................................................... 494 FIGURE 6-9: VC ID AND PRIORITY ORDER AN EXAMPLE......................................................... 495 FIGURE 6-10: MULTI-FUNCTION ARBITRATION MODEL.............................................................. 498 FIGURE 6-11: ROOT COMPLEX REPRESENTED AS A SINGLE COMPONENT ................................... 530 FIGURE 6-12: ROOT COMPLEX REPRESENTED AS MULTIPLE COMPONENTS ................................ 531 FIGURE 6-13: EXAMPLE SYSTEM TOPOLOGY WITH ARI DEVICES ............................................... 544

15

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 6-14: SEGMENTATION OF THE MULTICAST ADDRESS RANGE ......................................... 546 FIGURE 6-15: LATENCY FIELDS FORMAT FOR LTR MESSAGES ................................................... 564 FIGURE 6-16: CLKREQ# AND CLOCK POWER MANAGEMENT ................................................... 568 FIGURE 6-17: USE OF LTR AND CLOCK POWER MANAGEMENT.................................................. 569 FIGURE 6-18: CODES AND EQUIVALENT WAKE# PATTERNS ...................................................... 571 FIGURE 6-19: EXAMPLE PLATFORM TOPOLOGY SHOWING A LINK WHERE OBFF IS CARRIED BY MESSAGES ........................................................................................................................... 572 FIGURE 7-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ................................................... 576 FIGURE 7-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................................ 576 FIGURE 7-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT ...................................................... 577 FIGURE 7-4: COMMON CONFIGURATION SPACE HEADER ............................................................ 588 FIGURE 7-5: TYPE 0 CONFIGURATION SPACE HEADER ................................................................ 595 FIGURE 7-6: TYPE 1 CONFIGURATION SPACE HEADER ................................................................ 597 FIGURE 7-7: POWER MANAGEMENT CAPABILITIES REGISTER ..................................................... 601 FIGURE 7-8: POWER MANAGEMENT STATUS/CONTROL REGISTER.............................................. 602 FIGURE 7-9: VECTOR CONTROL FOR MSI-X TABLE ENTRIES ..................................................... 603 FIGURE 7-10: PCI EXPRESS CAPABILITY STRUCTURE ................................................................. 605 FIGURE 7-11: PCI EXPRESS CAPABILITY LIST REGISTER ............................................................ 605 FIGURE 7-12: PCI EXPRESS CAPABILITIES REGISTER ................................................................. 606 FIGURE 7-13: DEVICE CAPABILITIES REGISTER .......................................................................... 608 FIGURE 7-14: DEVICE CONTROL REGISTER ................................................................................. 613 FIGURE 7-15: DEVICE STATUS REGISTER .................................................................................... 620 FIGURE 7-16: LINK CAPABILITIES REGISTER............................................................................... 622 FIGURE 7-17: LINK CONTROL REGISTER ..................................................................................... 627 FIGURE 7-18: LINK STATUS REGISTER ........................................................................................ 635 FIGURE 7-19: SLOT CAPABILITIES REGISTER .............................................................................. 638 FIGURE 7-20: SLOT CONTROL REGISTER ..................................................................................... 640 FIGURE 7-21: SLOT STATUS REGISTER ....................................................................................... 644 FIGURE 7-22: ROOT CONTROL REGISTER.................................................................................... 646 FIGURE 7-23: ROOT CAPABILITIES REGISTER.............................................................................. 647 FIGURE 7-24: ROOT STATUS REGISTER ....................................................................................... 648 FIGURE 7-25: DEVICE CAPABILITIES 2 REGISTER ........................................................................ 649 FIGURE 7-26: DEVICE CONTROL 2 REGISTER .............................................................................. 654 FIGURE 7-27: LINK CAPABILITIES 2 REGISTER ............................................................................ 658 FIGURE 7-28: LINK CONTROL 2 REGISTER .................................................................................. 660 FIGURE 7-29: LINK STATUS 2 REGISTER ..................................................................................... 665 FIGURE 7-30: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT .................................. 668 FIGURE 7-31: PCI EXPRESS EXTENDED CAPABILITY HEADER .................................................... 669 FIGURE 7-32: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITY STRUCTURE ............................................................................................................................................. 671 FIGURE 7-33: ADVANCED ERROR REPORTING EXTENDED CAPABILITY HEADER ........................ 672 FIGURE 7-34: UNCORRECTABLE ERROR STATUS REGISTER ........................................................ 673 FIGURE 7-35: UNCORRECTABLE ERROR MASK REGISTER ........................................................... 675 FIGURE 7-36: UNCORRECTABLE ERROR SEVERITY REGISTER ..................................................... 677 FIGURE 7-37: CORRECTABLE ERROR STATUS REGISTER ............................................................. 679 FIGURE 7-38: CORRECTABLE ERROR MASK REGISTER ............................................................... 680

16

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-39: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER ................................ 681 FIGURE 7-40: HEADER LOG REGISTER ........................................................................................ 683 FIGURE 7-41: ROOT ERROR COMMAND REGISTER ...................................................................... 683 FIGURE 7-42: ROOT ERROR STATUS REGISTER ........................................................................... 685 FIGURE 7-43: ERROR SOURCE IDENTIFICATION REGISTER .......................................................... 687 FIGURE 7-44: TLP PREFIX LOG REGISTER .................................................................................. 688 FIGURE 7-45: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE ................................. 689 FIGURE 7-46: VIRTUAL CHANNEL EXTENDED CAPABILITY HEADER .......................................... 690 FIGURE 7-47: PORT VC CAPABILITY REGISTER 1 ....................................................................... 691 FIGURE 7-48: PORT VC CAPABILITY REGISTER 2 ....................................................................... 692 FIGURE 7-49: PORT VC CONTROL REGISTER .............................................................................. 693 FIGURE 7-50: PORT VC STATUS REGISTER ................................................................................. 694 FIGURE 7-51: VC RESOURCE CAPABILITY REGISTER .................................................................. 695 FIGURE 7-52: VC RESOURCE CONTROL REGISTER...................................................................... 697 FIGURE 7-53: VC RESOURCE STATUS REGISTER ......................................................................... 699 FIGURE 7-54: EXAMPLE VC ARBITRATION TABLE WITH 32 PHASES ........................................... 701 FIGURE 7-55: EXAMPLE PORT ARBITRATION TABLE WITH 128 PHASES AND 2-BIT TABLE ENTRIES ............................................................................................................................................. 702 FIGURE 7-56: PCI EXPRESS DEVICE SERIAL NUMBER CAPABILITY STRUCTURE......................... 703 FIGURE 7-57: DEVICE SERIAL NUMBER EXTENDED CAPABILITY HEADER .................................. 704 FIGURE 7-58: SERIAL NUMBER REGISTER ................................................................................... 705 FIGURE 7-59: PCI EXPRESS ROOT COMPLEX LINK DECLARATION CAPABILITY ......................... 706 FIGURE 7-60: ROOT COMPLEX LINK DECLARATION EXTENDED CAPABILITY HEADER ............... 707 FIGURE 7-61: ELEMENT SELF DESCRIPTION REGISTER ............................................................... 708 FIGURE 7-62: LINK ENTRY .......................................................................................................... 709 FIGURE 7-63: LINK DESCRIPTION REGISTER ............................................................................... 709 FIGURE 7-64: LINK ADDRESS FOR LINK TYPE 0 .......................................................................... 711 FIGURE 7-65: LINK ADDRESS FOR LINK TYPE 1 .......................................................................... 712 FIGURE 7-66: ROOT COMPLEX INTERNAL LINK CONTROL CAPABILITY ...................................... 713 FIGURE 7-67: ROOT INTERNAL LINK CONTROL EXTENDED CAPABILITY HEADER ...................... 713 FIGURE 7-68: ROOT COMPLEX LINK CAPABILITIES REGISTER .................................................... 714 FIGURE 7-69: ROOT COMPLEX LINK CONTROL REGISTER .......................................................... 717 FIGURE 7-70: ROOT COMPLEX LINK STATUS REGISTER.............................................................. 719 FIGURE 7-71: PCI EXPRESS POWER BUDGETING CAPABILITY STRUCTURE ................................. 720 FIGURE 7-72: POWER BUDGETING EXTENDED CAPABILITY HEADER .......................................... 721 FIGURE 7-73: POWER BUDGETING DATA REGISTER .................................................................... 722 FIGURE 7-74: POWER BUDGET CAPABILITY REGISTER ............................................................... 724 FIGURE 7-75: ACS EXTENDED CAPABILITY ................................................................................ 725 FIGURE 7-76: ACS EXTENDED CAPABILITY HEADER ................................................................. 725 FIGURE 7-77: ACS CAPABILITY REGISTER ................................................................................. 726 FIGURE 7-78: ACS CONTROL REGISTER ..................................................................................... 727 FIGURE 7-79: EGRESS CONTROL VECTOR REGISTER ................................................................... 730 FIGURE 7-80: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION CAPABILITY ......... 731 FIGURE 7-81: ROOT COMPLEX EVENT COLLECTOR ENDPOINT ASSOCIATION EXTENDED CAPABILITY HEADER ........................................................................................................... 731 FIGURE 7-82: PCI EXPRESS MFVC CAPABILITY STRUCTURE ..................................................... 733

17

PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-83: MFVC EXTENDED CAPABILITY HEADER .............................................................. 733 FIGURE 7-84: PORT VC CAPABILITY REGISTER 1 ....................................................................... 734 FIGURE 7-85: PORT VC CAPABILITY REGISTER 2 ....................................................................... 736 FIGURE 7-86: PORT VC CONTROL REGISTER .............................................................................. 737 FIGURE 7-87: PORT VC STATUS REGISTER ................................................................................. 738 FIGURE 7-88: VC RESOURCE CAPABILITY REGISTER .................................................................. 738 FIGURE 7-89: VC RESOURCE CONTROL REGISTER...................................................................... 740 FIGURE 7-90: VC RESOURCE STATUS REGISTER ......................................................................... 742 FIGURE 7-91: PCI EXPRESS VSEC STRUCTURE .......................................................................... 746 FIGURE 7-92: VENDOR-SPECIFIC EXTENDED CAPABILITY HEADER ............................................ 746 FIGURE 7-93: VENDOR-SPECIFIC HEADER .................................................................................. 747 FIGURE 7-94: ROOT COMPLEX FEATURES CAPABILITY STRUCTURE ........................................... 748 FIGURE 7-95: RCRB HEADER EXTENDED CAPABILITY HEADER ................................................ 748 FIGURE 7-96: VENDOR ID AND DEVICE ID ................................................................................. 749 FIGURE 7-97: RCRB CAPABILITIES ............................................................................................ 750 FIGURE 7-98: RCRB CONTROL ................................................................................................... 750 FIGURE 7-99: MULTICAST EXTENDED CAPABILITY STRUCTURE ................................................. 751 FIGURE 7-100: MULTICAST EXTENDED CAPABILITY HEADER .................................................... 751 FIGURE 7-101: MULTICAST CAPABILITY REGISTER .................................................................... 752 FIGURE 7-102: MULTICAST CONTROL REGISTER ........................................................................ 753 FIGURE 7-103: MC_BASE_ADDRESS REGISTER ......................................................................... 754 FIGURE 7-104: MC_RECEIVE REGISTER ..................................................................................... 754 FIGURE 7-105: MC_BLOCK_ALL REGISTER ............................................................................... 755 FIGURE 7-106: MC_BLOCK_UNTRANSLATED REGISTER ............................................................ 756 FIGURE 7-107: MC_OVERLAY_BAR.......................................................................................... 757 FIGURE 7-108: RESIZABLE BAR CAPABILITY ............................................................................. 759 FIGURE 7-109: RESIZABLE BAR EXTENDED CAPABILITY HEADER............................................. 759 FIGURE 7-110: RESIZABLE BAR CAPABILITY REGISTER............................................................. 760 FIGURE 7-111: RESIZABLE BAR CONTROL REGISTER ................................................................ 761 FIGURE 7-112: ARI CAPABILITY ................................................................................................. 762 FIGURE 7-113: ARI CAPABILITY HEADER .................................................................................. 763 FIGURE 7-114: ARI CAPABILITY REGISTER ................................................................................ 763 FIGURE 7-115: ARI CONTROL REGISTER .................................................................................... 764 FIGURE 7-116: DYNAMIC POWER ALLOCATION CAPABILITY STRUCTURE .................................. 765 FIGURE 7-117: DPA EXTENDED CAPABILITY HEADER ............................................................... 765 FIGURE 7-118: DPA CAPABILITY REGISTER ............................................................................... 766 FIGURE 7-119: DPA LATENCY INDICATOR REGISTER ................................................................. 767 FIGURE 7-120: DPA STATUS REGISTER ...................................................................................... 767 FIGURE 7-121: DPA CONTROL REGISTER ................................................................................... 768 FIGURE 7-122: DPA POWER ALLOCATION ARRAY ..................................................................... 768 FIGURE 7-123: LTR EXTENDED CAPABILITY STRUCTURE .......................................................... 769 FIGURE 7-124: LTR EXTENDED CAPABILITY HEADER ................................................................ 769 FIGURE 7-125: MAX SNOOP LATENCY REGISTER ....................................................................... 770 FIGURE 7-126: MAX NO-SNOOP LATENCY REGISTER ................................................................. 770 FIGURE 7-127: TPH EXTENDED CAPABILITY STRUCTURE .......................................................... 771 FIGURE 7-128: TPH REQUESTER EXTENDED CAPABILITY HEADER ............................................ 772

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

FIGURE 7-129: TPH REQUESTER CAPABILITY REGISTER ............................................................ 772 FIGURE 7-130: TPH REQUESTER CONTROL REGISTER ................................................................ 774 FIGURE 7-131: TPH ST TABLE ................................................................................................... 775 FIGURE 7-132: SECONDARY PCI EXPRESS EXTENDED CAPABILITY STRUCTURE ........................ 776 FIGURE 7-133: SECONDARY PCI EXPRESS EXTENDED CAPABILITY HEADER.............................. 776 FIGURE 7-134: LINK CONTROL 3 REGISTER ................................................................................ 777 FIGURE 7-135: LANE ERROR STATUS REGISTER ......................................................................... 778 FIGURE 7-136: LANE EQUALIZATION CONTROL REGISTER ......................................................... 778 FIGURE 7-137: LANE ((MAXIMUM LINK WIDTH 1):0) EQUALIZATION CONTROL REGISTER .... 779 FIGURE A-1: AN EXAMPLE SHOWING ENDPOINT-TO-ROOT-COMPLEX AND PEER-TO-PEER COMMUNICATION MODELS .................................................................................................. 784 FIGURE A-2: TWO BASIC BANDWIDTH RESOURCING PROBLEMS: OVER-SUBSCRIPTION AND CONGESTION ........................................................................................................................ 785 FIGURE A-3: A SIMPLIFIED EXAMPLE ILLUSTRATING PCI EXPRESS ISOCHRONOUS PARAMETERS ............................................................................................................................................. 790 FIGURE C-1: SCRAMBLING SPECTRUM AT 2.5 GT/S FOR DATA VALUE OF 0 ............................... 810 FIGURE E-1: REFERENCE TOPOLOGY FOR IDO USE .................................................................... 819 FIGURE G-1: DEVICE AND PROCESSOR CONNECTED USING A PMUX LINK ................................ 827 FIGURE G-2: PMUX LINK .......................................................................................................... 828 FIGURE G-3: PMUX PACKET FLOW THROUGH THE LAYERS ...................................................... 829 FIGURE G-4: PMUX PACKET ...................................................................................................... 836 FIGURE G-5: TLP AND PMUX PACKET FRAMING (8B10B ENCODING)....................................... 837 FIGURE G-6: TLP AND PMUX PACKET FRAMING (128B/130B ENCODING)................................ 839 FIGURE G-7: PMUX EXTENDED CAPABILITY ............................................................................. 843 FIGURE G-8: PMUX EXTENDED CAPABILITY HEADER ............................................................... 843 FIGURE G-9: PMUX CAPABILITY REGISTER ............................................................................... 844 FIGURE G-10: PMUX CONTROL REGISTER................................................................................. 846 FIGURE G-11: PMUX STATUS REGISTER .................................................................................... 847 FIGURE G-12: PMUX PROTOCOL ARRAY ENTRY ....................................................................... 850

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PCI EXPRESS BASE SPECIFICATION, REV. 3.0

TablesTABLE 2-1: TRANSACTION TYPES FOR DIFFERENT ADDRESS SPACES ........................................... 54 TABLE 2-2: FMT[2:0] FIELD VALUES ............................................................................................ 59 TABLE 2-3: FMT[2:0] AND TYPE[4:0] FIELD ENCODINGS .............................................................. 60 TABLE 2-4: LENGTH[9:0] FIELD ENCODING .................................................................................. 61 TABLE 2-5: ADDRESS TYPE (AT) FIELD ENCODINGS .................................................................... 66 TABLE 2-6: ADDRESS FIELD MAPPING .......................................................................................... 66 TABLE 2-7: HEADER FIELD LOCATIONS FOR NON-ARI ID ROUTING ............................................. 68 TABLE 2-8: HEADER FIELD LOCATIONS FOR ARI ID ROUTING..................................................... 68 TABLE 2-9: BYTE ENABLES LOCATION AND CORRESPONDENCE ................................................... 70 TABLE 2-10: ORDERING ATTRIBUTES ........................................................................................... 75 TABLE 2-11: CACHE COHERENCY MANAGEMENT ATTRIBUTE...................................................... 76 TABLE 2-12: DEFINITION OF TC FIELD ENCODINGS ...................................................................... 76 TABLE 2-13: LENGTH FIELD VALUES FOR ATOMICOP REQUESTS ................................................. 77 TABLE 2-14: TPH TLP PREFIX BIT MAPPING ............................................................................... 81 TABLE 2-15: LOCATION OF PH[1:0] IN TLP HEADER.................................................................... 82 TABLE 2-16: PROCESSING HINT ENCODING .................................................................................. 82 TABLE 2-17: LOCATION OF ST[7:0] IN TLP HEADERS .................................................................. 83 TABLE 2-18: MESSAGE ROUTING .................................................................................................. 85 TABLE 2-19: INTX MECHANISM MESSAGES ................................................................................. 86 TABLE 2-20: BRIDGE MAPPING FOR INTX VIRTUAL WIRES ......................................................... 88 TABLE 2-21: POWER MANAGEMENT MESSAGES ........................................................................... 90 TABLE 2-22: ERROR SIGNALING MESSAGES ................................................................................. 91 TABLE 2-23: UNLOCK MESSAGE ................................................................................................... 92 TABLE 2-24: SET_SLOT_POWER_LIMIT MESSAGE ....................................................................... 92 TABLE 2-25: VENDOR_DEFINED MESSAGES ................................................................................. 93 TABLE 2-26: IGNORED MESSAGES ................................................................................................ 95 TABLE 2-27: LTR MESSAGE ................................................