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Microsoft PowerPoint - 1_Paper_ID_1267_Yukinori_MORITA.ppt [Compatibility Mode]P f Li it f P ll l El t i Fi ld Performance Limit of Parallel Electric Field Tunnel FET and Improvement by Modified Gate
d Ch l C fi tiand Channel Configurations
Yukinori Morita Takahiro Mori Shinji MigitaYukinori Morita, Takahiro Mori, Shinji Migita, Wataru Mizubayashi, Akihito Tanabe, Koichi Fukuda, Takashi Matsukawa, Kazuhiko Endo, Shin-ichi O’uchi, Yongxun Liu, Meishoku Masahara, and Hiroyuki Ota
Green Nanoelectronics Center(GNC) Nanoelectronics Research Institute (NeRI)
AIST JapanAIST Japan
- Why tunnel FET (TFET)
P ll l l t i fi ld TFET (PE TFET)- Parallel electric field TFET (PE-TFET)
Performance of PE-TFET
Device fabrication- Device fabrication
lo g(
I d )
lo g(
Ioff 60 V/d
VddVdd VddVdd
Conventionally Vdd scaling causes a significant increase in Ioff due to the lower limit of SS (~60mV/dec.) V li ith t I i b d b t i th SS
3
Vdd scaling without Ioff increase can be done by steepening the SS
MOSFET Tunnel FET
Why tunnel FET ?
n+ p p+
Carrier flow is determined by BTBT transport mechanism
4
Lateral & vertical TFETs • Two TFET architectures
Lateral (conventional) TFET Vertical (parallel electric field) TFET
Two TFET architectures
L : Overlap length
BTBT is limited in interface -->> Small ID
BTBT area is enlarged C H t l VLSI TSA 2008 14 (2008)>> Small ID
5
C. Hu et.al., VLSI-TSA 2008, 14 (2008) R. Li et.al., Phys. Status Solidi C 9, 389 (2012) Y. Morita et.al, Jpn. J. Appl. Phys. 52, 04CC25 (2013)
Objective of this work
Performance of the parallel electric field TFET (PE TFET) relation between ON current and (PE-TFET), relation between ON current and overlap length, is analyzed.
Proposal of modified TFET architecture to improve l t t ti (S th ti l t i fi ld TFET)electrostatics (Synthetic electric field TFET)
6
Fabrication of PE-TFET with epichannel
SOI mesa etching (a) P I/I (b) BF2 I/I (c)
Si epitaxial growth, high-k and gate (d) Gate stack etch (e) Contact
50( ) (b) 5
Mask
(c)
Operation of p- & n-PE-TFETs
1.2 (a) 101(b)
S D
A/
10-5
100 101 102 103 1040 0 80 LOV (nm) LOV (nm)
Confirming ID increase with increasing LOVConfirming ID increase with increasing LOV ON current degraded at LOV > 1000 nm
10
( )
( d )Gate
y g
(x) VD
dv(x)dv(x) dx- = Rci(x)
di(x) dx- = Gv(x)
In ideal case (RS ~ 0), i-v relation can be describes as,
dx ( )
11
2 R C
G V D
(b) G
S D
1.2
1.6
Considering RS 10-3I D
C s g S
LOV (nm) LOV (nm)
12
VD~
I G VIONMAX ~ G RC
VD
Trade off Enhancing G <<-->> Reducing RCEnhancing G << >> Reducing RC
Balance between tunnel conductance and h l i t i iti l
13
14
Lateral TFET Synthetic electric field TFET (a)
Ultrathin undoped channel
IT BOX
(b) (c) (d)(a) As ion implantation
MaskMask Mask BF2 ion implantation
(b) (c) (d)
Mesa-etching(e) Gate insulator & Gate electrode
(f) Gate etch(g)
Epitaxial h l
Gate electrode (TiN)
IT
Gate
IT
18
Simulation of electric field
• Electric field at edges is enlarged by SE-effect. • Scaling of channel thickness and width enhances
SE-effect
EC
9x104
3x105
19
102 ID-VG
4
10-2
Slide 20
L 400 V = 1 V
2 0
VG = -2 V
1.0 DEPI = 16 nm0.7 uA
0.0 0 5 10 15 20 W (um) 5 4 10 3 A/
0.2 uA
Slide 21
21
L 400 V = 1 V
2 0
VG = -2 V
1.0 DEPI = 16 nm0.7 uA
0.0 0 5 10 15 20 W (um) 5 4 10 3 A/
0.2 uA
Slide 22
22
102
100
102
n+ Sn+ S
60 70 -1.0 V V
G 0.1 V step
A/ um
) -0.9 V
OV
-2 -1 0 V
D (V)
Significant performance SS 58 I 4 uA/um @(V V ) ( 0 5 0 2 V)
24
SSMIN = 58, ID = 4 uA/um @(VG,VD)=(-0.5,-0.2 V) 400 uA/um @(VG,VD)=(-2,-1 V)
Summary
Parallel electric field TFET • Limit of ON current • Balance between tunnel conductance and channel Balance between tunnel conductance and channel
resistance is critical
S th ti l t i fi ld TFETSynthetic electric field TFET • Scaling induced performance enhancement • FinFET-like slim device is promising.p g. • Significant performance in small voltage
SSMIN = 58, ID = 4 uA/um @(VG,VD)=(-0.5,-0.2 V) 400 A/ @(V V ) ( 2 1 V)400 uA/um @(VG,VD)=(-2,-1 V)
• The concept can be applicable to Ge or III-V TFETs.
25
The concept can be applicable to Ge or III V TFETs.
Acknowledgement
This research was supported by JSPS through the First Program, “Development of Core Technologies
for Green Nanoelectronics”.
Slide 2626
102 um
) [1] G. Zhou, et al., IEDM 2012 [2] A. Villalon, et al., VLSI2012 [3] G. Dewey, et al., IEDM 2011
[1]
[5] K. Tomioka, et al., VLSI2012
[2] [3] (0.3V)
Blue: III-V
SS (mV/dec)
Our data (No strain, no Ge, no metal SD, only by device consideration)
Impact of LOV
WCH = 10 um
0 15
Slide 28
LOV (nm)
p+ Source
BTBT IT
BTBT window
Slide 29
DEPI 7 nm
, 1,E+00 1,E+01 1,E+02 1,E+03 1,E+04 1,E+05
WFIN (nm)
SIMS analysis of dopant profiles
• Dopant steepness in the epitaxial channel is maintained  below 900 C.
1020
1021
C
Do
o
B
Gate ID-VG
EC
V G (V)Parallel electric field TFET
This work This work This work This work Villalon et al VLSI2012
[8]
Dewey et al IEDM2011
[11] Types p p p p p p p n n nTypes p p p p p p p n n n
Materials Si Si Si Si SiGe30% SiGe30% Si GaSb/InAs GaSb/InAs InGaAs Structures DL Fin DL Fin DL Fin DL Fin ETSOI ETSOI Nanowire Vertical Vertical Vertical
Boosters DL Fin DL Fin DL Fin DL Fin Strain Strain Strain M t l S/D III-V III-V III-VMetal S/D
VD (V) -1 -1 -0.2 -0.2 -1 -1 -0.5 1 0.5 0.3 VG (V) -2 -1 -1 -0.5 -2 -1 -1 1 0.5 ~0.48
VON-VOFF (V) -2 -1 -1 -0.5 -2 -1 -1 2 1.5 0.5(V) 0 5 5 0 5
ION (uA/um) 417 82 40 4 ~300 ~10 ~5 380 180 5.7 IMIN (uA/um) 2.00E-04 2.00E-04 2.00E-06 2.00E-06 3.70E-05 3.70E-05 ~2e-6 5.07E-02 3.00E-02 1.00E-04
ION/IMIN 2.09E+06 4.10E+05 2.00E+07 2.00E+06 8.11E+06 2.70E+05 2.50E+06 7.50E+03 6.00E+03 5.70E+04 SSMIN
(mV/dec) 70 70 58 58 ~120 ~120 90 200 200 58
EOT (nm) 1.3 1.3 1.3 1.3 1.25 1.25 3 nm HfO2 1.3 1.3 1.1 LG (nm) 60 60 60 60 200 200 200 - - 100
ID-VG of SE-TFETs
100 D
V (V)
Tunability of LOV
35
source
sourceBOX
source
sourceBOX
sourceBOX
Slide 38