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5/99 i M0-0053 Q-Line Installation Manual Section Title Page Westinghouse Proprietary Class 2C Summary of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changes-1 Section 1. Introduction 1-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 Contents of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1-3 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Section 2. Field Wiring Procedures 2-1 Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-2 WDPF Field Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2-3 System Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2-4 Noise Minimization Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2-5 Thermocouple Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2-6 Common Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2-7 Field Termination Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2-8 “B” Cabinet Field Terminations and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2-9 Q-Card Hardware Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2-10 Using Address Selection Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36 2-11 Pre-Wiring Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2-12 Field Wiring Half-Shell Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2-13 Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2-14 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 Section 3. Q-Card Reference Sheets 3-1 Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 QAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-3 QAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 3-4 QAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 3-5 QAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-61 3-6 QAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74 3-7 QAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100 3-8 QAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119 3-9 QAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-148 3-10 QAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-173 3-11 QAXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-190 3-12 QAXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-193 3-13 QBE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-200 3-14 QBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-212 3-15 QBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-224

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Summary of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Change

Section 1. Introduction

1-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11-2 Contents of this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-3 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2. Field Wiring Procedures

2-1 Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 WDPF Field Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 System Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4 Noise Minimization Techniques. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 Thermocouple Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 Common Input Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2-7 Field Termination Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2-8 “B” Cabinet Field Terminations and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22-9 Q-Card Hardware Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 Using Address Selection Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 Pre-Wiring Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2-12 Field Wiring Half-Shell Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32-13 Environmental Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2-14 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Section 3. Q-Card Reference Sheets

3-1 Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 QAA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-143-3 QAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-373-4 QAH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-493-5 QAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-613-6 QAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-743-7 QAO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1003-8 QAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1193-9 QAW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-183-10 QAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1733-11 QAXD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103-12 QAXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-133-13 QBE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2003-14 QBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2123-15 QBO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-224

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3-16 QCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2353-17 QCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2543-18 QDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2653-19 QDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2663-20 QDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2763-21 QFR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2823-22 QIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-2833-23 QID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2963-24 QLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3173-25 QLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3183-26 QLJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3323-27 LIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3433-28 SLIM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3513-29 QMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3593-30 QPA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3653-31 QRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3983-32 QRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3993-33 QRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4103-34 QRS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4203-35 QRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4213-36 QSC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4533-37 QSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4583-38 QSE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4833-39 QSR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5123-40 QSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5413-41 QST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5523-42 QTB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5533-43 QTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5623-44 QVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-573

Appendix A. Worksheets

A-1. Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A

Appendix B. Setting Q-Card Addresses

B-1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

Appendix C. Card-Edge Field Termination

C-1. Section Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC-2. Card-Edge Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Glossary

Index

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-8-91567

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-2345

16-1617782323243738901

Section 1. Introduction

1-1. Phases of WDPF Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2. Field Wiring Procedures

2-1. Example Sort-by-Hardware Terminations List . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-2. Termination List Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-3. Amplitude Discrimination Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-4. Typical Noisy Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-5. Ideal Analog Signal Field Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 2-6. Typical Thermocouple Analog Signal Wiring by User . . . . . . . . . . . . . . . . . . . . . 2-1 2-7. Typical Sensor Analog Signal Wiring by User . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-8. QAXT Half-Shell Mounting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2-9. Standard “A” Cabinet and Field Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 2-10. Enhanced “B” Cabinet, Termination Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 2-11. Address Jumpers on Cable Connector (“B” Cabinet Terminations) . . . . . . . . . . . 2- 2-12. Q-Card Hardware Address Selection Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-13. Q-Card Number of Channels and Starting Address. . . . . . . . . . . . . . . . . . . . . . . . 2 2-14. Q-Card Hardware Address Selection Example . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2-15. Address Jumpering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Section 3. Q-Card Reference Sheets

3-1. Typical Q-Card Termination, “Standard” Cabinet . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-2. Typical Q-Card Termination, Remote “B” Cabinet . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-3. QAA G01 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-4. QAA G02 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-5. QAA Card Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-6. QAA Card Usage Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-7. QAA Card State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-8. QAA G01 Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-9. QAA G02 Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-10. QAA Mother Card Components, Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-11. QAA DWC Daughter Card Components, Test Points. . . . . . . . . . . . . . . . . . . . . . 3- 3-12. QAA DBK Daughter Card Components, Test Points . . . . . . . . . . . . . . . . . . . . . . 3- 3-13. QAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-14. QAC Block Diagram (Groups 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-15. QAC Block Diagram (Group 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-16. QAC Block Diagram (Group 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-17. QAC Block Diagram (Group 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

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Figure Title Page

1-45-484935555-579

06167890-712

3467-7891

-95002345

11121314

16

91456

3-18. QAC Block Diagram (Group 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-19. QAC Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-20. QAC Card Components (Indicators and test Points) . . . . . . . . . . . . . . . . . . . . . . . 3 3-21. QAH Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-22. QAH Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-23. QAH Card Front-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . 3- 3-24. QAH Word Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-25. QAH Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-26. QAH Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-27. QAH CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-28. QAI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-29. QAI Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-30. QAI Control Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-31. QAI Analog Point Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3-32. QAI Analog Point Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-33. QAI Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-34. QAI Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-35. QAI CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-36. QAM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-37. QAM Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-38. QAM Card Systems Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3-39. QAM Card Usage Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-40. QAM Card Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-41. QAM Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-42. QAO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-43. QAO Card Functional Block Diagram, 5-Level . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-44. QAO Point Block Diagram, 5- Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-45. QAO Card Functional Block Diagram, 6-Level and Later . . . . . . . . . . . . . . . . . 3-10 3-46. QAO Point Block Diagram, 6-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3-47. QAO Bipolar Output Voltage Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-48. QAO Unipolar Output Current Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-49. QAO Unipolar Output Voltage Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-50. QAO Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-51. QAO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-52. QAO CE MARK Wiring Diagram (Groups 1 & 7). . . . . . . . . . . . . . . . . . . . . . . 3-117 3-53. QAO CE MARK Wiring Diagram (Groups 2 through 6, & 8) . . . . . . . . . . . . . . 3-118 3-54. QAV Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3-55. QAV Typical Control System Using QAV Cards . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-56. QAV Analog Input Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-57. QAV Card Digital Circuits Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3-58. QAV Analog-to-Digital Conversion Process Flowchart . . . . . . . . . . . . . . . . . . . 3-12

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Figure Title Page

303133343635

480345759616263580

23838467

88

395978900204520708089

3-59. QAV Card Front-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 3-1 3-60. QAV Card Rear-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 3-1 3-61. QAV Card Output Data Pattern Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-62. QAV Card Components (Level 6 and earlier) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-63. QAV Card Components (Level 8 and later) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-64. QAV Wiring Diagram (QAV Groups 1 through 5) . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-65. Wiring Diagram, QAV to TSC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3-66. QAV CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-147 3-67. QAW Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-68. QAW Typical Control System Using QAW Cards . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-69. QAW Analog Input Circuits Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-70. QAW Digital Circuits Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3-71. QAW Card Rear-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 3-1 3-72. QAW Card Front-Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . 3-1 3-73. QAW Card Output Data Pattern Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-74. QAW Card Components (Level 7 and earlier) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-75. QAW Card Components (Level 9 and later) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-76. Wiring Diagram, QAW Groups 1,2,3,4, and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-77. Wiring Diagram: QAW Group 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3-78. Wiring Diagram, QAW to TSC Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-79. QAW CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-80. QAX Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3-81. QAX Output Data Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-82. QAX Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-83. QAX Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-84. QAX Shield Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3-85. QAX Recommended Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-86. QAX CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-189 3-87. QAXT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-88. QAXT Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-89. QAX Card with R75 Jumper Installed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-90. QAXT Standard Half-Shell Cabinet Installation . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3-91. QAXT Remote I/O Half-Shell Cabinet Installation. . . . . . . . . . . . . . . . . . . . . . . 3-19 3-92. QBE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-93. Typical, Multicrate, Q-Line System Using QBE Card Interfacing . . . . . . . . . . . 3-20 3-94. QBE Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-95. QBE Timing Diagram of the Operation of the Bus Discharge Circuit . . . . . . . . 3-20 3-96. QBE Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-97. QBE Transmit Mode Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-98. QBE Receive Mode Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-99. QBE No Level Shift Mode Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . 3-20

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Figure Title Page

131517900121

222426289

2313344040

24142434448

51

5235456589

2626346797071174

3-100. QBI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-101. QBI Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-102. Example of a QBI Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . 3-2 3-103. Typical G01 and G02 QBI Card – Point Wiring Diagram . . . . . . . . . . . . . . . . . 3-21 3-104. Typical G03, G04 and G05 QBI Card – Point Wiring Diagram . . . . . . . . . . . . . 3-22 3-105. Typical G06, G07, G09 and G10 QBI Card – Point Wiring Diagram. . . . . . . . . 3-22 3-106. Typical G08 and G11 QBI Card – Point Wiring Diagram . . . . . . . . . . . . . . . . . 3-22 3-107. QBI Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-108. QBI Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-109. QBO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-110. QBO Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-111. QBO Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-112. QBO Typical Point Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3-113. QBO Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-114. QBO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-115. QBO CE MARK Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3-116. QCA Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-117. QCA Channel Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-118. QCA Channel Range Adjustment Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-119. QCA Channel Offset Adjustment Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-120. QCA Output Gain Stage - Group 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-121. QCA Output Gain Stage - Group 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-122. QCA Card Outline and User Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-123. QCA Wiring Diagram (Group 1) (Using AMP-18 conductor 18 AWG wiring)

(3A99512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-124. QCA Wiring Diagram (Group 2) (Using AMP-18 conductor 18 AWG wiring)

(3A99512) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-125. QCA CE MARK Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3-126. QCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-127. QCI Card Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-128. QCI Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-129. Cable Length Limitations for QCI Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3-130. QCI Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-131. QCI Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-132. QCI CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3-133. QDI Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-134. QDI Card Address Jumper Assembly (Differential Input) . . . . . . . . . . . . . . . . . 3-26 3-135. QDI Card Address Jumper Assembly, Single Ended Input. . . . . . . . . . . . . . . . . 3-2 3-136. QDI G01 Point Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-137. QDI Typical Contact Input Point Wiring (G03, 05, 07, 08, 09, 10) . . . . . . . . . . 3-27 3-138. QDI Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

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Figure Title Page

757680838990670506080809

09101112134568192424

7

8

313233

337338404141

4243447

3-139. Wiring Diagram: QDI Groups 2, 4, 6, and 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-140. QDT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-141. QDT Card Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-142. QIC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-143. QIC Detailed Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-144. QIC Card Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3-145. QID Block Diagram, Double Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-146. QID Block Diagram, Single Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3-147. QID Card Address Jumper Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-148. QID Card Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-149. QID Group 1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-150. QID Group 8 and Group 17 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-151. QID Single Ended Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-152. QID Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-153. QID Wiring for Groups 2, 4, 6, 11, 13, and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-154. QID Card Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-155. QID Card Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-156. QID Card Connections (G10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-157. QID CE MARK Wiring Diagram (Groups 2, 4, 6, 11, 13 and 15) . . . . . . . . . . . 3-31 3-158. CE MARK Wiring Diagram (Groups 1, 3, 5, 7, 8, 9, 12, 14 and 16) . . . . . . . . . 3-31 3-159. CE MARK Wiring Diagram (Group 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3-160. QLI Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31 3-161. QLI Card Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-162. QLI Card Address Jumper Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-163. QLI Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-164. QLI Wiring Diagram: WDPF Powered, Local Grounding . . . . . . . . . . . . . . . . . 3-32 3-165. QLI Wiring Diagram: Digital I/O-WDPF Powered

Analog I/O-Self Powered with Remote Grounding . . . . . . . . . . . . . . . . . . . . . . . 3-32 3-166. QLI CE MARK Wiring Diagram (Analog Inputs Powered at Field Side) . . . . . 3-330 3-167. QLI CE MARK Wiring Diagram (Analog Inputs Powered at WDPF System Side)3-3 3-168. QLJ Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-169. QLJ Card Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-170. QLJ Card Address Jumper Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-171. QLJ Card Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-172. QLJ Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-173. QLJ Ground Inputs at System End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-174. QLJ Ground Inputs at Signal Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-175. QLJ Fused Half-Shell Extension Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-176. Loop Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-177. LIM Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3-178. Keyboards for Group 1 and Group 2 LIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

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3-179. LIM Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-348 3-180. SLIM Small Loop Interface Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3-181. SLIM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3-182. Keyboards for Group 1 and Group 2 SLIMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-183. SLIM Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3-184. QMT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-185. QMT Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3-186. QMT Card Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-187. QPA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-188. QPA +48 VDC Clock Input Signal Wiring (G01, G04) . . . . . . . . . . . . . . . . . . . 3-368 3-189. QPA Control Signal (+48 VDC) Input Wiring (G01, G02). . . . . . . . . . . . . . . . . 3-369 3-190. QPA+5 VDC Clock Input Signal Wiring (G02, G03) . . . . . . . . . . . . . . . . . . . . 3-370 3-191. QPA Clock Signal Wiring (Differential Line Driver) G02 and G03. . . . . . . . . . 3-371 3-192. QPA +5 VDC Control Input Wiring (G03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-372 3-193. QPA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-194. QPA Card Counter/Comparator (1 of 2) (G01, 2, 3) . . . . . . . . . . . . . . . . . . . . . . 3-3 3-195. QPA Card Counter/Comparator (2 of 2) (G04) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-196. QPA J2 Pin Connector (G01, 2 and 3) (Front View). . . . . . . . . . . . . . . . . . . . . . 3-3 3-197. QPA J3 Pin Connector (G01, 2, 3, and 4) (Front View) . . . . . . . . . . . . . . . . . . . 3-3 3-198. QPA Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-199. QPA Card Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-200. QPA Card Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-201. QPA Card Address Selection (Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-202. QPA Card Address Selection (Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-203. QPA Card Group Read Bit Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-204. QPA Card Used for Speed Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-205. QPA Card Used for Elapsed Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-206. QPA Used for Speed Ratio Measurement (For example, estimate

stretch of materials between two rollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-207. QPA Used for Average Inverse Speed Measurement . . . . . . . . . . . . . . . . . . . . . 3- 3-208. QPA Wiring Diagram, Groups 1 and 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-209. QPA Wiring Diagram, Groups 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-210. QPA CE MARK Wiring Diagram (Groups 1 and 4). . . . . . . . . . . . . . . . . . . . . . 3-39 3-211. QPA CE MARK Wiring Diagram (Group 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3-212. QPA CE MARK Wiring Diagram (Group 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3-213. QRF Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-214. QRF Card Jumpers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-215. QRF Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-216. QRF CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3-217. QRO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-218. QRO Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4

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3-219. QRO Safe Operating Area Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-220. QRO Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-221. QRO Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-222. QRO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-223. QRT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-224. Typical Control System Using QRT Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-225. QRT Card Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-226. QRT Card Output Dynamic Linear Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-227. QRT Card Bridge and I to F Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . 3-42 3-228. QRT Card Digital Circuits Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3-229. QRT Card Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-230. QRT Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-231. Bridge Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-232. RTDs and Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-233. QRT Wiring Diagram: Plant Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3-234. QRT Wiring Diagram: Cabinet Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3-235. QRT CE MARK Wiring Diagram (Grounded at the B Cabinet). . . . . . . . . . . . . 3-45 3-236. QRT CE MARK Wiring Diagram (Grounded in the Field) . . . . . . . . . . . . . . . . 3-452 3-237. QSC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-238. QSC Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-239. QSC Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-240. QSD Typical QSD Card Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3-241. QSD Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-242. QSD Card Input Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-243. QSD Card Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-244. EH and MH Actuator Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3-245. QSD Card Outline and User Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-246. QSD Analog Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-247. QSD CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48 3-248. QSE Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3-249. Contact Wiring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49 3-250. QSE Event Buffer Memory Arbitration Timing Chart . . . . . . . . . . . . . . . . . . . . 3-50 3-251. QSE LED Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-252. QSE Event Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-253. QSE Status Byte Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-254. QSE Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-255. QSE CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 3-256. QSR Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-257. Read Data Format for Reading Demand, Feedback, and Scale Factors . . . . . . . 3 3-258. Read Data Format for Reading Channel Valve-Type Assignments . . . . . . . . . . 3-5 3-259. Write Data Format for Sending Demands to a Channel . . . . . . . . . . . . . . . . . . . 3-5

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-1-2

3-260. QSR Card Outline and User Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-261. QSR Analog Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-262. QSR Wiring Diagram (Groups 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-263. QSR Wiring Diagram (Groups 2 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-264. QSR CE MARK Wiring Diagram (Groups 1 & 3) . . . . . . . . . . . . . . . . . . . . . . . 3-53 3-265. QSR CE MARK Wiring Diagram

(Groups 2 & 4 with B Cabinet Earth Grounding). . . . . . . . . . . . . . . . . . . . . . . . . 3-53 3-266. QSR CE MARK Wiring Diagram (Groups 2 & 4 with Field Earth Grounding) 3-540 3-267. QSS Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-268. QSS Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-269. QSS Speed Selection Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-270. QSS Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-271. QSS Wiring Diagram (Recommended) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-272. QSS Wiring Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-273. QSS CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55 3-274. QTB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-275. QTB Card Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-276. QTB Real Time Clock Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-277. QTB Output Signal Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-278. QTB Card Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-279. QTO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-280. TRIAC Zero Voltage Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56 3-281. TRIAC Operation with Load Current Below 75 mA. . . . . . . . . . . . . . . . . . . . . . 3-56 3-282. QTO Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-283. QTO Card Address Jumper Assembly Example . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-284. QTO Card Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 3-285. QTO Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-286. Example of QVP DIOB Base Address Selection . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-287. QVP Card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-580 3-288. QVP Wiring Diagram (Using #6 Screws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-289. QVP Wiring Diagram (Using #8 Screws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3-290. QVP CE MARK Wiring Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58

Appendix A. Worksheets

A-1. Q-card Hardware Address Selection Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A

Appendix B. Setting Q-Card Addresses

B-1. Address Jumpers on Cable Connector (“B” Cabinet Terminations) . . . . . . . . . . . . B B-2. Card Address Jumper Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B

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-2C-3-4

Appendix C. Card-Edge Field Termination

C-1. Address Jumpers on Card-Edge Termination Connector . . . . . . . . . . . . . . . . . . . . C C-2. Standard Card-Edge Field Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3. Screw-Down Terminal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C

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Table Title Page

. . . . 1-

. 2-. 2. 2-26. 2-27 . 2-40

. . . 3-4. 3-20 . 3-21 . 3-223-253-30. 3-32

. 3-33 . 3-34 . 3-42. 3-46. 3-47. 3-47. 3-47. 3-48 . 3-52. 3-56. 3-56 . 3-583-71

. 3-79 . 3-80. 3-84 . 3-86. 3-88

Section 1. Introduction

1-1. Available Q-Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4 1-2. Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Section 2. Field Wiring Procedures

2-1. Noise Class Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2-2. “B” Cabinet Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -23 2-3. Enhanced Half-Shell Terminal Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4. Half-Shell to Q-Card Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5. Power Consumption and Heat Load for Q-Cards. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 3. Q-Card Reference Sheets

3-1. Q-Card Groups and Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2. QAA Status/Command Byte Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3. QAA J1 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4. QAA J2 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5. QAA G02 Analog Position Input Circuit Plug-in Resistor Selection. . . . . . . . . . . . . . 3-6. QAA Half-Speed Clock On and Off Time Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7. QAA Card Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8. QAA LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3-9. QAA Potentiometers (Daughter Board). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10. QAA Test Points (Daughter Board) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11. QAC Output Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12. QAC G01 and G02 Contact Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13. QAC G03 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14. QAC G04 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15. QAC G05 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16. QAC G06 Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17. QAH Conversion Scan Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18. QAH Bipolar Conversion Dataword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19. QAH Unipolar Conversion Dataword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20. QAH Option Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21. QAI Analog Input Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22. QAM Current Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23. QAM J2 Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24. QAM Output Demand Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25. QAM J3 Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26. QAM DIOB Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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. 3-89. 3-92. 3-92. 3-93. 3-96. 3-96. 3-97. 3-97 .. 3-993-115

3-1153-1343-1353-136-138-1403-1613-1633-1643-1743-1763-1783-1793-180-181

3-182-182

3-183. 3-1833-1853-1903-191-1943-1-1953-3-1963-2053-205

-206

3-27. QAM Analog Values versus Hex Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28. QAM Manual Mode Demand Operations (G03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29. QAM Manual Mode Demand Operations (G01, 2, 4, 5, 6) . . . . . . . . . . . . . . . . . . . . 3-30. QAM Watchdog Timer Switch Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31. QAM RL Selected or Demand Linear Clock Frequency . . . . . . . . . . . . . . . . . . . . . . 3-32. QAM RE Selection of Demand Exponential Clock Frequency Sweep Rates . . . . . . 3-33. QAM RS Selection of Setpoint Linear Clock Frequency. . . . . . . . . . . . . . . . . . . . . . 3-34. QAM Jumper Selection of Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35. QAM Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-98 3-36. QAM Potentiometer Adjustments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37. QAO Card Reset Switch Position (Update Period) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38. QAO Analog Output Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39. QAV Card Output Data Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40. QAV Card Jumpers, Locations and Functions (Level 6 and earlier) . . . . . . . . . . . . . 3-41. QAV Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42. QAV Thermocouple Coefficient Definitions (WDPF System) . . . . . . . . . . . . . . . . . 3 3-43. QAV Thermocouple Coefficient Definitions (Ovation System) . . . . . . . . . . . . . . . . 3 3-44. QAW Card Output Data Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45. QAW Card Jumpers and Functions (Level 7 and earlier). . . . . . . . . . . . . . . . . . . . . . 3-46. QAW Jumper Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47. QAX Card Groups and Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-48. QAX Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49. QAX Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50. QAX Address Offsets (WDPF Systems) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51. QAX Address Offsets (Ovation System) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52. QAX Thermocouple Coefficient Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-53. QAX Low-Level Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54. QAX Low-Level Inputs with Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-55. QAX High Level Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56. QAX Data Pattern Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57. QAX Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-58. QAXD Card Groups and Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59. QAXD Counter Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-60. QAXT Power Supply Voltages (from QAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-61. QAXT Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 3-62. QAX/QAXT Based Thermocouple Compensation Kit Group Usage . . . . . . . . . . . . 3 3-63. QAXT Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 3-64. QAXT Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-65. QBE Power Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66. QBE Internal Power Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67. QBE +5 VDC to +11 VDC Level Shift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

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-206. 3-209. 3-2113-2123-2143-2153-2173-230

3-2313-2323-2383-2393-249

. 3-250. 3-2503-2573-2603-263-2623-2663-2683-3-273-2803-292

3-2933-294

3-299

3-3023-3033-303-307

. 3-3

. 3-33-3483-3493-3573-363

. 3-363

3-68. QBE +11 VDC to +5 VDC Level Shift Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3-69. QBE J1 Connector Pin Assignments and Signal Names . . . . . . . . . . . . . . . . . . . . . 3-70. QBE J2 and J3 Connector Pin Assignments and Signal Names. . . . . . . . . . . . . . . . 3-71. QBI QID Card Equivalents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-72. QBI Card Group Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73. QBI Card Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-74. QBI Card Front-Edge Connector Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75. QBO Digital Output Contact Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-76. QBO Card Reset Switch Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77. QBO DIP Switch Positions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78. QCA DIOB Card Edge Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-79. QCA Field Front Card Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-80. QCA Plug-in Scaling Resistor Reference Designators. . . . . . . . . . . . . . . . . . . . . . . . 3-81. Reference Designators for QCA Jumpers - Groups 1 and 2. . . . . . . . . . . . . . . . . . . 3-82. QCA Test Point Reference Designators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83. QCI Contact Wetting Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-84. Cable Length Limits for QCI Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-85. QCI Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 3-86. QCI G02 DIP Switch Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87. QDI-QID Card Equivalents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88. QDI Input Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-89. QDI Pin Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 3-90. Cable Length for QDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3-91. QDT Card Controls and Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-92. QIC DIOB1 Card Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-93. QIC DIOB2 for WDPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-94. QIC DIOB2 (P4) for WIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-95. QID Card Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-96. QID Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-300 3-97. QID Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-301 3-98. QID Differential Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-99. QID Single-Ended Input Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-100. QID G10 Input Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3-101. QID Allowable Cable Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102. Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3-103. Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3-104. LIM Power Card-Edge Terminal Block Connector . . . . . . . . . . . . . . . . . . . . . . . . . . 3-105. LIM Serial Port Card-Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-106. SLIM Serial Port Card-Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-107. QMT J5 (Power Monitor Relay) Pin Connections and Signal Names . . . . . . . . . . . . 3-108. QMT Card Fuse Ratings and Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3-3763-

. 3-3803-406

. 3-4173-417. 3-4263-4303-4333-434

3-4343-4413-442

. 3-4553-469. 3-43-473

. 3-4743-476

3-4783-4793-4803-4883-490

. 3-4913-493

. 33-4963-4973-4993-518

3-5193-5203-522

. 3-523. 3-531. 3-531 . 3-533 . 3-533 . 3-534

3-109. QPA Field Signal (J3) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-110. Field Signal Times (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 3-111. QPA Clock Select Jumper Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-112. QRF DIOB Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-113. Field Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-406 3-114. QRO Card Reset Switch Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-115. QRO Digital Output Contact Allocations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-116. QRT Card Conversion Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-117. Normal Mode Voltage Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-118. QRT Front Edge Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-119. Front Edge Pairs for QRT Card Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-120. QRT Card RTD Bridge Modules (7380A92) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-121. Bridge, Count, and Output Values (Example A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-122. Bridge, Count, and Output Values (Example B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-123. QSC Input Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-124. QSD Front-Edge M/A Station and Field Connector. . . . . . . . . . . . . . . . . . . . . . . . . . 3-125. QSD Card Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3-126. QSD Watchdog Timeout Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-127. QSD Clock Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-128. QSD Analog Output Stage Plug-in Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-129. LVDT Calibration resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-130. QSD Direct Output Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-131. QSD P + I Controller Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-132. Maximum Cable Lengths (Assume RC = 0) for QSE Card . . . . . . . . . . . . . . . . . . . 3-133. QSE J1 Connector DIOB Pin Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-134. QSE J2 Connector Pin Out for Address Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-135. QSE J2 Connector Pin Out for Field Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-136. QSE Current Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -495 3-137. QSE Status Word Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-138. QSE Status Word Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-139. QSE Point ID Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-140. QSR DIOB Card Edge Connector Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-141. Groups 1 and 3 (DC LVDT) Field/Addressing Front Card Edge Connector . . . . . . . 3-142. Groups 2 and 4 (AC LVDT) Field/Addressing Front Card Edge Connector . . . . . . 3-143. QSR DIOB Address Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-144. QSR Read Register Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-145. Plug in Resistor Reference Designators (Groups 1 and 3) . . . . . . . . . . . . . . . . . . . . 3-146. Plug in Resistor Reference Designators (Groups 2 and 4) . . . . . . . . . . . . . . . . . . . . 3-147. Channel Jumper Reference Designators (Groups 1 and 3). . . . . . . . . . . . . . . . . . . . 3-148. Channel Jumper Reference Designators (Groups 2 and 4). . . . . . . . . . . . . . . . . . . . 3-149. Channel Test Point Reference Designators (Groups 1 and 3) . . . . . . . . . . . . . . . . .

M0-0053 xvi 5/99

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Table of Contents, Cont’dList of Tables

Table Title Page

. 3-534. 3-546

3-5703-5703-5743-575

3-5753-53-5763-5763-33-577

. 3-581

. . B-3

. . C-5

3-150. Channel Test Point Reference Designators (Groups 2 and 4) . . . . . . . . . . . . . . . . . 3-151. QSS Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-152. QSS Field Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-548 3-153. QTO Card Reset Switch Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-154. QTO Digital Output Contact Allocations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-155. LVDT Coil Drive Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-156. LVDT Secondary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-157. QVP Valve Coil Drive Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-158. QVP Setpoint Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 3-159. QVP Valve Position Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-160. QVP Current Loop Input (Groups 3 and 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-161. QVP Digital Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .577 3-162. QVP Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-577 3-163. QVP Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-164. QVP Testjacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-579 3-165. QVP LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-581 3-166. QVP Option Select Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B. Setting Q-Card Addresses

B-1. Conversion of Hexadecimal Number to Jumper Address. . . . . . . . . . . . . . . . . . . . . .

Appendix C. Card-Edge Field Termination

C-1. Card-Edge Terminal Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5/99 xvii M0-0053

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Table of Contents, Cont’dList of Tables

Table Title Page

M0-0053 xviii 5/99

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ow

,

Summary of Changes

This revision of “Q-Line Installation Manual” (M0-0053) includes the followingchanges:

• QRF wiring diagram was changed to clarify A and B halfshells.

• QBI termination numbers were changed.

• QAX drawing number was changed.

• QPA clock rate was changed.

• QAW input value was changed

• QAI, QAV, and QAX conversion values were added.

• QLI-5 digital input ranges were changed.

• There were notes added to QLI-5 and QLI-8.

• QLI-7 wiring diagram was changed.

• QAO, QID, and QRT had additions and changes made.

• Appropriate information was added to describe the Q-Line cards which are nCE Mark compliant.

All sections may include additional miscellaneous reorganization, correctionsclarifications, and additions.

5/99 Changes-1 M0-0053Westinghouse Proprietary Class 2C

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hy

theof

tionand, and

all

Section 1. Introduction

1-1. Overview

The WDPF system consists of individual processing units (called drops) whiccommunicate over networks (called highways). These drops are connected bcoaxial cable or fiber optic cable to the WDPF Data Highway.

Installation of a WDPF system includes planning, followed by the installation ofData Highway, the individual drops, and I/O. This manual describes installationQ-Line I/O, including field wiring and card addressing.

Note

Prior to beginning the I/O installationprocedures described in this volume, earlierphases of WDPF installation must becompleted. Refer to the applicabledocuments for details (seeFigure 1-1).

AsFigure1-1 indicates, this manual is one of several which describe the installaof a WDPF system. In combination, these manuals detail the considerations decisions that face the user before the equipment arrives at the permanent sitedescribe installation procedures from receipt of the equipment to power-up ofdrops and peripheral devices.

5/99 1-1 M0-0053Westinghouse Proprietary Class 2C

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1-1. Overview

Figure 1-1. Phases of WDPF Installation

Phase 1Plan

SystemLayout

Phase 2Prepare

Site

Phase 3AInstallData

Highway

Phase 3BInstallField

Wiring

Phase 4Receive/

InstallDrops

Phase 5Start-upHighway

Phase 1 . Plan system layout as described in“Data Highway Installation Manual” (M0-0051)or “ Planning and Highway Installation Manual(WEStation)”(M0-8000).

Phase 2 . Prepare site as described in“ Data Highway Installation Manual” (M0-0051)or “Highway Installation Manual (WEStation)”(M0-8000).

Phase 3A . Install Data Highway as described in“ Data Highway Installation Manual” (M0-0051)or “Installation Manual (WEStation) ”(M0-8000).

Phase 3B . Install field wiring as described in thismanual (M0-0053)ORin “Remote Q-Line Installation Manual”(M0-0054)ORin “Distributed I/O Installation Manual”(NLAM-B204) and associated instructionleaflets.

Phase 4 . Receive and install drops described in“Drop Installation Manual” (M0-0052) or “DropInstallation Manual (WEStation)” (M0-8005).

Phase 5 . Start-up highway as described in“ Data Highway Installation Manual” (M0-0051)or “ Installation Manual (WEStation)”(M0-8000).

M0-0053 1-2 5/99Westinghouse Proprietary Class 2C

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1-2. Contents of this Document

nd

ng

the

1-2. Contents of this Document

The contents of this document are described below:

Section 1. Introduction describes the WDPF system installation documents, athe contents and scope of this document.

Section 2. Field Wiring Procedures provides general information onrecommended field wiring techniques, including termination and noiseminimization.

Section 3. Q-Card Reference Sheets describes the available Q-Cards, includingtermination information.

Appendix A. Worksheetsshows sample worksheets used to determine the wiriand addresses of the WDPF system.

Appendix B. Setting Q-Card Addressesshows how to set card addresses on aWDPF system. A hexadecimal to binary table is included

Appendix C. Card-Edge Field Termination shows an alternate method of wiringa WDPF system.

Table 1-1 lists the Q-Cards that are described in this manual. Cards that aredescribed in detail in other manuals are indicated by an asterisk (*) in front ofcard name and the number of the manual after the card name

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1-2. Contents of this Document

ck)

rd)

Table 1-1. Available Q-Cards

Q-Card Q-Card

QAA (Actuator Auto/Manual Card) * QLC (Serial Link Controller)(see also U0-1100)

QAC (Analog Conditioning Card) QLI (Loop Interface Card)

QAH (High-Speed Analog Input Point Card) QLJ (Loop Interface Card with output readba

QAI (Analog Input Card) LIM (Loop Interface Module)

QAM (Auto/Manual Station Controller Card) SLIM (Small Loop Interface Module)

QAO (Analog Output Card) QMT (M-Bus Terminator Card)

QAV (Analog Input Point Card) QPA (Pulse Accumulator Card)

QAW (Analog High-Level Input Point Card) * QRC (Remote Q-Line)(see also M0-0054)

QAX (Analog Input Point Card) QRF (Four Wire RTD Input Card)

QAXD (QAX Digital Daughter Board) QRO (Relay Output Card)

QAXT (Temperature Compensation) QRS (Redundant Station Interface Card)

QBE (Bus Extender Card) QRT (RTD Input Amplifier Card)

QBI (Digital Input Card) QSC (Speed Channel Card)

QBO (Digital Output Card) QSD (Servo Driver)

QCA (Current Amplifier Card) QSE (Sequence of Events Recorder Card)

QCI (Contact Input Card) QSR (Servo Driver with Position Readback Ca

* QDC (Digital Controller)(see also U0-1105)

QSS (Speed Sensor Card)

QDI (Digital Input Card) * QST (Smart Transmitter Interface)(see alsoU0-1115)

QDT (Diagnostic Test Card) QTB (Time Base Card)

* QFR (Fiber-Optic Repeater)(see also M0-0054)

QTO (TRIAC Output Card)

QIC (Q-Line DIOB Monitor) QVP (Servo Valve Position Controller Card)

QID (Digital Input)

* indicates this card is not fully described in this manual.

M0-0053 1-4 5/99Westinghouse Proprietary Class 2C

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1-3. Reference Documents

1-3. Reference Documents

In addition to this manual, which describes installation of Q-Line I/O,Table 1-2lists documents and pertinent standards which may be helpful:.

Table 1-2. Reference Documents

DocumentNumber

Document Nameor Source

IEEE Standard No. 81-1962 Recommended Guide for Measuring GroundResistance and Potential Gradients in the Earth

IEEE Standard No. 118-1978 IEEE Standard Test Code for ResistanceMeasurement

IEEE Standard No. 518 IEEE Service Center445 Hoes LanePiscataway, NJ 08854

M0-0051 Data Highway Installation Manual(Standard and PCH)

M0-0052 Drop Installation Manual (Standard and PCH)

M0-0054 Remote Q-Line Installation Manual

M0-8000 Highway Installation Manual(WEStation Equipped)

M0-8005 Drop Installation Manual (WEStation Equipped)

National Electric Code National Fire Protection Association470 Atlantic AvenueBoston, MA 02210

NLAM- B204 Distributed I/O Installation Manual

Power Line Disturbances and Their Effecton Computer Design and Performance byDuell, Arthur W. and W. Vincent Roland

Hewlett-Packard Journal, August 1981

U0-0106 Standard Control Algorithm User’s Guide

U0-0131 Record Type User’s Guide

U0-0135 DPU Introduction and Configurations

U0-1100 QLC User’s Guide

U0-1105 QDC User’s Guide

U0-1115 Smart Transmitter Interface User’s Guide

5/99 1-5 M0-0053Westinghouse Proprietary Class 2C

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1-3. Reference Documents

Additional publications may be obtained by writing the following professionalsocieties, and requesting their lists of available publications:

• Electronic Industries AssociationEngineering Department20011 Street NWWashington, DC 20006

• Instrument Society of America67 Alexander DriveP.O. Box 12277Research Triangle Park, NC 27709

• Scientific Apparatus Makers AssociationProcess Measurement & Control Section1101 16th Street NWWashington, DC 20036

M0-0053 1-6 5/99Westinghouse Proprietary Class 2C

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tionres.

eldction

Section 2. Field Wiring Procedures

2-1. Section Overview

This section describes WDPF field wiring, defines both the field signal terminaand noise minimization techniques, and provides specific field wiring proceduAdditional information on each Q-card can be found inSection 3.

This information is designed to enable installation personnel to easily make fisignal connections between the user’s process and the WDPF System. This seassumes that the user is familiar with the procedures given in“Data HighwayInstallation Manual (M0-0051) and“Highway Installation Manual (WEStation)”(M0-8000).

This section includes the following:

• WDPF Field Wiring (Section 2-2).

• System Reference Documents (Section 2-3).

• Noise Minimization Techniques (Section 2-4).

• Thermocouple Considerations (Section 2-5).

• Common Input Considerations (Section 2-6).

• Field Termination Types (Section 2-7).

• “B” Cabinet Field Terminations and Addressing (Section 2-8).

• Q-Card Hardware Address Selection (Section 2-9).

• Using Address Selection Jumpers (Section 2-10).

• Pre-Wiring Consideration (Section 2-11).

• Field Wiring Half-Shell and Card-Edge Terminations (Section 2-12).

• Environmental Specifications (Section 2-13).

• Power Consumption (Section 2-14).

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2-2. WDPF Field Wiring

ichss

seiring

tion

2-2. WDPF Field Wiring

In WDPF System applications, field signal connections are made to drops whinterface directly to the process. Typically, the process I/O interface and procepoint cards are contained in the Distributed Processing Unit (DPU).

Field-signal wiring within WDPF Systems involves connecting user-supplied,pre-installed field cables/wires to the respective drops’ field terminations. Thedrops are pre-assembled at the factory, and all internal field signal cable and wconnections up to the field termination points are already in place.

To field-wire a WDPF System, two areas should be considered: noise minimizatechniques and the drop field terminations.

Noise minimization is discussed inSection 2-4.

Section 2-5 throughSection 2-12 present procedures for drop field wiringterminations.

M0-0053 2-2 5/99Westinghouse Proprietary Class 2C

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2-3. System Reference Documents

sing

stem

dty ofpport

e and

rd,ns,

et.n’s

2-3. System Reference Documents

Each system’s specific field signal requirements determine the mix of Q-cardwithin the drop, the field wiring connections, and the types of cabling and/or wirto be used.

Westinghouse provides the following task-related documentation to support syinstallation and maintenance:

• Q-card descriptions

• Typical Q-Line or process I/O termination schematics

• External cabling lists

• Field signal termination lists

• Half-shell termination drawings

The “Field Signal Termination Lists” are used by installation personnel for fielwiring purposes. The lists are computer-generated and are compiled in a varieforms, column heads, and sorts to meet the specific user requirements, to sumaintenance and to support installation. The two primary types are thesort-by-point and the sort-by-hardware lists.

The sort-by-point (or signal) type of list supports post-installation maintenancactivities, where easy point or signal identification is needed to aid diagnostictroubleshooting procedures.

The sort-by-hardware type of list is organized for easy identification of signal, cacabinet, and field termination point (half-shell or card-edge connector) locationeeded for field wiring.

An example of the sort-by-hardware list and its format is shown inFigure2-1. Thislist illustrates the required wiring for a DPU, which utilizes a termination cabinThis list is produced from the process I/O lists developed during the installatioplanning phase (see“Data Highway Installation Manual” (M0-0051) and“Highway Installation Manual (WEStation)” (M0-8000)).

5/99 2-3 M0-0053Westinghouse Proprietary Class 2C

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2-3. System Reference Documents

ags,ion

ed

lific

From this list, the user can find the point name, signal description, and signal tas specified by a process I/O list. This list also contains the following installatinformation provided by Westinghouse:

• Q-card Address-- This field is the specific card address (in hexadecimal) usby the process I/O bus (DIOB) for data communications; it enables systemaddressing of a specific card.

• Point Number -- This field is the number which identifies the specific signaand input or output circuits of each Q-card. This can be used to identify speccircuits on the card schematics, card termination schematics, or exampleprocess field wiring diagrams.

Figure 2-1. Example Sort-by-Hardware Terminations List

User defined signal point name

User defined signal description

User defined signal tag

Card address

I/O signal point number

System cabinet number

Half-shell zone location

Ground connection point

Terminal strip connection points

CA Z S

AD P C O H G P C

POINT RD N A N H N O O

NAME DESCRIPTION TAG DR I B E L D S M

HMF506 REACTOR CORE INLET WATER TEMP ABCD1234 20 0 35 A 3 A 2 B 2

HMF512 REACTOR CORE OUTLT WATER TEMP ABCD1235 20 1 35 A 3 A 3 B 3

HMF518 REACTOR CORE STEAM TEMP ABCD1236 20 2 35 A 3 A 4 B 4

BMF506 FEEDWATER INLET TEMP FGHI4567 20 3 35 A 3 A 5 B 5

BMF512 FEEDWATER OUTLET TEMP FGHI4568 20 4 35 A 3 A 6 B 6

BMF518 FEEDWATER PRESS AT DISCHRGE FGHI4569 20 5 35 A 3 A 7 B 7

GQF506 RETURN STEAM TEMPERATURE QWER2222 20 6 35 A 3 A 8 B 8

GQF512 STACK GAS FLOW RATE QWER3333 20 7 35 A 3 A 9 B 2

GQF518 IONS PER SQUARE METER QWER4444 20 8 35 A 3 A10 B10

ZRF506 GALLONS OF WATER, FEEDWATER ASDF5555 20 9 35 A 3 A11 B11

ZRF512 COOLANT FLOW, PRESSURE ASDF6666 20 10 35 A 3 A12 B12

ZRF518 DISCHARGE TANK OVERFLOW ALRM ASDF7777 20 11 35 A 3 A13 B13

M0-0053 2-4 5/99Westinghouse Proprietary Class 2C

Page 30: Ovation Q Line

2-3. System Reference Documents

e

(in

sed

• Cabinet Number -- This field identifies the specific termination cabinet withinthe system, at which the signal is to be terminated.

• Half-Shell Zone Location -- This field identifies the specific half-shell withinthe termination cabinet, at which the signal is to be terminated.

Note

For card-edge termination applications, thisis the Q-crate/slot location.

• Ground Connection -- This field identifies the specific point within thetermination cabinet where signal grounds are connected (as defined by thcustomer).

• Terminal Strip Connection Points -- This field identifies the specifichalf-shell terminal points where the field signal connections are to be madethis example, positive and common).

Figure2-2 gives some of the various termination list formats and column heads ufor installation purposes.

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2-3. System Reference Documents

Figure 2-2. Termination List Formats

Terminations Cabinet Without Signal Conditioning

POINTNAME DESCRIPTION TAG DR T R B L D S G M N

SIGNALCOND

RD N O A L N O E O TAD I S C E G P N C RCA O N H

P E SS H

EPYT

ENOZ

Terminations Cabinet Without Signal Conditioning

POINTNAME DESCRIPTION TAG DR T B L D S M

RD N A L N O OAD I C E G P CCA O H

P SH

ENOZ

Card-Edge Terminations With Signal Conditioning

POINTNAME DESCRIPTION TAG DR T R B T D S G M

SIGNALCOND

RD N O A O N O E OAD I S C L G P N CCA O N S

P ES

EPYT

Cable Terminations With Signal Conditioning

POINTNAME DESCRIPTION TAG DR T R B D S G M

SIGNALCOND

RD N O A N O E OAD I S C G P N CCA O N

P ES

EPYT

NNOC

ETARC

Q

Card-Edge Terminations Without Signal Conditioning

POINTNAME DESCRIPTION TAG DR T R B T D S M

RD N O A O N O OAD I S C L G P CCA O N S

P ES

EPYT

ETARC

Q

Cable Terminations Without Signal Conditioning

POINTNAME DESCRIPTION TAG DR T B D S M

RD N A N O OAD I C G P CCA O

P

NNOC

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2-4. Noise Minimization Techniques

seitive

dr

esult

that

rorsg

ated toee

ired

2-4. Noise Minimization Techniques

2-4.1. Background

A wide variety of analog and/or digital circuits are associated with the WDPFSystem’s installation. There are low-level voltage circuits, high-level voltagecircuits, circuits that transfer information, and circuits that transfer power. Thecircuits are placed into two categories: noise-producing circuits and noise-senscircuits.

Noise problems typically occur when transmitting analog (voltage, current, another measured values) or digital information (on/off conditions, pulse trains osimilar data) via inter-connected or wired circuits. The information carried bysignals in such circuits may become distorted during transfer and errors may rfrom this distortion.

The difference between the signal of transmitted information and the signal ofinformation as received is called noise (seeFigure 2-3 andFigure 2-4). The noiseminimization techniques briefly described in this section focus on preventing erby either eliminating the noise, or when elimination is not possible, performinsteps to lessen its impact.

2-4.2. Noise Discrimination

Natural signal properties (such as the peaks of a digital signal) or conditions creduring signal transmission (such as the voltage of the analog signal) are usedmake the desired information in the signal appear different from the noise. Threcovery of correct information from a noisy signal therefore depends upon thability to subtract the noise from the desired information.

There are three components of a signal that can be used to separate the desinformation from a noisy signal:

• Energy Level

• Frequency

• Source (of both Signal and Noise)

The following pages explain how each of these components can be applied tominimize errors that may occur because of a noisy signal.

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2-4. Noise Minimization Techniques

re isjected

he

Energy Level

The energy level is the total energy for the signal plus any induced noise. If thea significant difference between the signal and the noise, then the noise is reeasily by thresholding techniques (as identified as Desirable inFigure 2-3).

If there is not a significant difference between the signal and the noise, then tnoise is not easily rejected (as identified as Undesirable inFigure 2-3).

Figure 2-3. Amplitude Discrimination Example

IdealSignal

IdealSignal

SevereNoise

Imposed

Signalplus

Noise

Undesirable

The noise and signal have insufficientamplitude contrast to permit simplethreshold discrimination.

Desirable

Threshold discrimination is possible becauseof sufficient contrast between noise andsignal amplitude.

1 threshold

0 threshold

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2-4. Noise Minimization Techniques

the

thed

sinceow

Frequency

Most of the noise commonly encountered in industrial plants is related either topower line frequency and its low harmonics, or toswitching transients. Theanalog signals are usually lower in frequency than one cycle per second, whiledigital signals between plant and controller appear from zero to a few hundrecycles per second.

Both analog and digital signals can be discriminated easily by eliminatingfrequency content from external noise sources such as switching transients, the transients do not contain appreciable energy below 0.5 MHz frequency. Lpass filtering is useful in recovering analog signals from either power line ortransient noise, and for recovering digital signals from transient noise.Figure 2-4shows an example of these two types of noise.

Figure 2-4. Typical Noisy Signal

mV

60

50

40

30

20

10

0

-10

Power LineFrequency Noise

0 Volt Reference

Desired Signal

TransientNoise

The signal above is shown at a 30mV level with both14 mV RMS (60 Hz) and transient noise.

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2-4. Noise Minimization Techniques

k ofsseem to

is

efer

.

on

Sources (Signal and Noise)

When signals are originally generated, most are relatively noise-free. The bulthe noise present on a received signal has been added to the signal during ittransmission. Isolation and segregation of signal sources and wiring from noisources is highly effective as a recovery means. This technique, as well as thlow-pass filtering previously mentioned, serves to reduce the recovery probleone of amplitude or energy level discrimination.

2-4.3. Noise Sources

The following devices and circuits are common sources of noise:

• Inductive devices, such as relays and solenoids

• AC and DC power circuits, and wiring

• Switchgear

• Fast-rise-time sources: thyristors and certain solid-state switching circuits

• Variable-frequency or variable current devices

2-4.4. Noise Classes

Signal and power circuits, wiring, and cables are classified as high-level orlow-level sources of noise and interference. A definition of each class of noisegiven inTable 2-1.

For details on the selection and spacing of field wiring with respect to noise, rto “Data Highway Installation Manual” (M0-0051) or“Highway InstallationManual (WEStation)” (M0-8000).

Table 2-1. Noise Class Definitions

Noise Class Level Definition

H High Includes all AC power circuits from household 115 VAC up toKV transmission levels. It includes all DC power circuits from250 VDC and 15 A or less up to 500 VDC and 200 A or more

M Medium Includes Contact Closure Input (CCI) and Contact ClosureOutput (CCO) signals. It also includes telephone and televisicircuits, and conventional (relay) logic circuits.

L Low Includes digital signals, data links, and low-speedpulse-counting circuits.

Q Very Low Includes analog inputs as well as pulse inputs to high-speedcounting and memory circuits.

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2-4. Noise Minimization Techniques

l

and

rund

ir.

les,ireslds.

iverencyls on at

2-4.5. Digital Signal Noise Rejection

The WDPF System employs three specific noise rejection measures for digitasignal plant interconnections:

• Low pass filtering (2 to 16 msec time constant)

• Substantial signal levels (48 VDC or 115 VAC)

• Isolation, or optical coupling

Low pass filtering and the use of large signal level techniques provide frequencyenergy level discrimination, respectively.

Isolation of the digital signal receiver from ground is important as a means forejecting noise which causes both wires in a signal pair to change voltage-to-gropotentials. An example of this type of isolation is a signal source (transmitter)which is grounded at a point remote from the receiver, where transmitter andreceiver grounds are not at the same voltage. In this case, ground potentialdifference appears as a voltage on both wires of the corresponding signal pa

Another example in which isolation may be required to reject ground potentiadifference noise would be in circuits where coupling exists between signal wirinducing a potential in both wires. Induced potentials can occur when signal ware present in environments with changing electromagnetic or electrostatic fieIsolation may be required in this case.

An optical isolator may be used to bring digital signals into the receiver. No receresponse to noise can occur unless signal line noise current flows. Low frequcurrent, which may flow as a result of equal noise voltage-to-ground potentiaboth wires of the signal pair, is eliminated if the signal wires are not groundedmore than one point. This is called the common-mode voltage.

Note

High frequency noise currents can flow usingstray capacitance as part of their path. Thisrequires the use of low pass filtering inaddition to the optical isolation.

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2-4. Noise Minimization Techniques

r

r anise,when this

ents.

l or

e rise the

y areoise

romible to

2-4.6. Analog Signal Noise Rejection

Analog signal isolation is provided for the same reasons that are discussed fodigital signals (as described inSection 2-4.5). However, since analog signals aretypically low level, filtering and isolation noise rejection techniques are morecritical for analog signals than for digital signals.

Analog signal filtering is achieved by averaging applied signals for one cycle (ointeger multiple of cycles) of the AC power line frequency. Power line related noat the power line frequency and its harmonics, has exactly zero average valuethe average is taken over exactly one cycle and is filtered out of the signal bytechnique.

Transient noise (high frequency damped ringing) has zero average value foraverages taken over time periods much longer than the duration of the transi

2-4.7. Output Signal Noise Rejection

Digital output signals from the WDPF System to the plant are electromechanicasemiconductor outputs which are entirely isolated from ground. Resistor andcapacitor circuits are placed across these contacts to control the rate of voltagupon turn-off. The only additional signal treatment needed is that required bydriven plant equipment itself.

Interconnections between various WDPF subsystems (printers, etc.) generalltreated by filtering, isolation, large signal level, and other appropriate forms of nsuppression. Such signal conditioning is built into the equipment.

2-4.8. Noise-Sensitive Circuit Noise Rejection

All transmitting, low-level analog and digital circuits must be assumed to benoise-sensitive and to require special protection against noise. Field signals fprocess transducers (thermocouples, RTDs, and so on) are especially susceptnoise. Noise can be coupled into these sensitive circuits in three ways:

• Electrostatic coupling via distributed capacitances

• Electromagnetic coupling via distributed inductances

• Conductive coupling, such as circuits sharing a common return

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2-4. Noise Minimization Techniques

e

tude

are

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estanceincht is

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hee theuousre

Noise suppression for these noise sensitive circuits involves one or more of thfollowing basic measures:

• Physical separation between noise-producing and noise-sensitive circuits

• Twisted-pair wiring for signal connection within plant

• Proper grounding, especially avoiding multiple grounding of cable shields

• Proper shielding, especially cable shielding

• Surge protection

Circuit Separation

Circuit separation is a simple and effective means of electrostatic andelectromagnetic field induced noise control. This is because electrostatic andelectromagnetic fields decay with increasing distance, producing lower amplinoise and maintaining a good signal-to-noise ratio.

Twisted-pair Wiring

Twisted-pair wiring suppresses noise by acting to eliminate circuit loops whichsensitive to stray electromagnetic fields. For this reason, Westinghouserecommends that all analog signal circuit connections should be made with twipairs wire. Digital signal connections should carry a group return (or commonwired in the same cable as the signal wires.

Twisted pairs are also recommended in digital circuits where unusually noisyenvironments exist. Twisting of the signal wire and its return conductor becomincreasingly important as the length of the two becomes greater, and as the disfrom noise sources becomes less. In twisted pairs or small cables (less than 1/2outer conductor circle diameter), a twist rate of at least one to two twists per foorecommended.

Proper Grounding and Shielding

Proper grounding along withShieldingcauses noise-induced currents to flow in thshield, and from the shield to ground, rather than in the corresponding signalconductors. Shielding itself is useful in avoiding capacitively coupled noise. Tshield’s sole function is to decrease effective capacitance from conductors insidshield to conductors outside. To accomplish this, the shield should be as continas possible (foil or metallized plastic) and equipped with a “drain wire” for secusingle-point grounding.

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2-4. Noise Minimization Techniques

ndield.ctive,

ost

e the

Conductors and corresponding returns may be grouped within a shield only ifcapacitive coupling between them is acceptable. Avoid the grouping of low- ahigh-level analog inputs, contact inputs, and contact outputs within a single shShields are used as current-carrying conductors on some systems. To be effeshields are grounded at the same point as the signals within.

lEEE Surge Protection

Surge protection to IEEE 472-1974 (Ref. ANSI C37.902-1974) is provided on mQ-Line cards. Check individual card descriptions (Section 3) for availability orpossible additional conditions. To ensure this feature works correctly, make surgrounding screw on the card is clean and tight.

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2-4. Noise Minimization Techniques

idered betedield

rce.

ieldt the

for

2-4.9. Analog Signal Shielding Techniques

For noise suppression purposes, analog signals of less than one volt are conslow-level and require shielding. Individually twisted and shielded pairs shouldused for all analog input signal wiring. Multipair cable can be used if each twispair in the cable has its own insulated shield. Use the following guidelines to shsignals:

• Ground the low-level analog signal shield.

• Ground the shield only once, preferably to a single point at the signal sou

• Connect the low side of the signal to the shield at the signal source. If the shcannot be conveniently grounded at or near the signal source, ground it aDPU. An ideal analog signal field connection is shown inFigure 2-5.

• Run the shield (unbroken) from the transducer to the guard terminal of theAnalog to Digital (A/D) front-end at the Analog Input card. Maintain shieldcontinuity at junction boxes when they are used.

Figure2-6 shows the typical thermocouple analog signal wiring recommendedthe WDPF user.

Figure 2-7 shows the recommended sensor analog signal wiring.

Figure 2-5. Ideal Analog Signal Field Connection

A/D

A/D Guard

Twisted Pair

UnbrokenCable Shield

Drain Wire

Single PointGround

ES

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2-4. Noise Minimization Techniques

Figure 2-6. Typical Thermocouple Analog Signal Wiring by User

Thermocouples

Field Grounded

Field Grounded

Field Grounded

in Well

Near Well

at LocalJunction Box

Not Groundedin Field

Preferred

Wiring for ungrounded

Preferred

Preferred

Preferred

Alternate

Alternate

thermocouple isinstalled by user.

Local JunctionBox (when used)

ConnectionHeadHalf Shell

Ground

Cable Drain

Note:Typical Cold Junction Box

Terminal Strip (or Half Shell) Shown

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

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2-4. Noise Minimization Techniques

Figure 2-7. Typical Sensor Analog Signal Wiring by User

Voltage Sensors

Field Groundedat or Near Sensor

Field Groundedat Local Junction Box

Not Groundedin Field

Preferred

(+)

Cable Drain

Preferred

Alternate

Preferred

Alternate

(-)Guard

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

(+)(-)Guard

Local JunctionBox (when used)

Half ShellGround

Note:Typical Cold Junction Box

Terminal Strip (or Half Shell) Shown.

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2-5. Thermocouple Considerations

ction

onicdule

.

2-5. Thermocouple ConsiderationsCurrently, there are three methods of compensating thermocouples for cold junreference temperature. They are listed below in order of preference:

• Half-Shell compensation (QAX, QAXT cards)

• Cabinet compensation (QRT card)

• On-board compensation (QAV card)

2-5.1. Half-Shell Compensation

The QAX card has 12 available channels. One channel is connected to an electrtemperature sensing module which is mounted at the B-cabinet half-shell. This moprovides the capability for compensating the other 11 channels on the QAX card

As shown inFigure 2-8, a steel cover is placed over the QAX half-shells. Thisisolates the terminal blocks from the rest of the cabinet and equalizes thetemperature. To provide compensation, the QAXT is mounted as indicated.

Figure 2-8. QAXT Half-Shell Mounting

2019181716151413121110987654321

QAXT

Half-Shell

Ground Bar

Protective Cover

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2-5. Thermocouple Considerations

) tont) of

s areIOB.uple

tems

d

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r

Benefits of this method include;

• No baffles or fans are needed within the termination cabinet.

• Minimal impact on compensation if cabinet door is opened.

• Preferred with Remote Q-Line I/O.

Refer to the QAX card section for additional information on this method ofcompensation.

2-5.2. B-Cabinet Compensation

This method uses cabinet mounted Resistance Temperature Detectors(RTDsdetermine an average temperature of an entire B-cabinet or a portion (segmethe cabinet. A maximum of two segments can be defined for each terminationcabinet, with two RTD temperatures in each segment. RTD cabinet temperaturefed into a QRT card at a specific address (F8 - FB), and then presented to the DThe system then averages the measurement and compensates the thermocovalues terminated within that segment of the cabinet.

Considerations with cabinet mounted RTDs include:

• Baffles and fans are used within the termination cabinet.

• QRT RTD input card and external circuitry are required.

• Compensation values are updated every 1/2 second. Compatible with sysequipped with “B” cabinets.

A twisted-three-conductor shielded cable is recommended for RTD signal fielconnections.

The preferred method to interface RTD signals is to use the QRT card, whichhave four isolated RTD bridges and A/D converters. An alternate method tointerface RTD signals in WDPF applications is to use an external bridge powesupply, externally mounted bridge, and a QAV card (low-level A/D converter).

Note

When using 10 ohm copper RTDs, the conversioncoefficients may need to be re-calibrated in the field.The lead resistance varies greatly with the size andlength of wire for this type of RTD.

Refer to the QRT card section for additional information on this method ofcompensation.

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2-5. Thermocouple Considerations

I/O.ards

venthauto-res

the

well.ablern

t

2-5.3. On-Board Compensation

This method can only be used with card-edge terminations and remote Q-Line(For most applications, QAXT compensation is preferred). In operation, on-bocompensation uses an on-card temperature sensor on a QAV card. QAV cardequipped with a thermocouple temperature compensation feature use the sechannel for the sensor. The channel is read every time the card performs an calibration cycle. This eliminates the need for external sensor cards and ensufield temperature accuracy.

• Compatible with card-edge terminations.

• Compensation values updated every 1/2 second.

• Usable with Remote I/O single crate enclosures or similar cabinets whereI/O cards and terminal blocks are housed within the same cabinet and thetemperatures within the entire cabinet are equalized.

Refer to the QAV card section for additional information on this method ofcompensation.

2-5.4. Thermocouple Grounding

Thermocouples used in WDPF applications should be grounded close to the For thermocouples that are in close proximity to a common ground, an overall cshield is sufficient. An example of this type of thermocouple or voltage sensowould be a boiler-tube metal-temperature thermocouple which uses a commomulti-conductor cable. In this case, jumpers would be added at the DPU inputerminals to tie all of the signal shield guard points to the cable shield.

Thermocouples which do not share a common ground should use individuallyshielded twisted pairs, with the shields grounded at the wells.

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2-6. Common Input Considerations

ntrolnded.

isy

PF

ble

2-6. Common Input Considerations

2-6.1. 4 to 20 mA Signal Considerations

When sufficient separation from noise sources exists, this standard class of cosignal does not require shielded cables. Use of twisted pair cables is recomme

2-6.2. Digital Signal Considerations

The WDPF System’s digital circuits used in data transmission do not requireindividual twisted or shielded pair conductors unless installed in unusually noenvironments. A multi-conductor cable, in which one conductor serves as acommon return and with a single overall cable shield, is sufficient for most WDdigital signal applications.

2-6.3. Contact Closure Signal Considerations

• Outputs (CCO) -- These circuits usually require no shielding.

• Inputs (CCI) -- These circuits require no shielding if the net current in the cais zero.

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2-7. Field Termination Types

ts).

es,

t,s are

hod

n.

2-7. Field Termination Types

The DPU drop utilizes one of two methods of field signal terminations:

• Cabinet termination

• Card-edge termination

Cabinet Termination

In cabinet termination the drop is packaged in dual cabinets (“A” and “B” cabine

Note

There are two types of A and B cabinets, theStandard and the Enhanced. With theEnhanced cabinets, there are more slots forQ-Cards, more half-shell zones, and moreterminals per half-shell zone.

One of these dual cabinets is called an “A” Cabinet, which houses the Q-cratMultibus crate, and related electronics.

The other cabinet of this dual-cabinet package is the terminations “B” Cabinewhich houses the terminal blocks for field signal connections. Q-Card addresseassigned using jumper wires on the card front-edge cable connector. Refer toSection 2-12 for more information on cabinet termination.

Card-edge Termination

In card-edge termination the drop is packaged in a single “A” Cabinet. This metuses field termination edge connectors at each Q-card for user field signalconnections. Refer toAppendix C for more information on card-edge terminatio

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2-8. “B” Cabinet Field Terminations and Addressing

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lock.

ses

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2-8. “B” Cabinet Field Terminations and Addressing

The Enhanced “B” Cabinet termination hardware consists of an eight-level arrabarrier-type terminal blocks. Six 20-point terminal blocks (called A-blocks) occueach level, giving a total of 48 (8 levels * 6 blocks) A-blocks for the “B” Cabine(The Standard “B” cabinet has 36 18-point terminal blocks).

The term “half-shell” is Westinghouse terminology for the metal structure thatsupports the terminal blocks in these cabinets. One half-shell supports one A-bConductors carrying field signals to and from the user’s process or plant areconnected to each block’s No. 6 screw terminals (The Standard “B” cabinet uNo. 8 screw terminals).

These screw terminals accept up to a No. 10 AWG conductor. An optional, 20-pB-block can be added to the half-shell when auxiliary power or grounding isrequired (for instance, when contact inputs requiring 48 V power are used). LikeA-block, the B-block uses No. 6 screw terminals, which can accept up to No.AWG conductor (Standard “B” cabinet uses No. 8 screw terminals).

Each half-shell is identified by “zone” and “row”.Table2-2 illustrates some of thedifferences between the Standard and Enhanced Cabinets.Figure 2-10 shows theEnhanced “B” Cabinet termination hardware, and identifies the zones and row

Table 2-2. “B” Cabinet Types

Cabinet Type Item Capacity/Size

Standard

Terminal Blocks 36

Half Shell Zones 6

Terminal Points 18

Connecting Screw Size #8

Enhanced

Terminal Blocks 48

Half Shell Zones 8

Terminal Points 20

Connecting Screw Size #6

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2-8. “B” Cabinet Field Terminations and Addressing

Figure 2-9. Standard “A” Cabinet and Field Connections

Edge Connector for Field Terminations

FUSE

Paddle Cardfor Expansion

CARD

EDGE

CONNECTOR

Slot 1Q-Card

Q-Crate

ElectronicsA-Cabinet

Front

Q

CRATE

ZONES

Q1

Q2

Q3

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2-8. “B” Cabinet Field Terminations and Addressing

Figure 2-10. Enhanced “B” Cabinet, Termination Structure

A

B

C

D

E

F

G

H

CabinetZones

Top View

Front View

Detail of Half-Shell

of Cabinet withHalf-Shells

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

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2-8. “B” Cabinet Field Terminations and Addressing

20

Table2-3 illustrates the half-shell zones, rows, and terminal point numbers (1 tofrom bottom) of the Enhanced terminations cabinet.

Table 2-3. Enhanced Half-Shell Terminal Locations

Row NumbersZones1 2 3 4 5 6

20••1

20••1

20••1

20••1

20••1

20••1

A

20••1

20••1

20••1

20••1

20••1

20••1

B

20••1

20••1

20••1

20••1

20••1

20••1

C

20••1

20••1

20••1

20••1

20••1

20••1

D

20••1

20••1

20••1

20••1

20••1

20••1

E

20••1

20••1

20••1

20••1

20••1

20••1

F

20••1

20••1

20••1

20••1

20••1

20••1

G

20••1

20••1

20••1

20••1

20••1

20••1

H

NotesB-Block Terminals not shown.Standard cabinets have only 18 terminals and Zones A-F.

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2-8. “B” Cabinet Field Terminations and Addressing

l thettom

PC

omeards,

and

4

4

4

4

These terminal numbers, along with the half-shell identifiers, are used to labesignals (or points). For example, the analog signal which terminates at the boterminal of the half-shell A1 A-block is identified as A1 A01.

The next terminal on that A-Block is identified as A1 A02, and so on.

Digital points (terminated at B-Blocks), have labels such as C1 B20 (whichindicated the highest terminal on the B-Block of half-shell zone C, row 1).

The 48 half-shells are assigned on a one-for-one basis to 48 Q-line process I/Oboard (Q-card) locations (slots) in the associated “A” Cabinet.

Table 2-4 shows the standard assignments of half-shells to Q-Card slots. In scontrol system applications, a 20-point A-block may be assigned to several Q-cto facilitate hard M/A station field wiring.

The half-shell to Q-Card cable connectors are labeled to assist in identificationplacement. The cable labeling convention is shown inTable 2-4.

Table 2-4. Half-Shell to Q-Card Connection

Q-CrateNumber Q-Crate Slot 1 2 3 4 5 6 7 8 9 10 11 12

1

Card EdgeIdentification

102 104 106 108 110 112 114 116 118 120 122 12

Half-ShellZone-Row

A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6

2

Card EdgeIdentification

202 204 206 208 210 212 214 216 218 220 222 22

Half-ShellZone-Row

C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6

3

Card EdgeIdentification

302 304 306 308 310 312 314 316 318 320 322 32

Half-ShellZone-Row

E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6

4

Card EdgeIdentification

402 404 406 408 410 412 414 416 418 420 422 42

Half-ShellZone-Row

G1 H1 G2 H2 G3 H3 G4 H4 G5 H5 G6 H6

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2-8. “B” Cabinet Field Terminations and Addressing

et.rates

A cable connects each half-shell with the corresponding Q-Card in the “A” cabinThe cable connector, which attaches to the front edge of the Q-Card, incorponine jumpers used to select the Q-Card address (shown inFigure 2-11). Foradditional information on Q-Card address selection, refer toSection 2-10 andAppendix B.

Figure 2-11. Address Jumpers on Cable Connector (“B” Cabinet Terminations)

28 (Last Address Jumper)27262524232221 (First Address Jumper

Location)

Note:The first 20 locations arereserved for card wiring.

WDPFIIQ- L i n eI / O

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2-9. Q-Card Hardware Address Selection

to

ilable be

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lockard

2-9. Q-Card Hardware Address Selection

The following Sections provide guidelines for assigning hardware addresses Q-Cards, and describe the use of the address jumpers.

If using Westinghouse supplied termination lists (or hardware addresses havealready been assigned), proceed toSection 2-12.

2-9.1. Determining Q-Card Addresses

Q-Card address assignment is dependent on several factors, including the avahardware addresses and the number and type of cards. Constraints may alsoimposed by the database size, and by the Q-Crate slot assignments (when dnaming is used). Each of these factors is discussed below.

Available Hardware Addresses (Standard)

Each cabinet consists of up to three Q-crates with 12 slots per crate for a maximtotal of up to 36 cards per cabinet. When using an extended A (AX) cabinet, ttotal is doubled to 72 per DPU.

Available Hardware Addresses (Enhanced)

Each cabinet consists of up to four Q-crates with 12 slots per crate, for a maximtotal of up to 48 cards per cabinet. When using an extended A (AX) cabinet, ttotal is doubled to 96 per DPU.

Address Blocks

Two address blocks are available for Q-Card hardware addressing for each ca80-F7 and 08-7F. Within these blocks, addresses FC-FF and 00-07 are not avaiNote that the hardware address range is the same for A cabinets and AX cabalthough the software addresses will be different. For information on calculatisoftware addresses, refer to “MA C Application Utilities User’s Guide” (U0-0136).

Caution

Do not use restricted blocks (FC-FF and 00-07)for hardware addressing.

When possible, it is recommended that addressing be confined to the upper b(80-F7).Figure 2-12 shows a worksheet that can be used when assigning Q-Caddresses. This worksheet also appears inAppendix A.

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2-9. Q-Card Hardware Address Selection

ing

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To use this worksheet, begin with the top block (80-F7), and fill in the cards usthe guidelines given below:

• Reserve address F8-FB for cold junction compensation QRT card (whethecurrently used or possible future addition), except when cold junctioncompensation is to be accomplished using a QAV card (level 6QAV or aboor half-shell compensation.

• QSE card cannot be placed in an extended (AX) cabinet.

• Reserve address 80 for QTB (Time Base) card, if applicable:

— If any AI points for QAI cards are terminated in a cabinet, a QTB card mube placed in that cabinet. For example, if both the A and the AX cabinet hAI point terminations, each cabinet must have a QTB card.

— With a 486-based DPU, a QBE is not currently supported. Therefore, iQAI card is used, the QTB must be in the same crate as the QAI.

— For QAV and QAW cards, the QTB card is optional (jumper selectable).selected, in the event of QTB failure, the QAV/QAW card’s point qualitywill be set to bad. If QTB monitoring is not selected, the QAV/QAW noisrejection rating will be lower than otherwise specified.

— When a second (back-up) QTB is used within a cabinet, it is assigned same address (80) as the primary QTB. Refer to the QTB card descripin Section 3 for additional details.

• No more than 30 QLI cards may be used with a DPU, due to timingconsiderations.

• If implementing DIOB Check, assign hardware addresses AA and 55 (whicannot be used by any other cards) to the QBO cards. The preferred layoutplace one QBO in crate 1 and one QBO in crate 2, 3 or 4. For additionalinformation on DIOB Check, refer to“DPU Introduction and Configurations”(U0-0135).

• To maximize utility, assign card hardware addresses (if applicable) in thefollowing order:

1. Reserve F8-FB for QRT (for cold junction compensation) when a QAX cais used for temperature compensation, this address block can be used

2. Assign QTB cards, (time base for QAI/QAV/QAW/QRT).

3. Assign QBO cards, (for DIOB Check).

4. Assign remaining point cards in descending order by number of channas described inFigure 2-12.

M0-0053 2-30 5/99Westinghouse Proprietary Class 2C

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2-9. Q-Card Hardware Address Selection

Figure 2-12. Q-Card Hardware Address Selection Form

Worksheet A

Q-Card Address Assignments

*8081828384858687

*9091929394959697

*A0A1A2A3A4A5A6A7

*B0B1B2B3B4B5B6B7

*C0C1C2C3C4C5C6C7

D0D1D2D3

*D4D5D6D7

* E0E1E2E3

*E4E5E6E7

*F0F1F2F3

*F4F5F6F7

*88898A8B8C8D8E8F

*98999A9B9C9D9E9F

*A8A9AAABACADAEAF

*B8B9BABBBCBDBEBF

*C8C9CACB

*CCCDCECF

*D8D9DADB

*DCDDDEDF

*E8E9EAEB

*ECEDEEEF

*F8F9FAFBFCFDFEFF

0001020304050607

*1011121314151617

*2021222324252627

*3031323334353637

*4041424344454647

*5051525354555657

*6061626364656667

*7071727374757677

* 08090A0B0C0D0E0F

*18191A1B1C1D1E1F

* 28292A2B2C2D2E2F

*38393A3B3C3D3E3F

*48494A4B4C4D4E4F

*58595A5B5C5D5E5F

* 68696A6B6C6D6E6F

*78797A7B7C7D7E7F

Indicates restricted address – DO NOT USEIndicates reserved address (80 = QTB; AA and 55 = QBO; F8-FB = QRT)

Indicates address used with default naming feature*Q-Cards with:

12 channels (QAX) must start at zero and use 2 blocks of 6 addresses

4 channels (QAI, QAO, QPA, QSE) must start at x0, x4, x8, xC2 channels (QAA, QAM, QLC) must start at x0, x2, x4, x6, x8, xA, xC, xE

where x = 0 through F

Other cards (QBI, QCI, QDI, QID, QRO, QSC, QSP, QTO) may use any address

Available only if QTB and/or DIOB checking is not implemented

8 or 6 channels (QAH, QAV, QAW, QLI, QLJ) must start at x0, x8

Note

QBI and QDI are being replaced by the QID card

5/99 2-31 M0-0053Westinghouse Proprietary Class 2C

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2-9. Q-Card Hardware Address Selection

dress,t

f six

x0

, x4,

A,

ightthen

rger

nnel

rtingsses

annel

gnal,d

Placement of Q-Cards by Number of Channels

Cards which have more than one channel require more than one hardware adas illustrated inFigure 2-13. Starting addresses for these cards (circuit 0) musfollow these rules:

• Twelve-channel cards (QAX) must start at address 0 and use two blocks oaddresses.

• Six and eight-channel cards (QAH, QAV, QAW, QLI) must start at addressor x8 (where x = 0 through F).

• Four-channel cards (QAI, QAO, QRT, QPA, QSE must start at address x0x8, or xC (where x = 0 through F).

• Two-channel cards (QAA, QAM must start at address x0, x2, x4, x6, x8, xxC, or xE (where x = 0 through F).

• All other cards require a single address.

When assigning Q-Card addresses, begin with the largest channel number (eand six) and assign those cards first. Proceed with the four-channel cards andthe two-channel cards. Finally, assign the digital single-channel cards. Thisapproach will allow the smaller address assignments to be filled in around the laassignments.

Note that no more than 30 of the six- or eight-channel cards, or 15 of the 12-chacards may be included in a cabinet, because of the addressing constraints.

As Figure2-13 illustrates, address blocks 80-FF and 00-7F each contain 16 staaddresses of 0 or 8, for a total of 32. However, because of the reserved addre(FC-FF and 00-07), addresses F8 and 00 cannot be used for the six- or eight-chcards. This leaves 30 addresses available.

Enable and Hl/LO Signals

In addition to the hardware address, some cards require an Enable or Hl/LO sias described inSection2-10. For additional information, refer to the individual cardescriptions inSection 3.

M0-0053 2-32 5/99Westinghouse Proprietary Class 2C

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2-9. Q-Card Hardware Address Selection

Q-Card Address Example

Figure 2-14 illustrates address selections for a DPU with the following cards:

Figure 2-13. Q-Card Number of Channels and Starting Address

1 QRT 2 QCI 3 QLI 15 QAV1 QTB 3 QSE 6 QAM2 QBO 3 QAO 6 QAW

StartingAddress

StartingAddress

StartingAddress

AddressStarting

AddressStarting

AddressStarting

0 or 8 0 or 8 0 or 8

0 or 80 or 8

EightChannels/Addresses

SixChannels/Addresses

FourChannels/Addresses

4 or C

TwoChannels/Addresses

OneChannel/Addresses

Eight Bits1/2 Address

2 or A

4 or C

6 or E

1 or 9

2 or A

3 or B

4 or C

5 or D

6 or E

7 or F

0 or 8

1 or 9

2 or A

3 or B

4 or C

5 or D

6 or E

7 or F

Hi/Lo

Hi/Lo

Hi/Lo

Hi/Lo

Hi/Lo

Hi/Lo

Hi/Lo

Hi/Lo

QAHQAV*QLI

QAV*QAW

QAIQAOQPAQRTQSE

QAAQAM

QBIQBOQID

QROQTO

5/99 2-33 M0-0053Westinghouse Proprietary Class 2C

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2-9. Q-Card Hardware Address Selection

Figure 2-14. Q-Card Hardware Address Selection Example

QAW

QAM

08090A0B0C0D0E0F

18191A1B1C1D1E1F

28292A2B2C2D2E2F

38393A3B3C3D3E3F

48494A4B4C4D4E4F

58595A5B5C5D5E5F

68696A6B6C6D6E6F

78797A7B7C7D7E7F

QTB

QCIQCIQAM

QAW

QAM

QAV

QBO

QSE

QRT

QSE

QAO

QBO

QSE

INDICATES RESTRICTED ADDRESS

Notice this example shows level 6 QAV cards, which require eight addresses.

8081828384858687

9091929394959697

A0A1A2A3A4A5A6A7

B0B1B2B3B4B5B6B7

C0C1C2C3C4C5C6C7

D0D1D2D3D4D5D6D7

E0E1E2E3E4E5E6E7

F0F1F2F3F4F5F6F7

88898A8B8C8D8E8F

98999A9B9C9D9E9F

A8A9AAABACADAEAF

B8B9BABBBCBDBEBF

C8C9CACBCCCDCECF

D8D9DADBDCDDDEDF

E8E9EAEBECEDEEEF

F8F9FAFBFCFDFEFF

0001020304050607

1011121314151617

2021222324252627

3031323334353637

4041424344454647

5051525354555657

6061626364656667

7071727374757677

QAV QAV QAV QAV

QAV

QAVQAV

QAV

QAV

QAVQAV QLI QLI

QLI

QAV QAV QAVQAW

QAM

QAW

QAM

QAW

QAM

QAW

QAO

QAO

M0-0053 2-34 5/99Westinghouse Proprietary Class 2C

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2-9. Q-Card Hardware Address Selection

ate slotfic

the

ed,

afy of

K is

aints

Q-Card Addresses and Q-Crate Slot Assignments

In most cases, the address assigned to a Q-Card does not depend on the Q-Crin which it is placed. However, if using the MEDIT default naming feature, speciaddresses must be associated with the Q-Crate card slots.

Appendix A contains two worksheets which can be copied and used to recordQ-Cards placement and addressing. Worksheet B can be used for any cardplacement scheme. Worksheet C, to be used when default naming will be usshows the addresses assigned to each card slot.

Refer to“MA C Application Utilities User’s Guide” (U0-0136) for additionalinformation on MEDIT and default naming.

Database Limitations

When selecting a set of Q-Cards, it is necessary to consider the databaserequirements as well as the addressing requirements. Each address used byQ-Card is associated with a point in the DPU database. A specified amount omemory space within the DPU is set aside for the database. Points defined bcontrol algorithms are also allocated space within the DPU. The total amountspace available is as follows:

• For a single-speed DPU, there is 82K is available for the database and 64available for control.

• For a multi-speed DPU:

— At software level 6, there is 82K is available for the database.

— At software level 7, there is 122 K is available.

— For software levels 6 and 7, four areas of 64K and one of 32K areavailable for control.

The amount of space used by each point depends on its record type (refer to“RecordTypes User’s Guide” (U0-0131) for information on record types). To verify thatconfiguration is acceptable, calculate the amount of memory required for the podefined.

5/99 2-35 M0-0053Westinghouse Proprietary Class 2C

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2-10. Using Address Selection Jumpers

ame.

ss isslates

ss

(pinesshenLO

AV,

2-10. Using Address Selection Jumpers

As described inSection 2-12 andAppendix C, both the termination card-edgeconnectors and the half-shell cable card-edge connector provide addressingjumpers. For both types of termination hardware, the use of the jumpers is the s

The Q-Card’s hexadecimal address is translated into binary. This binary addrerepresented by jumpers 21 through 28. For example, the card address E9 traninto binary 1110 1001. The jumpering for this address is shown inFigure2-15. Asshown, each jumper represents a 1, and is removed to represent 0.

Refer toAppendix B for a conversion table that provides a hexadecimal addreconversion.

Note that certain cards (QAA, QAX, QPA, and QLl) use different jumperingschemes. Refer to the individual card descriptions inSection 3 for details.

High/Low or Enable Jumpering

While the first eight jumpers are used to select the address, the ninth jumper number 20) is used to select Hl/LO or ENABLE. The QRO and QTO can addrthe high or low 8 bits of a 16 bit address, based on the setting of this jumper. Wthe jumper is inserted, HI is selected (bits 8-15). When the jumper is removed,is selected (bits 0-7).

Jumper pin 20 is a required address enable jumper for the following cards: QQAW, QLl, QRT, and QSE. Refer to the individual card descriptions inSection 3for details.

Figure 2-15. Address Jumpering Example

1 1 1 0 1 0 0 1

28 27 26 25 24 23 22 21

Topof

Connector

E9

Jumper in Place =1Jumper Removed = 0

20

Jumper 20 inplace = High Byteor Enabled

Removed = Low Byte

M0-0053 2-36 5/99Westinghouse Proprietary Class 2C

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2-11. Pre-Wiring Considerations

,(refer

theabless Me

s.

torswer

ral

ablesuter

ardd.

2-11. Pre-Wiring ConsiderationsSite Preparation and Planning-- The WDPF System’s field wiring troughs, ductschannels, and/or false floors should already have been planned and installedto “Data Highway Installation Manual” (M0-0051) and “Highway InstallationManual (WEStations)” (M0-8000). Most potential noise problems should havebeen resolved during this installation phase.

Cable Routing -- In the typical WDPF installation, cables are routed between plant or process and the data acquisition system via conduit and raceways (ctrays). Generally, covered trays are not necessary for class Q, class L, and clacables when minimum spacing is maintained between dissimilar trays. Use thfollowing precautions to minimize or avoid noise and inter-circuit interference

• Do not route computer cables near AC or DC power conductors.

• Tightly twist power conductors (including return or neutral) as these conducmay share a cable tray with signal cables. If the cables are not twisted, poconductors should not be in the same trays as signal cables.

• Keep generator output buses with kilovolt or kiloampere power levels sevefeet away from trays with signal cables.

• Because of the associated high-frequency noise, induction heater supply cshould be far from computer cables. Spacing from such cables to any compinput or output cable should be very large (approximately 50 to 100 ft).

Additional information on selection of signal cables and on minimum spacingbetween cables can be found inSection 2 of this manual, in “Data HighwayInstallation Manual” (M0-0051), and in “Highway Installation Manual(WEStations)” (M0-8000).

Card Replacement -- Q-line I/O cards can be removed and replaced with the+ 13 VDC power on. The front-edge connector should be removed from the cand the card should be replaced before the front-edge connector is re-installe

Caution

Power to the Multibus cards within theDPU must be off before the Multibus cardsare removed and replaced.

5/99 2-37 M0-0053Westinghouse Proprietary Class 2C

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2-12. Field Wiring Half-Shell Terminations

inal

for

nals

nalts

akeals.

torsyuld

to the

until

2-12. Field Wiring Half-Shell Terminations

When a terminations cabinet is used, connections are made to its half-shell termstrips. Installation Data Sheets have been provided inSection 3 as an aid to theinstaller. These sheets show the “B” Cabinet terminal block connections usedmost applications.

When using the field terminations card-edge connectors for process I/O field sig(where connections are made directly to each Q-card, seeAppendix C).

Follow the procedures listed below for field wiring a WDPF System to the termiblocks of the Enhanced termination cabinets. Use the custom Termination Lissupplied for your system to locate specific termination points. Also refer to thespecific card information provided inSection 3.

WARNING

Remove drop power and use extreme caution whenmaking field connections to terminal blocks. A shockhazard to personnel may exist on some of the highervoltage signals.

1. Locate the field wires or cables to be connected to the selected block, and mconnections to the No. 8 (Standard) or the No. 6 (Enhanced) screw termin

Connection to these terminals can be made with up to No. 12 AWG conducor No. 10 AWG with ring terminals. Only wires and/or cables which complwith each field connection’s signal and noise minimization requirements shobe used.

2. Bundle the wires connected to the terminal block with tie wraps and thentie-wrap these cables to the cabinet frame.

Remember to leave service loops to relieve stress and/or to permit accesscabinet when it is to be moved out of position for maintenance purposes.

3. Repeat the procedures of Steps 1 and 2 for each remaining terminal blockall terminations to the cabinet have been completed.

4. If not previously done at the factory, insert the appropriate jumpers in theQ-Card’s edge connectors. Each card’s selected address should be incompliance with the terminations list.

Caution

After address selection, do not switchconnectors between cards. Doing so willunpredictably switch card addresses andchange the half-shell to card assignments.

M0-0053 2-38 5/99Westinghouse Proprietary Class 2C

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2-13. Environmental Specifications

gith

lal

2-13. Environmental Specifications

All Q-cards can be expected to perform as specified subjected to the followinenvironmental specifications. Any deviation form these specifications is noted wthe affected card.

Ambient Air Temperatures

From 0°C through+60°C (32°F through 140°F) as measured approximately 1/2inch from any point on the printed circuit card while it is mounted in its norma(vertical) position and while subject to air movements which result from naturconvection only (that is, no forced air movement).

Humidity Rating

10 to 90%, noncondensing.

Vibration

From 0.7g acceleration at 10Hz, following a straight line change, to 10gacceleration at 40Hz, and at a constant acceleration of 10g from 40 to 50 Hz.

5/99 2-39 M0-0053Westinghouse Proprietary Class 2C

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2-14. Power Consumption

2-14. Power Consumption

Table 2-5. Power Consumption and Heat Load for Q-Cards

Card Type

Current(A rms)@ 115V

Current(A rms)@ 230V

Power(Watts)

HeatDissipation(BTU/Hr)

QAA 0.11 0.05 8.1 27.7

QAC G01 0.26 0.13 19.5 66.6

QAC G02 0.10 0.05 7.2 24.9

QAC G03 0.09 0.04 6.5 22.2

QAC G04 0.16 0.08 12.2 41.7

QAC 5 0.17 0.08 13 44.4

QAH 0.17 0.08 13 44.4

QAI 0.12 0.05 8.9 30.4

QAM 0.09 0.04 6.5 22.2

QAO 0.28 0.14 21.1 72

QAV 0.22 0.1 16.3 55.7

QAW 0.22 0.1 16.3 55.7

QAX 0.19 0.09 14.5 49.8

QAXD NONE - Covered by the QAX numbers

QAXT 0.016 0.008 1.2 4.2

QBE 0.08 0.04 6.6 22.5

QBI 0.04 0.02 3.3 11.3

QBO 0.05 0.03 4.1 14

QCA Load Dependent - Consult the EPS

QCI 0.11 0.05 8.1 27.7

QDC 0.16 0.08 12.2 41.7

QDIG01, G03, G05, G07, G08,GO9, G10

0.04 0.02 3.3 11.3

M0-0053 2-40 5/99Westinghouse Proprietary Class 2C

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2-14. Power Consumption

QDI G02, G04, G06, G11 0.02 0.01 1.6 5.5

QDT 0.16 0.08 12.2 41.7

QIC 0.09 0.04 7.15 24.4

QID 0.04 0.02 3.3 11.3

QLC 0.28 0.14 21.1 72

QLI 0.26 0.13 19.5 66.6

QLJ 0.26 0.13 19.5 66.6

LIM 0.22 0.11 18.0 61.5

SLIM 0.07 0.04 6.0 20.5

QPA 0.02 0.01 1.6 5.5

QRC 0.15 0.08 11.4 38.9

QRF 0.14 0.07 10.5 35.8

QRO 0.09 0.04 6.5 22.2

QRS 0.18 0.09 13.8 46.9

QRT 0.26 0.13 19.5 66.6

QSC 0.09 0.04 6.5 22.2

QSD 0.26 0.13 21.0 71.1

QSE 0.22 0.11 16.3 55.7

QSR 0.18 0.09 13.8 46.9

QSS 0.11 0.05 8.1 27.7

QST 0.14 0.07 10.5 35.8

QTB 0.02 0.01 1.6 5.5

QTO 0.04 0.02 2.6 8.9

QVP 0.14 0.07 10.5 35.8

Table 2-5. Power Consumption and Heat Load for Q-Cards (Cont’d)

Card Type

Current(A rms)@ 115V

Current(A rms)@ 230V

Power(Watts)

HeatDissipation(BTU/Hr)

5/99 2-41 M0-0053Westinghouse Proprietary Class 2C

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sy-Cardopce

age.

esewhich

brief

Section 3. Q-Card Reference Sheets

3-1. Section Overview

This section contains reference sheets for each available Q-Card. To allow eareference, these sheets are arranged alphabetically by the three-character Qidentifier (the exceptions are the Loop Interface Module (LIM) and the Small LoInterface Module (SLIM) which appear immediately after the QLJ card referensheets). The Q-Card identifier is shown in the upper outside corner of each p

For each Q-Card, the following is provided in the reference sheets:

• Functional Description

• Specifications

• Controls/Indicators Description

• Installation Data Sheet(s)

The Installation Data Sheets provide card-specific termination information. Thsheets are provided at the end of each card description, except for those cardsdo not require field termination.Figure3-1 illustrates a typical “Standard” Q-Cardhalf-shell termination. As shown, the connections from the terminal block aredifferent for each card.

Table 3-1 lists the Q-Cards that are described in this section, and provides a description of each group of each card.

Note

Many of the wiring diagrams for the Q-cardsindicate the “Standard” termination of thecards with 18 posts. When ordering newsystems with the “Enhanced” cabinets, therewill be 20 termination points on a half-shell.The basic wiring for both the 18 and 20terminal half-shells stays the same, with onlythe first 18 terminations being used.

5/99 3-1 M0-0053Westinghouse Proprietary Class 2C

Page 68: Ovation Q Line

Figure 3-1. Typical Q-Card Termination, “Standard” Cabinet

M0-0053 3-2 5/99Westinghouse Proprietary Class 2C

Page 69: Ovation Q Line

Figure 3-2. Typical Q-Card Termination, Remote “B” Cabinet

5/99 3-3 M0-0053Westinghouse Proprietary Class 2C

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Table 3-1. Q-Card Groups and Ranges

Name Group Range

QAA(Actuator Auto/Manual Card)

G01 -16 to +16 mA (Velocity),+4 to +20 mA (Position)

G02 +4 to +20 mA (Standard),Voltage ranges between -10 and +10 VDC(Optional)

QAC(Analog Conditioning Card)

G01 0 to 10 VDC+4 to +20 mA at 24/40 VDC(1 power supply)

G02 0 to 10 VDC+4 to +20 mA at 24/40 VDC(2 auctioneered power supplies)

G03 Signal switching

G04 1 to 5 VDC+4 to +20 mA at 24/40 VDC

G05 +120 mA at + 48 VDC

G06 0V to 10VDC

QAH(High-Speed Analog Input Point Card)

G01 -10.24 to +10.235 VDC

G02 -5.12 to +5.117 VDC

G03 0 to +10.237 VDC

G04 0 to +5.119 VDC

QAI(Analog Input Card)

G01 -20 to +20 mVDC

G02 -50 to +50 mVDC

G03 -100 to +100 mVDC

G04 -500 to +500 mVDC

G05 -1 to +1 VDC

G06 -10 to +10 VDC

G07 0 to +20 mA

G08 -50 to +50 mA

M0-0053 3-4 5/99Westinghouse Proprietary Class 2C

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e

e

e

QAM(Auto/Manual Station Controller Card)

G01 0 to +10 VDC (Output)

G02 0 to +20 mA, 0 to +5 VDC (Output)

G03 0 to 5VDC

G06 1 to 5VDC

QAO(Analog Output Card)

G01 0 to +20.475 mA

G02 0 to +10.2375 VDC

G03 -10.24 to +10.235 VDC

G04 0 to +5.1187 VDC

G05 -5.12 to +5.1175 VDC

G06 -10.24 to +10.235 VDC

G07 0 to +20.475 mA

G08 -10.24 to +10.235 VDC

QAV(Analog Input Point Card)

G01 -5 to +20 mVDC, 500Ω source impedance

G02 -12.5 to +50 mVDC, 500Ω source impedanc

G03 -25 to +100 mVDC, 1KΩ source impedance

G04 -12.5 to +50 mVDC, 500Ω source impedanc

G05 -25 to +100 mVDC, 1KΩ source impedance

G06 -12.5 to +50 mVDC, 1KΩ source impedanc

GO7 -5mV to 20mV (with temperaturecompensation)

GO8 -12.5mV to 50mV (with temperaturecompensation)

GO9 -25mV to 100mV (with temperaturecompensation)

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

5/99 3-5 M0-0053Westinghouse Proprietary Class 2C

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e

QAW(Analog High-Level Input Point Card)

G01 0 to +1 VDC, 1KΩ source impedance

G02 0 to +5 VDC, 5KΩ source impedance

G03 0 to +10 VDC, 10KΩ source impedance

G04 0 to +20 mA

G05 0 to +20 mA (self-powered)

G06 0 to +50 mA

QAX(12 Point Analog Input Card)

GO1 -5mV to 20mV, 500Ω source impedance

GO2 -12.5mV to 50mV, 500Ω source impedanc

GO3 -25mV to 100mV, 1KΩ source impedance

GO4 0 to 1V, 1KΩ source impedance

GO5 0 to 5V, 5KΩ source impedance

GO6 0 to 10V, 10KΩ source impedance

QAXD (QAX Digital Daughter Board) GO1 -5mV to 20mV

GO2 -12.5mV to 50mV

GO3 -25mV to 100mV

GO4 0 to 1V

GO5 0 to 5V

GO6 0 to 10V

QAXT(Terminal Block Temperature SensingModule)

GO1 +20mV

GO2 +50mV

GO3 +100mV

GO4 +20mV

GO5 +50mV

GO6 +100mV

QBE(Bus Extender Card)

G01 DIOB discharging

G02 No DIOB discharging

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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Page 73: Ovation Q Line

QBI(Digital Input Card)(Superseded by QID Card)

G01 +5 (4 to 6) V Logic

G02 +12 (10 to 15) V Logic

G03 +12 (10 to 15) VDC

G04 +24 (20 to 30) VDC

G05 +48 (40 to 60) VDC

G06 +48 (40 to 60) VDC

G07 +125 (100 to 150) VDC

G08 +120 (100 to 150) VAC

G09 +12 (10 to 15) VDC

G10 +24 (20 to 30) VDC

G11 +120 (100 to 150) VAC (High Threshold)

QBO(Digital Output Card)

G01 60 VDC at 300 mA (max)

G02 60 VDC at 300 mA (max.)

G03 20 VDC at 16 mA (max.)

G04 20 VDC at 16 mA (max.)

G05 20 VDC at 16 mA (max.)

QCA(Current Amplifier Card)

G01 Voltage Input, Voltage Output

G02 Voltage Input, Current Output

QCI(Contact Input Card)

G02 6 to 22 mA (closed contact)

QDC(Q-Line Digital Controller Card)

G01G02

See “QDC User’s Guide” (U0-1105).

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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QDI(Digital Input Card)(Superseded by QID Card)

G02 24 VAC/VDC (8-bit differential)

G04 48 VAC/VDC (8-bit differential

G06 120 VAC/VDC

G08 12 VDC (8-bit differential

G10 48 VAC/VDC (16-bit angle-ended)

G11 120 VAC/VDC (high threshold)(8-bit differential

QDT(Diagnostic Test Card)

G01 N/A

QFR(Fiber-Optic Repeater)

G01 See“Remote Q-Line Installation Manual”(M0-0054).

QIC(Q-Line DIOB monitor)

G01 N/A

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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ed

QIDQ-Line Digital Input(To be used where QDI or QBI wereformerly specified).

G01 +5 (4 to 6) V Logic, 16 single-ended

G02 24 VAC/VDC (20 to 30), 8 differential

G03 24 VAC/VDC (20 to 30), 16 single-ended

G04 48 VAC/VDC (40 to 60), 8 differential

G05 48 VAC/VDC (40 to 60), 16 single-ended

G06 120 VAC/VDC (100 to 150), 8 differential

G07 120 VAC/VDC (100 to 150), 16 single-end

G08 12 VDC (10 to 15) 16 single-ended

G09 12 VAC/VDC (10 to 15) 16 single-ended

G10 48 VDC (40 to 60), 16 single-ended

G11 120 VAC (95 to 150), 8 differential

G12 120 VAC (95 to 150), 16 single-ended

G13 220 VAC (190 to 264), 8 differential

G14 220 VAC (190 to 264), 16 single-ended

G15 220 VDC (180 to 264), 8 differential

G16 220 VDC (180 to 264), 16 single-ended

G17 5 VDC (3A99159 only)

QLC(Q-Line Serial Link Controller)

G01 See“QLC User’s Guide” (U0-1100).

QLI(Loop Interface Card)

G01 0 to 10 VDC(Analog Input/Output)

G02 0 to 5 VDC (Analog Input),0 to 10 VDC (Analog Output)

G03 0 to 20 mA (Analog Input),4 to 20 mA (Analog Output)

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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s

s

s

QLJ(Loop Interface Card with outputReadback)

G01 0 to 10 VDC (Analog Input)0 to 10 VDC (Analog Output)0 to 10 VDC (Output Readback)

G02 0 to 5 VDC (Analog Input)0 to 10 VDC (Analog Output)0 to 10 VDC (Output Readback)

G03 0 to 20 mA (Analog Input)4 to 20 mA (Analog Output)4 to 20 mA (Output Readback)

LIM(Loop Interface Module)

G01 Four selectable operating modes

G02 One operating mode

SLIM(Serial Loop Interface Module)

G01 Four selectable operating modes

G02 One operating mode

QMT(M-Bus Terminator Card)

G01 DIOB extension with 13 VDC power statuindication, discharge circuits, voltagethreshold detection, and timeout detectionand recovery

G02 DIOB extension with 13 VDC power statuindication, discharge circuits, and voltagethreshold detection

G03 DIOB extension with 13 VDC power statuindication

QPA(Pulse Accumulator Card)

G01 48 VDC Clock Inputs48 V Control Inputs

G02 5 VDC Clock Inputs48 V Control Inputs

G03 5 VDC Clock Inputs5 V Control Inputs

G04 48 VDC Clock InputsNo Control Inputs

QRC(Remote Q-Line)

See“Remote Q-Line Installation Manual”(M0-0054).

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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)

)

nd

nd

e

QRF(Four Wire RTD Input Card)

G01 Range set by QRD (3A99114) plug-inmodule

QRO(Relay Output Card)

G01 330 VDC/250 VAC (max.) Form A (open)

G02 330 VDC/250 VAC (max.) Form B (closed

G03 330 VDC/250 VAC (max.) Form A (open)Non-inductive loads only.

G04 330 VDC/250 VAC (max.) Form B (closedNon-inductive loads only.

QRS(Redundant Station Interface Card)

G01through

G06

Consult Westinghouse for information.

QRT(RTD Input Amplifier Card)

G01 10 mV (nominal)

G02 33.3 mV (nominal)

QSC(Speed Channel Card)

G01 1.5, 1.8, 3.0, 3.6, 4.0, or 6.67 kHz; 1/8 secoupdate

G02 1.5, 1.8, 3.0, 3.6, 4.0, or 6.67 kHz; 1/2 secoupdate

QSD(Servo Driver Card)

G01 Input: 20 V peak-to-peak, 1KHz sine wav(LVDT)Output: +/- 24 mA

QSE(Sequence of Events Recorder Card)

G01 7 to 21 mA; event tagging 1/8 msec

G02 7 to 21 mA; event tagging 1 msec

QSR(Servo Driver with Position ReadbackCard)

G01 DC LVDT Supply

G02 AC LVDT Supply

G03 DC LVDT Supply

G04 AC LVDT Supply

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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nd

nd

QSS(Speed Sensor Card)

G01 1.5, 1.8, 3.0, 3.6, 6.0, or 7.2 kHz; 1/8 secoupdate

G02 1.5, 1.8, 3.0, 3.6, 6.0, or 7.2 kHz; 1/2 secoupdate

QST(Smart Transmitter Interface)

G01 See “Smart Transmitter Interface User‘sGuide” (U0-1115).

QTB(Time Base Card)

G01 60 Hz (+2 Hz Input)

G02 50 Hz (+2 Hz Input)

G03 60 Hz (+2 Hz On-board)

G04 50 Hz (+2 Hz On-board)

QTO(TRIAC Output Card)

G01 115 (80 to 140) VAC

QVP(Servo Valve Position Controller Card)

G01 LVDT interface; 80Ω (+ 24 mA)

G02 LVDT interface; 280Ω (+ 50 mA)

G03 4-20 mA loop interface; 80Ω (+ 24 mA)

G04 4-20 mA loop interface; 280Ω (+ 50 mA)

Table 3-1. Q-Card Groups and Ranges (Cont’d)

Name Group Range

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Q-Card Descriptions

The following pages describe Q-card functionality, features, and wiring.

5/99 3-13 M0-0053Westinghouse Proprietary Class 2C

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3-2. QAA

/Aly

ce

d

ichk

3-2. QAA

Actuator Auto Manual Card(Style 7379A91G01 and G02)

3-2.1. Description

The QAA card provides the interface between the DIOB controller, the OIM (Mstation), and a final controlled device such as a WEMAC or a Beck drive. If onsoft M/A stations (CRT’s) are provided, the QAA card is still required to interfathe final drive to the DIOB. The QAA card-to-OIM interface is a group ofhard-wired DIM level signals.

Block Diagrams

The QAA card is available in two groups (G01 and G02). Group one is forcontrolling fast acting actuators such as a WEMAC which provide position anvelocity feedback plus limit inputs (seeFigure3-3). Plug braking is used to stop theactuator. Group two is used to control slow acting actuators like Beck drives whprovide position feedback and limit inputs, but do not provide velocity feedbac(seeFigure 3-4).

Figure 3-3. QAA G01 Block Diagram

DACPositionRegister

ADC

Gain

Gain

ErrorComparators

PositionRIM

Output

PositionRIF

Input

VelocityRIF

Input

OutputBuffer

InputBuffer

InputBuffer

DIMOutputs

DIMInputs

+-

-

Increase/ Decrease/

DIMOutputs

M/ALogic

PlugBraking

Comparator

OutputControlLogic

DIOB Interface

DIOB

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3-2. QAA

3-2.2. Features

The QAA card provides the following features:

• Computer (Automatic) or Local Manual mode operation

• Mode selection via external OIM signals

• Watchdog timer

• Two plug-in resistor variable rate clocks (G02 only)

• Local Manual mode selection via DIOB controller

• OIM indication of computer or Local Manual mode operating status

• OIM indication of actuator position high or low limit status

• Jumper selectable QAA card logic options

• Two external auctioneered DC power supplies

• On-card potentiometer parameter adjustments

Figure 3-4. QAA G02 Block Diagram

DIOB

DACPositionRegister

ADC

GainError

Comparators

OutputControlLogic

PositionRIM

Output

PositionRIF

Input

OutputBuffer

InputBuffer

DIMOutputs

DIMInputs

+-

Increase/ Decrease/

DIMOutputs

QuarterSpeedClockHalf

SpeedClock

DIOB Interface

M/ALogic

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3-2. QAA

ard isylon

ter

The QAA card is actually two separate printed circuit cards. One card has thestandard Q-line I/O card outline and serves as the mother card. The second ca smaller, rectangular daughter card that is attached to the mother board by nspacers. A fifty-conductor flat flex cable transfers signals and power from themother board to the daughter board. An outline of the QAA card and a daughboard is shown inFigure 3-5. Detailed card views are shown inFigure 3-10 throughFigure 3-12.

Card Usage

A typical QAA usage scheme is shown inFigure 3-6.

Figure 3-5. QAA Card Outline

Figure 3-6. QAA Card Usage Scheme

J1 Connector

Daughter

Connector

Card

is underDaughter Card

QAW/ QAA QCI QAO

CL

BIASBIAS

Demand INCRDECR

RelayPanel

MotorDrive

PT

ProcessVariable

DI

PB

= Digital Input

= Push-button

FEED-BACK

Meters

DI’S/PB’SPOSN

PBS

DIOBController

QAXQAW/QAX

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3-2. QAA

Functional block diagrams of the QAA card are shown inFigure 3-7,Figure 3-8, andFigure 3-9.

Figure 3-7. QAA Card State Diagram

Figure 3-8. QAA G01 Detailed Block Diagram

LocalManual

Not AliveMode

LocalManualMode

ComputerMode

QAA Alive Bit Reset

QAA Healthy Bit Reset

QAA AliveBit Set

QAA HealthyBit Set

OIM Comp. Push-button

OIM LMAN Push-button

DIOB LMAN Bit

QAA Alive Bit Reset

QAA Healthy Bit Reset

DIOBINTER-FACE

COMMANDREGISTER

STATUSREGISTER

WATCHDOGTIMER

DEMANDREGISTER

POSITIONREGISTER

DAC

+

––

ERRORCOMPARATORS FOUR

SECONDDELAY

M/ALOGIC

OUTPUTCONTROL

LOGIC

GAIN

PLUG

COMPARATORSBRAKING

BUFFER BUFFER

BUFFER

GAINADC

POSITION(RIF INPUT)

VELOCITY(RIF INPUT)

INCREASE

DECREASE

ACTUATORENABLE

OIM AND FIELDDIM INPUTS

OIMLAMPS

(DIM OUTPUTS)• • •••

POSITIONOUTPUT TOOIM METER

(RIM OUTPUT)

(DIM OUTPUTS)

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3-2. QAA

3-2.3. Specifications

Inputs/Outputs

G01 Analog Position Input and Analog Velocity Input

Figure 3-9. QAA G02 Detailed Block Diagram

Analog Position Input Analog Velocity Input

Signal Type Unipolar RIF Bipolar RIF

Input Range 4 to 20 mA = 0 to 100% (−) 16 mA to 16 mA

Input Impedance 250 ohms+ 2% 250 ohms+ 2%

DIOBINTER-FACE

COMMANDREGISTER

STATUSREGISTER

WATCHDOGTIMER

DEMANDREGISTER

POSITIONREGISTER

DAC

+

ERRORCOMPARATORS

M/ALOGIC

OUTPUTCONTROL

LOGIC

HALF

CLOCKSPEED

BUFFER BUFFER

GAINADC

POSITION

INCREASE

DECREASE

OIM AND FIELDDIM INPUTS LAMPS

(DIM OUTPUTS)• • •••

POSITIONOUTPUT TOOIM METER

(RIM OUTPUT)

(RIM ORRIF INPUT)

QUARTER

CLOCKSPEED

(DIM OUTPUTS)

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3-2. QAA

).Bis

G02 Analog Position Input

• Standard factory installed range = 4 to 20 mA = 0 to 100%

Note

With jumper JE inserted, the resultant 250 ohms+2% input impedance converts the input current intoan equivalent 1 to 5V input voltage range.

• Input Ranges: -10V to +10V, 1 to 5V, -10V to 0V, 0 to 8V, and 0 to 10V.Each range is = 0 to 100%

• Allowable Span: 3.5V to 20V

• Bias Subtraction: 2.5V to (−)10V, selectable using various plug-in resistors

• Gain Adjustment: 0.46 to 4.0 using a plug-in resistor (5k to 75k)

Watchdog Timer

Two jumper selected time-out periods, 0.5 seconds+20% and 2.0 seconds+20%.An additional jumper may be used to disable the timer.

Operating Modes

The QAA card has two modes of operation: Computer and Local Manual (LMANIn addition, Local Manual mode has a submode that is entered when the DIOcontroller has not updated the QAA card’s watchdog timer over the DIOB. Thsubmode is called Local Manual Not Alive (LMNA).

5/99 3-19 M0-0053Westinghouse Proprietary Class 2C

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3-2. QAA

AAighsec.

3-2.4. Card Addressing and QAA Word Format

The QAA card occupies two continuous DIOB addresses (four bytes). Address bitUADD0 and control bit HI/LO are used to select one of the four bytes. When the QCard’s Demand Register is written to or read from, the low byte must precede the hbyte. The maximum time between the reading or writing of the Demand bytes is 0.1 m

The Status/Command byte is as follows:

Table 3-2. QAA Status/Command Byte Interpretation

BitNumber Status Command

0 COMPUTER/LMAN KEEP ALIVE

1 LO-LIM GO TO LMAN

2 HI-LIM RESET ACTUATOR (LATCHED)

3 QAA ALIVE COMP MODE PERMIT (LATCHED)

4 QAA HEALTHY PRIORITY COMMAND (LATCHED)

5 NOT USED (LOGIC 0) FULL SPEED (LATCHED) G02

6 NOT USED (LOGIC 0) NOT USED

7 NOT USED (LOGIC 0) NOT USED

DIOB

15 HIGH BYTE 0

POSITION (READ)/STATUS (READ) OR COMMAND (WRITE)

BASE ADDRESSPLUS

0

8 7 LOW BYTE

MSB POSITION LSB STATUS /COMMAND

15 HIGH BYTE 0

DEMAND (READ/WRITE)1

8 7 LOW BYTE

MSB LSB

6

M0-0053 3-20 5/99Westinghouse Proprietary Class 2C

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3-2. QAA

DIOB Pin Assignments

Pin assignments for the J1 connector are given inTable3-3. Pin assignments for theJ2 connector are given inTable 3-4.

Table 3-3. QAA J1 Pin Assignments

Solder State J1 Connector Pins Component Side

PRIMARY 1 2 PRIMARY

BACKUP 3 4 BACKUP

GROUND 5 6 GROUND

UADD0 7 8 UADD1

UADD2 9 10 UADD3

UADD4 11 12 UADD5

UADD6 13 14 UADD7

HI/LO 15 16 R/W

* 17 18 DATA-GATE

GROUND 19 20 DEV-BUSY/ACK

UDAT0 21 22 UDAT1

UDAT2 23 24 UDAT3

UDAT4 25 26 UDAT5

UDAT6 27 28 UDAT7

GROUND 29 30 *

* 31 32 *

* 33 34 GROUND

Notes

* These pins are open. The QAA Card does not interface to the followingDIOB signals:

UFLAG, UCAL, USYNC, UCLOCK, and UNIT.

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3-2. QAA

Table 3-4. QAA J2 Connector Pin Assignments

Component Side Signals (B) Pins Solder Side Signals (A)

CA7 28 DIOB GROUND

CA6 27 DIOB GROUND

CA5 26 DIOB GROUND

CA4 25 DIOB GROUND

CA3 24 DIOB GROUND

CA2 23 DIOB GROUND

CA1 22 DIOB GROUND

POSITION INPUT 21 VELOCITY INPUT

SIGNAL COMMON 20 SIGNAL COMMON

POSITION TO METER (+) 19 POSITION TO METER (−)

SLOT 18 SLOT

OIM GO TO COMPUTER (See Note 1) 17OIM GO TO LMAN (See Note 1)

RAISE (See Note 1) 16 LOWER (See Note 1)

HIGH LIMIT (See Note 1) 15 LOW LIMIT (See Note 1)

ACTUATOR ALIVE (See Note 1) 14 RESET WEMAC (See Note 1)

HIGH LIMIT (See Note 2) 13 LOW LIMIT (See Note 2)

COMPUTER (See Note 2) 12 LMAN (See Note 2)

ACTUATOR ENABLE (See Note 2) 11

INCREASE (See Note 2) 10 DECREASE (See Note 2)

13 V CARD BACKUP 9

PSC FOR SHIELD(+) 8V FOR SLIDEWIREPSPPSP For Actuator andPSP Feedback Unit

PSP FOR OIM (See Note 3)

876543

PSCPSC For Actuator and Feedback UnitPSCPSCPSC FOR OIMPSC FOR OIM SHIELD (See Note 3)

SYSTEM BACKUP 2 BACKUP RETURN

SYSTEM PRIMARY 1 PRIMARY RETURNNotes

1. DIM Inputs2. DIM Outputs3. PSC = POWER SUPPLY COMMON (SYSTEM GROUND)

PSP = AUCTIONEERED 21 TO 27 VOLT POWER

M0-0053 3-22 5/99Westinghouse Proprietary Class 2C

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3-2. QAA

3-2.5. Controls, Indicators, and Test Points

Figure 3-10 throughFigure 3-12 illustrate the locations of the QAA controls,indicators, and test points.Table 3-8,Table 3-9, andTable 3-10 describe them.

Figure 3-10. QAA Mother Card Components, Test Points

Figure 3-11. QAA DWC Daughter Card Components, Test Points

TP1 JS4 JS5

J1

J2

Power On

Reset

JS6,7,8

JS1,2,3

TP2 TP3

WatchdogTimer

StatusLEDs

JA

JF

JA1

TP9-12

TP7

TP5 TP8

TP3,4

TP1,2

TP14

TP13

DWC

VR10

VR2

VR1

R60

VR11

VR12

R59

VR6

VR8 VR9

VR7VR3

VR4

TP6

VR5

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3-2. QAA

e

3-2.6. QAA Tuning

Depending on the application, the QAA card may require adjustments from thfactory-shipped potentiometer settings and plug-in resistors. The followingadjustments may be made to the QAA card:

• Position feedback range (G02 only)

• Positioning accuracy (G01 and G02)

• Half-speed clock ON/OFF time (G02 only)

• Quarter-speed clock pulse width (G02 only)

• High and low limit (G02 only)

Each of these adjustments are described below.

Figure 3-12. QAA DBK Daughter Card Components, Test Points

TP7-10

TP5

TP6

TP2,3

TP1TP13

TP11 TP12

TP4VR3

DBK

JE

VR2

R59, 60

VR12

VR10 VR11

VR1

VR6

VR7

VR9VR8

VR4

R26,27,28

R16,17

J2,3

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3-2. QAA

red:

e

and

g-inriate

y be

Equipment and Set-up

In order to adjust the QAA potentiometers, the following test equipment is requi

• Q-Line Extender Card (QEX)

• Digital voltmeter

• Trim potentiometer adjustment tool (or small screwdriver)

Note

The QAA card must be installed on the QEXto provide access to potentiometers and othercomponents.

To re-calibrate the G02 QAA (after changing the position feedback range), thfollowing additional test equipment will be required:

• Precision 0 - 20 VDC power supply (adjustable to 0.1 V)

• Special Q-Line card edge connector with external test leads tied to pins 21B20B.

Select Position Feedback Range (G02 Only)

The valve position feedback range for the G02 QAA card is selectable using pluresistors R16, R26, R27, and R28. The card is factory-shipped with the appropresistors for a 4 to 20mA range.

Determine the desired range. For the standard ranges listed inTable 3-5, use theplug-in resistors as shown. To use a nonstandard range, refer to the followingdiscussion of resistor selection. When the plug-in resistors are changed, it manecessary to re-calibrate the card, as described below:

Table 3-5. QAA G02 Analog Position Input Circuit Plug-in Resistor Selection

PositionSignalRange R16 R26 R27 R28

JumpersUsed

1V to 5V 45.3K 0.1W 0.1%669A664H53

499K 0.25W 1%406A069549

200K 0.1W 0.1%669A664H13

– J2 or J3

-10V to 10V 5K 0.1W 0.1%669A664H08

499K 0.25W 1%406A069549

– 20K 0.1W 0.1%669A664H10

J2 or J3

5/99 3-25 M0-0053Westinghouse Proprietary Class 2C

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3-2. QAA

r of

7, andge, it

:

Resistor Selection for Non-Standard Position Signal Ranges

The DBK card position feedback input circuit has the ability to convert a numbedifferent input voltage or current values to a common 0 to -10 V range. Theconversion is scaled based on the values of three zero bias resistors (R26, R2R28) and one gain resistor (R16). To select a non-standard position signal ranis necessary to calculate the values for these resistors.

Note the following definitions:

If a current position feedback signal (IFB) is used, IFB is converted into an equivalentvoltage VFB, where:

Note that jumper JE must be inserted to use a current position signal.

When the zero bias and gain resistors are calculated, three cases may occur

• Case 1: VFB(0%) = 0 VIn this case, resistors R26, R27, and R28 are not required.

• Case 2: VFB(0%) < 0 V

0 to 10V 15K 0.1W 0.1%669A664H44

– – – –

0 to 8V 20K 0.1W 0.1%669A664H10

– – – –

4 to 20 mA 45.3K 0.1W 0.1%669A664H53

499K 0.25W 1%406A069549

200K 0.1W 0.1%669A664H13

– JE, J2 or J3

VFB(0%) = Zero percent of span position feedback voltage, where -10 V<VFB(0%)< 2.5 V.

VFB(100%) = One hundred percent of span position feedback voltage

Span = VFB(100%) - VFB(0%), where 3.5 V< Span< 20 V

IFB maximum = 20mA

VFB = IFB * 250 Ω

Table 3-5. QAA G02 Analog Position Input Circuit Plug-in Resistor Selection

PositionSignalRange R16 R26 R27 R28

JumpersUsed

M0-0053 3-26 5/99Westinghouse Proprietary Class 2C

Page 93: Ovation Q Line

3-2. QAA

ures.

toe (aswing

on21Bthe

R26 = 499 kΩ

R27 is not used

R28 =

• Case 3: VFB(0%) > 0 V

R26 = 499 kΩ

R27 =

R28 is not used.

For all three cases, R16must meet the following conditions:

R16 < - 4.02 kΩ

R16 + 2 kΩ > - 4.02 kΩ

Ideally, the value of R16 should be as shown below:

R16 = - 5.02 kΩ

The zero bias and gain may be fine tuned using the following calibration proced

Calibration of G02 QAA (DBK)

The G02 QAA is factory-shipped with the appropriate plug-in resistors for a 420 mA position signal range. If the resistors are changed to select a new rangdescribed above), it may be necessary to re-calibrate the card, using the folloprocedure (seeFigure 3-11 for component locations).

To set-up the card for calibration, install the QAA card using the QEX extensicard, and connect the QAA J2 to the special card-edge connector. Connect pinto the positive output terminal of the precision power supply: connect pin 20B tonegative output terminal; then turn the precision power supply on.

10 V * 20 kΩVFB 0%( )

----------------------------------–

10 V * 20 kΩVFB 0%( )

----------------------------------

10 V * 20 kΩSpan

----------------------------------

10 V * 20 kΩSpan

----------------------------------

10 V * 20 kΩSpan

----------------------------------

5/99 3-27 M0-0053Westinghouse Proprietary Class 2C

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3-2. QAA

erooribed

e.

ect

als

thin

elow:

V.

ect

als

The VFB(0%) of the new position feedback voltage range equals 0 V, then no zbias adjustment is required. If VFB(0%) does not equal 0 V, then the amount of zerbias should be adjusted using potentiometer VR4 and jumper J2 or J3, as descbelow:

1. Adjust the output voltage of the precision power supply to equal VFB(0%)+ 0.1 mV. Use the digital voltmeter to verify the power supply output voltag

2. Connect the positive lead of the digital voltmeter to test point TP4, and connthe negative lead to test point TP13.

3. Adjust potentiometer VR4 until the voltage displayed on the voltmeter equ0 V + 0.5 mV. If the voltage cannot be adjusted to within this range, movejumper JU3 from the J2 position to the J3 position. Once the voltage is wirange, leave this jumper in the selected position.

The amount of gain may be adjusted using potentiometer VR3, as described b

1. Adjust the output of the precision power supply to equal VFB(100%) + 0.3 mUse the digital voltmeter to verify the power supply output voltage.

2. Connect the positive lead of the digital voltmeter to test point TP4, and connthe negative lead to test point TP13.

3. Adjust potentiometer VR3 until the voltmeter displayed on the voltmeter equ-10 V + 2 mV.

M0-0053 3-28 5/99Westinghouse Proprietary Class 2C

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3-2. QAA

ters

nts

ters

nts

ed by

ed by

Adjusting Positioning Accuracy of G01 QAA (DWC Daughter Board)

The positioning accuracy of the G01 QAA may be adjusted using potentiomeVR8 (Negative Small Error Band), VR9 (Positive Small Error Band), VR10(Positive Large Error Band), and VR11 (Negative Large Error Band). Test poiTP9, TP10, TP11, and TP12 may be used to verify the adjustments.

The usable Large Error Band adjustment range is as follows:

+ 1% to+ 10% of span

OR

+ 0.5V to+ 5V

The usable Small Error Band adjustment range is as follows:

+ 0.15% to+ 2% of span

OR

+ 75mV to+ 1V

Adjusting Positioning Accuracy of G02 QAA (DBK Daughter Board)

The positioning accuracy of the G02 QAA may be adjusted using potentiomeVR8 (Negative Small Error Band), VR9 (Positive Small Error Band), VR10(Positive Large Error Band), and VR11 (Negative Large Error Band). Test poiTP7, TP8, TP9, and TP10 may be used to verify the adjustments.

The usable Large Error Band adjustment range is as follows:

+ 3% to+ 19.7% of span

OR

+ 1.5V to+ 9.85V

For example, a large error deadband of approximately 5% of span is representa measured voltage of -2.5V at test point TP9 and 2.5V at test point TP10.

The usable Small Error Band adjustment range is as follows:

+ 0.3% to+ 5% of span

OR

+ 0.15V to+ 2.5V

For example, a small error deadband of approximately 1% of span is representa measured voltage of 0.5V at test point TP7 and -0.5V at test point TP8.

5/99 3-29 M0-0053Westinghouse Proprietary Class 2C

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3-2. QAA

theselected the

ure:

rt

to

ff

eedk’s

varythe

Adjusting Half-Speed and Quarter-Speed Clocks (G02 Only)

On the G02 QAA, two variable duty clocks are provided to allow operation of actuator at reduced speeds. Two plug-in resistors (R59 and R60) are used toOFF and ON time values (respectively) for the medium speed clock (called th“Half-speed” clock). The low speed (or “Quarter-speed”) clock is synchronizewith the medium speed clock. A potentiometer (VR12) may be used to adjustpulse width of the second clock, to provide a lower speed.

To adjust the Half-speed and Quarter-speed clocks, use the following proced

1. Set up the QAA on the QEX extender card, as described above. Use a strip charecorder to monitor the voltages on TP11 and TP12.

2. Determine the desired ON and OFF time values for the Half-speed clock. Refer Table 3-6 and select the appropriate resistors for R59 and R60 (49.9 kΩ resistors arefactory-installed). Install the selected resistors(seeFigure 3-12) for component locations).

3. Check test point TP11 voltage waveform to verify the Half-speed clock on and otimes.

4. Adjust potentiometer VR12 to achieve the desired pulse width for the Quarter-spclock. Note that if VR12 is adjusted clockwise to its limit, the Quarter-speed clocoutput pulse will match that of the Half-speed clock. As VR12 is adjustedcounterclockwise, the ON time of the Quarter-speed clock is reduced.

5. Check test point TP12 to verify the Quarter-speed clock on and off times.

R59 and R60 are 0.25W 1% metal film (406A069) resistors whose values mayfrom 10K to 499K. 49.9K resistors are supplied in the R59 and R60 locations onstandard G02 QAA’s DBK daughter card.

Table 3-6. QAA Half-Speed Clock On and Off Time Selection

Resistor On-Time Off-Time

R60 On-time (seconds)

R59 Off-time (seconds)

10K 0.12 0.12

20K .24 .24

49.9K .6 .6

100K 1.2 1.2

200K 2.4 2.4

499K 5.9 5.9

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3-2. QAA

ints

Adjusting High and Low Limit (G02 Only)

The Low and High Limit of the G02 QAA (DBK) may be adjusted usingpotentiometers VR6 and VR7.

• The nominal High Limit adjustment range is from 94% (-4.7V) to 103.2%(-5.16V) of span.

• The nominal Low Limit adjustment range is from -2% (+0.1V) to 7.3%(-0.365V) of span.

The card is factory-shipped with the limits set at -1% and 101% of span (test poTP5 = -5.05V, TP6 = +0.05V. If a different range is desired, use the followingprocedure:

1. Adjust VR6 to change the High Limit, if desired.

2. Check test point TP5 voltage.

3. Adjust VR7 to change the Low Limit, if desired.

4. Check test point TP6 voltage.

Note

The test point TP5 or TP6 voltages multipliedby (-20%) equals the High Limit and LowLimit settings respectively as a percentage ofthe input position feedback span.

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3-2. QAA

sterd

d the

er

d

The operations possible in each mode are summarized inTable 3-7.

Table 3-7. QAA Card Operation Table

QAA DIOB Status Bits StateMode

COMP LMAN LMNA

COMPUTER/LMAN 1 0 0

LOW LIMIT 1/0 1/0 1/0

HIGH LIMIT 1/0 1/0 1/0

QAA ALIVE 1 1 1/0

QAA HEALTHY 1 1 1/03

Possible DIOB Operations COMP LMAN LMNA

READ DEMAND WORD Y Y Y

WRITE DEMAND WORD TO CONTROLDRIVE POSITION

Y N1 N

READ DRIVE POSITION Y Y Y

READ STATUS BITS Y Y Y

WRITE KEEP ALIVE Y Y Y

LMAN REQUEST Y −2 N

PRIORITY COMMAND N N/Y4 N

RESET ACTUATOR – – Y/N5

Possible OIM Operations COMP LMAN LMNA

COMP MODE REQUEST −2 Y5 N

LMAN MODE REQUEST Y −2 N

RAISE/LOWER OUTPUT N Y8 Y/N7

Notes1. A QAA Card option is available (via a plug-in jumper) that allows the data in the QAA Card’s Demand Regi

to control the card’s output while it is in LMAN mode. New values of data may be written into the DemanRegister in order to change the position of the actuator. See also Note 4.

2. It has no effect while the QAA Card is in the present mode.3. If the QAA HEALTHY bit is reset, the card is rejected to LMNA mode.4. For the card option described in Note 1 to be available, a plug-in jumper must be inserted onto the card an

PRIORITY COMMAND bit must be set.5. The UIOB/DIOB controller must have previously written a COMP. MODE PERMIT bit into the Command

Register.6. The QAA ALIVE bit must be set in order to permit the actuator to be reset via a DIOB command bit.7. For the OIMRAISE/LOWER inputs to be operative while the QAA Card is in LMNA mode, the actuator pow

must be available.8. The OIMRAISE/LOWER inputs are ignored if the PRIORITY COMMAND bit is set and the option discusse

in Notes 1 and 4 is selected.

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3-2. QAA

Light Emitting Diodes QAA (7379A91)

Potentiometers

Table 3-8. QAA LEDs

Group 1 Group 2

POWER-OK POWER-OK

ACTUATOR ALIVE ACTUATOR ALIVE

INCREASE INCREASE

DECREASE DECREASE

Table 3-9. QAA Potentiometers (Daughter Board)

Group 1 DWC (7380A66) Group 2 DBK (7380A67)

VR1 DEMAND GAIN DEMAND GAIN

VR2 ADC VOLTAGE REFERENCE ADJ. ADC VOLTAGE REFERENCE ADJ.

VR3 VELOCITY DAMPING POSITION GAIN

VR4 POSITION BIAS POSITION BIAS

VR5 POSITION GAIN POSITION FEEDBACK GAIN

VR6 POSITIVE PLUG BRAKEDEADBAND

HIGH LIMIT ADJUST

VR7 NEGATIVE PLUG BRAKEDEADBAND

LOW LIMIT ADJUST

VR8 NEGATIVE SMALL ERROR BAND NEGATIVE SMALL ERROR BAND

VR9 POSITIVE SMALL ERROR BAND POSITIVE SMALL ERROR BAND

VR10 POSITION FEEDBACK GAIN POSITIVE LARGE ERROR BAND

VR11 POSITIVE LARGE ERROR BAND NEGATIVE LARGE ERROR BAND

VR12 NEGATIVE LARGE ERROR BAND QUARTER SPEED CLOCK DUTY CYCLEADJUST

VR1* - EIGHT VOLT SUPPLY OUTPUT ADJ.

* located on 7379A91 mother board

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3-2. QAA

,

Test Points

Plug-In Jumpers

JA (Both Groups) QAA (7379A91)

When this jumper is connected to test points JS2 and JS3, the PRIORITYCOMMAND option is available. If the PRIORITY COMMAND option is not usedthe jumper is moved so that it connects test points JS1 and JS2.

Table 3-10. QAA Test Points (Daughter Board)

Group 1 DWC (7380A66) Test Points Group 2 DBK (7380A67) Test Points

TP1 MINUS VELOCITY MINUS ERROR TIMES FIVE

TP2 MINUS ERROR TIMES FIVE POSITION VOLTAGE

TP3 POSITION VOLTAGE DEMAND

TP4 DEMAND MINUS POSITION

TP5 VELOCITY DAMPING HIGH LIMIT

TP6 MINUS POSITION LOW LIMIT

TP7 POSITIVE PLUG BRAKE DEADBAND NEGATIVE SMALL ERROR BAND

TP8 NEGATIVE PLUG BRAKE DEADBAND POSITIVE SMALL ERROR BAND

TP9 NEGATIVE SMALL ERROR BAND POSITIVE LARGE ERROR BAND

TP10 POSITIVE SMALL ERROR BAND NEGATIVE LARGE ERROR BAND

TP11 NEGATIVE LARGE ERROR BAND HALF SPEED CLOCK

TP12 POSITIVE LARGE ERROR BAND QUARTER SPEED CLOCK

TP13 ANALOG COMMON ANALOG COMMON

TP14 ANALOG COMMON -

TP1* AOK AOK

TP2* POWER-UP POWER-UP

TP3* +5.9V (TP3) +5.9V (TP3)

* located on 7379A91 mother board

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Page 101: Ovation Q Line

3-2. QAA

d by

ey

/orpin

rd

JD (Group Two) QAA (7379A91)

When this jumper is connected to test points JS7 and JS8, the QAA card willoperate the actuator at a fraction of the nominal velocity. This is accomplishecontrolling the DIM outputs,INCREASE andDECREASE, with the plus trainoutput of the HALF SPEED CLOCK circuit.

This option is only effective while the QAA card is in LMAN mode. Connectingthe jumper to test points JS6 and JS7 disables this option. TheINCREASE andDECREASE DIM outputs will then operate at a 100 percent duty cycle when thare activated (LMAN mode).

JE (Group Two) DBK (7380A67)

Out – Selects voltage position feedback

In – Selects 4 to 20 mA position feedback

Watchdog Timer Period Selection (Both Groups) QAA (7379A91)

JF (Both Groups) QAA (7379A91)

This jumper is not included on the board if the voltage supplied to pin 1B andpin 2B of the J2 connector is between 22.0 and 27.0 V. If the voltage supplied to1B and/or 2B is between 12.4 and 13.1 V, jumper JF is inserted onto the boabetween test points JS4 and JS5 on the mother board.

Warning

Verify the JF jumper setting prior to tuning orinstalling a QAA card. Failure to perform thischeck may result in damage to the QAA card.

JA1 Jumper Nominal Timer Period

Pin 3 to Pin 6 2.0 seconds

Pin 2 to Pin 7 0.5 seconds

Pin 1 to Pin 8 Timer disabled

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Page 102: Ovation Q Line

3-2. QAA

tageange

J2 and J3 (Group Two) DBK (7380A67)

These jumpers are used to provide different bias voltages for the position volgain and bias stage. Their use is dependent on the particular position voltage rthat is used.

DIOB Power Supply Requirements

• Primary: 12.4 to 13.1 VDC, 13.0 VDC nominal

• Backup: 12.4 to 13.1 VDC

• Current: 500 mA maximum

G02 QAA Slidewire Power Supply

• Output Voltage: 8.0V±0.1V, user adjustable

• Output Current: 16 mA nominal for a 500-ohm load

External Power Supply Limits

• G01 WEMAC Primary: 22.5 VDC Minimum27.0 VDC Maximum

• G01 WEMAC Backup: 22.5 VDC Minimum27.0 VDC Maximum

• G02 Beck Primary and Backup:

Low Voltage+12.4 VDC Minimum13.1 VDC Maximum

High Voltage+22.0 VDC Minimum27.0 VDC Maximum

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Page 103: Ovation Q Line

3-3. QAC

esedonsstem.lddatarify

3-3. QAC

Analog Conditioning Card(Style 2840A86G01 through G06)

3-3.1. Description

The primary QAC function is as an analog signal conditioner. Additionally somsignal switching is provided for online testing. Automatic test versions can be uin conjunction with other Q-line cards (such as, QAI and QMD). These test versiselect either process data signal inputs or test data signal inputs for a Q-line syThere are four analog points on the QAC card. Each analog point has one fiecontact connection, two internal contact connections which may receive inputor test data, and one field output connection. A test signal may be injected to veoperation of succeeding logic stages. Six QAC groups are available.

Block Diagram

Figure 3-13. QAC Block Diagram

5/99 3-37 M0-0053Westinghouse Proprietary Class 2C

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3-3. QAC

Circuit Description

Functional block diagrams of the QAC groups are shown inFigure 3-14 throughFigure 3-17.

Figure 3-14. QAC Block Diagram (Groups 1 and 2)

AD

DR

ES

SD

ATA

DIOB

+48 V

G02

TO SIMILAR CIRCUITSAS SHOWN BELOW

+

TEST INPUT

FROM QAO

+

−K1

K1

250 Ω

TRANSMITTER

4 TO 20 mA

0 TO 10 V

+

− OUTPUT

I

K1

JUMPER

EITHEROPTIONMAY BEUSED

TEST PERMIT

CONTACT

+12 V

VOLTAGE REGULATOR ANDCURRENT LIMITING

TO T

HR

EE

OT

HE

R C

IRC

UIT

S

LAT

CH

CO

MPA

RE

8 8

FRONT CONNECTORJUMPER ARRANGEMENT

STROBE

UNIT (RESET)

+12 V 24/48 VCHOPPER(G01 ONLY)

ROUT(PLUGGABLE)

I

I

FRONT CARD EDGE CONNECTOR (J2)

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Page 105: Ovation Q Line

3-3. QAC

Figure 3-15. QAC Block Diagram (Group 3)

AD

DR

ES

SD

ATA

DIOB CONTACT

CO

MPA

RE

8 8

STROBE

UNIT (RESET)

FRONT CONNECTORJUMPER ARRANGEMENT

JUMPER

++12

TEST PERMIT

K1

K1

NORMALINPUT

OUTPUT

TO T

HR

EE

OT

HE

R C

IRC

UIT

S

TESTINPUT

CMOS

LAT

CH

SUPPLY

K1

LAT

CH

TEST

FRONT CARDEDGECONNECTOR (J2)

5/99 3-39 M0-0053Westinghouse Proprietary Class 2C

Page 106: Ovation Q Line

3-3. QAC

Figure 3-16. QAC Block Diagram (Group 4)

DIOB

TO THREE OTHER CIRCUITS

250 Ω

4 TO

NOTE

NO ADDRESS SPACE IS REQUIRED. G04 DOES NOT ADDTO THE 48 CARD LIMIT SPECIFIED FOR THE UIOB.

+24/48 VCHOPPER

ROUTI

20 mA

TRANSMITTER

IVOLTAGE REGULATORS

AND CURRENT LIMITERS

− +

TO QAI

M0-0053 3-40 5/99Westinghouse Proprietary Class 2C

Page 107: Ovation Q Line

3-3. QAC

Figure 3-17. QAC Block Diagram (Group 5)

Figure 3-18. QAC Block Diagram (Group 6)

DIOB

48 VOLTS

CHOPPER

I I

+48 V.D.C.

DIOB

TO THREE OTHER CIRCUITS

250 Ω

4 TO

+24/48 VCHOPPER

ROUT

20 mA

TRANSMITTER

VOLTAGE REGULATORSAND CURRENT LIMITERS

+-

10 V

10 VPLUGGABLE

0 - 10 VOUTPUT

(PLUGSELECTABLE)

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3-3. QAC

d to

orA

e to

dt ofaynput

ope

3-3.2. Features

• G01 provides one internal transmitter power supply with four current-limitevoltage regulators (40 to 24 V). Four amplifiers convert a loop current of 420 mA to a corresponding output voltage of 0 to 10 VDC. Test relays areavailable to switch the field input off, and inject a test input from a QAO.

• G02 converts two +48 VDC external power supplies (auctioneered) to 24 40 V transmitter supplies. Four amplifiers convert a loop current of 4 to 20 mto a corresponding output voltage of 0 to 10 VDC. Test relays are availablswitch the field inputs off and inject a test input from a QAO.

• G03 provides four DIOB-controlled DPDT, signal selectors for relayingRS-232C and controls or other low-current signals (less than 50 mA).

• G04 provides one internal transmitter power supply with four current-limitevoltage regulators (24 or 40 V). Four amplifier outputs convert a loop curren4 to 20 mA to a corresponding output voltage of 1 to 5 VDC. The outputs mbe directly connected to a high impedance (1.0 megaohm or more) analog icard (such as., QAI). There is no test provision.

• G05 provides one on-card +48 VDC power supply which supplies contactwetting voltage for up to ten QPA, QBI,QDI, or QID field inputs.

• G06 provides one on-card power supply with four current limited voltageregulators. Both the 1.00 to 5.00 volt signals obtained from the 4-20 mA locurrents via 250Ω resistors and the two proportional 0-10 volt outputs of thcard on-card amplifiers are available at the card edge.

3-3.3. Specifications

Inputs/Outputs

DIOB Input Requirements

Logic 0: 0 V to 3 V

Logic 1: 7 V to 12 V

Table 3-11. QAC Output Capabilities

Group Specification

G01: 0 V to 10 VDC, 4 mA to 20 mA at 24 or 40 VDC

G02: 0 V to 10 VDC,4 mA to 20 mA at 24 or 40 VDC

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3-3. QAC

Output Buffer Specifications (G01 and G02 only)

Accuracy: 0.2 percent (additive to a QAI with a 0 to 10 V span)

Load Resistance: 4 kΩ (minimum)

Temperature Coefficient: 40 PPM/°C

Signal Switching (G03 Only)

Form C Reed Relay Contacts

Voltage: 50 VDC (maximum)

Current: 50 mA (maximum)

Operate Time: 7 msec (maximum)

Release Time: 7 msec (maximum)

Relay Coil

Voltage: 12 VDC nominal

Current: 310 mA (four relays energized simultaneously)

Power Supply

Primary: 12.4 VDC to 13.1 VDC (13 VDC typical)

Backup: 12.4 VDC to 13.1 VDC

Current: G01 – 1750 mA (maximum)G02 – 675 mA (maximum)G03 – 400 mA (maximum)G04 – 1000 mA (maximum)G05 – 1000 mA (maximum)G06 – 1500 mA (maximum)

G03: Signal Switching

G04: 1 V to 5 VDC, 4 mA to 20 mA at 24 or 40 VDC

G05: 120 mA at +48 VDC

G06: 0 V to 10 VDC

Table 3-11. QAC Output Capabilities

Group Specification

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3-3. QAC

onal

nes.

Transmitter Power Supply

Voltage: 40 V+ 2.0 VDC (jumper selected)24 V + 2.0 VDC (jumper selected)

Current: 4 mA to 20 mA (nominal)30 mA+ 7 mA (short-circuit limit)

Impedance: 25.0+ 10Ω (output)

Space is provided on the card for insertion of a resister (up to 1 W), for additiloop impedance.

3-3.4. Card Addressing

The QAC card uses eight address lines, four data lines, and four DIOB control liThe first step in QAC operation involves the QAC address lines.

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3-3. QAC

dgeich iss an thelusiveignalhis

f atryess

ctor.

ly.

The address lines (UADD0 through UADD7) enter the QAC card via the rear-econnector. The address available on the DIOB is compared to the address whphysically jumpered in on the front, card-edge connector. The QAC address iselected by eight jumpers on the top, front, card-edge connector. Insertion ofjumper encodes a 1 in the address line; absence of the jumper encodes a 0 iaddress line. The jumpered address lines and the DIOB address lines are excOR’d. This configuration gates the compared addresses and outputs an AOK sfrom pin 13 (W319-1) if the address jumpers are opposite the DIOB address. Tallows ground potential to appear at the front, card-edge connector instead ovoltage. Once the QAC determines it has been addressed, the address circuioutputs the AOK signal and four data bits are latched onto the QAC. An addrselection example is shown inFigure 3-19.

Connectors and Terminations

The QAC card interfaces the DIOB via a standard DIOB, rear, card-edge conneThe analog outputs are brought out to the front, card-edge connector (J2).Table 3-12 lists the contact allocations for G01 and G02.Table 3-13throughTable3-15 list the contact allocations for G03, G04, and G05, respectiveThe QAC card connectors and test points are shown inFigure 3-20.

Figure 3-19. QAC Address Jumper Assembly

JUMPER:

JUMPER:

JUMPER:

A7 = 0

A6 = 1

A5 = 0

A4 = 0

A3 = 1

A2 = 0

A1 = 0

A0 = 1

CARD ADDRESS = 01001001 (49H)

FRONT CONNECTOR 404A037

5/99 3-45 M0-0053Westinghouse Proprietary Class 2C

Page 112: Ovation Q Line

3-3. QAC

Table 3-12. QAC G01 and G02 Contact Allocations

Point 0 Point 1 Point 2 Point 3

0 to 10 V QAI Signal PositiveNegativeShield

5A3A3B

9A7A7B

13A11A11B

17A15A15B

Transmitter Loop OutReturn

2B2A

6B6A

10B10A

14B14A

Test Input PositiveNegative

5B4B

9B8B

13B12B

17B16B

Power Primary +48 VBackup +48 V+12VTEST PERMIT48V RETURN

19A19B20A20B1A and 1B – G02 only

G02 only

Jumpered

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Page 113: Ovation Q Line

3-3. QAC

Table 3-13. QAC G03 Contact Allocations

Point 0 Point 1 Point 2 Point 3

Normal Input(Normally Closed)

PositiveNegative

2A2B

6A6B

10A10B

14A14B

Test Input(Normally Open)

PositiveNegative

5B4A

9B8B

13B12A

17B16A

Output (Armature) PositiveNegativeShield

5A3A3B

9A7A7B

13A11A11B

17A15A15B

Power +12VTEST PERMIT

20A20B

19A, 19B1A, 1B

Table 3-14. QAC G04 Contact Allocations

Point 0 Point 1 Point 2 Point 3

Transmitter Loop OutReturn

2B2A

6B6A

10B10A

14B14A

Output PositiveNegativeShield

5A3A3B

9A7A7B

13A11A11B

17A15A15B

No Connections 1A, 1B, 19A, 19B, 20A, 20B

Table 3-15. QAC G05 Contact Allocations

Power Supply +48V 19A, 19B

+48V Return 1A, 1B

Jumpered

No Connection

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Page 114: Ovation Q Line

3-3. QAC

3-3.5. Controls and Indicators

Table 3-16. QAC G06 Contact Allocations

Point 0 Point 1 Point 2 Point 3

0 - 10 V Signal PositiveNegativeShield

5A3A3B

9A7A7B

13A11A11B

17A15A15B

Transmitter Loop OutReturn

2B2A

6B6B

10B10A

14B14A

1.0 - 5.0 V Signal PlusMinus

5B4B

9B8B

13B12B

17B16B

Power +12V auctioneered, fusedTEST PERMIT

20A20B

+48 Backup+48 Backup

19A19 B

Figure 3-20. QAC Card Components (Indicators and test Points)

Jumpered

LEDsG01,2,3Test Points

G01-4, 6

LEDG01-6

LEDG01-3

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3-4. QAH

ntialt is

ethe

al

3-4. QAH

High Speed Analog Input Point(Style 7379A36G01 through G04 )

3-4.1. Description

Groups 01, 02, 03, 04, are applicable for use in the CE MARK Certified System

The QAH card is a high-speed, A/D converter which interfaces to the DIOB inprocess control systems. The QAH card processes up to eight high level differeinputs from the field process points in the plant environment. Each bipolar inpuconverted to a 16-bit digital value and stored in RAM. The analog signal value(11 bits), a polarity bit, an overrange bit, and a system-in-operation bit and onunused bit comprise the 16-bit digital value. This stored data is multiplexed viaDIOB to the DIOB controller when the QAH is addressed.

3-4.2. Features

The QAH card is available in four groups (G01 through G04), providing severanalog input ranges. The QAH card offers the following features:

Figure 3-21. QAH Block Diagram

DIOBDATA Address

AddressSelection

and Control

OpticalIsolation

A/DConverter

AnalogMUX

SignalConditioning

0 7

From ProcessField Points

...

RAMMemory

5/99 3-49 M0-0053Westinghouse Proprietary Class 2C

Page 116: Ovation Q Line

3-4. QAH

ee

atingn beation

andfirstod

• Two jumper-selectable modes of operation.

• Continual input scanning and RAM updating

• 0.64 msec scan rate for all groups.

• Jumper-selectable zero checking and + and− full scale checking for bothbipolar and unipolar operation.

• Isolated on-card power supplied.

• Analog/digital isolation.

• IEEE surge withstand protection on input circuits.

The QAH card multiplexes eight high-level differential inputs to a high-speed,successive approximation, A/D converter. Optical and transformer isolationseparates the analog section from the digital and/or DIOB interface section (sFigure 3-21).

The input point scan period is 0.64 msec. Scan rates can be increased by truncthe number of points per card to be scanned. One, two, four, or eight points cascanned by the QAH card. The scan rate approximately doubles for each truncstep.

The QAH has two jumper-select modes of scan: “Continuous Scan” and “ScanHold.” In the “scan and hold” mode, a scan can be initiated in two ways. The method is to write to the normal DIOB address of the QAH. The second methuses a group write address which triggers a group of QAH cards to providesimultaneous data snapshots.

3-4.3. Specifications

Power Requirements

• Primary: 12.4 to 13.1 VDC

• Secondary: 12.4 to 13.1 VDC

• Current: 800mA Maximum

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3-4. QAH

ect

Input Filter Time Constant: 0.3µs (min.)10 µs (max.)

DC Common Mode Rejection: 60dB

DC Input Impedance: 5 megohm at full scale.

Sustained overrange input: 30 V relative to analog common.

Source Impedance: 200Ω max.

Overrange input impedance: 2,000Ω min.

Isolation:

Analog common to DIOB common: 500 V max.

The analog common will withstand the IEEE surge waveform applied with respto the DIOB common without damage to the QAH card.

Note

All QAH data is invalid until anothercomplete scan has been made after the surgewaveform is removed.

A block diagram of the QAH is shown inFigure 3-22.

Input Range (Volts) Common ModeRange Span (Volts) (Typ.) Volts/Step

G01: −10.240 to +10.235 ±1.76 V 20.475 5.0 mV

G02: −5.120 to +5.1175 ± 6 V 10.2375 2.5 mV

G03: 0 to +10.2375 ± 1.76 V 10.2375 2.5 mV

G04: 0 to +5.11875 ± 6 V 5.11875 1.25 mV

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3-4. QAH

gh

for

E

ointsach

Inputs and Outputs

The QAH input consists of eight differential inputs which are multiplexed to a hispeed A/D converter. This analog section is isolated from the digital and DIOBinterface section. The isolation is transformer-type for power and optical-typedata. Each input contains an RLC filter with a time constant of approximately1 microsecond and a clamp. This circuit allows the inputs to withstand the IEEsurge without damage.

To increase the scan rate for the continuous scan operating modes, the input pcan be truncated to only scan 1, 2, or 4 points. The scan rate is doubled for etruncated step. SeeTable 3-17.

Input DC Accuracy

Reference accuracy:± 0.1% of span± 1/2 LSB at 99.7% confidence.

Temperature coefficient: 40 ppm/°C of 20.475 V span45 ppm/°C of 10.2375 V span50 ppm/°C of 5.11875 V span

Linearity: 0.05% of span

Reference condition:25°C temperature, +13 VDC power supply,0 V common mode

Table 3-17. QAH Conversion Scan Time

Number of Points G01, 2, 3, 4

8 640µsec

4 320µsec

2 160µsec

1 80µsec

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3-4. QAH

d inctedB

3-4.4. Card Addressing and Data Output

Address Jumpers

The QAH card address is established by five jumper fixtures which are locatethe front-edge connector. The insertion of a jumper encodes a “1” on the seleaddress line (ADD3 through ADD7) which when matched by the UIOB or DIOaddress signals selects the QAH card by the system controller.

Figure 3-22. QAH Card Functional Block Diagram

INP

UT

CO

NT

RO

L

PO

WE

RS

UP

PLY

SC

AN

CO

NT

RO

LLE

R

A/D

CO

NV

ER

TE

R

AD

DR

ES

SC

OU

NT

ER

LAT

CH

DAT

AM

ULT

IPLE

XE

R

CLO

CK

AN

DC

ON

TR

OL

CIR

CU

ITR

Y

SE

RIA

L-PA

RA

LLE

LC

ON

VE

RT

ER

RE

AD

/S

CA

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TE

2:1

DAT

AM

ULT

IPLE

XE

R RA

M

SIG

NA

L (+

)

SIG

NA

L (−

)

AN

ALO

GC

OM

MO

N

TY

PIC

AL

INP

UT

DIO

B A

DD

RE

SS

DIO

BD

ATA

AD

DR

ES

S

ME

MO

RY

AD

DR

ES

S

CLO

CK

CLO

CK

(R/W

)

SC

AN

/HO

LD

CO

NV

DAT

A

CH

AN

NE

L

STA

TU

S

5/99 3-53 M0-0053Westinghouse Proprietary Class 2C

Page 120: Ovation Q Line

3-4. QAH

n the

insd on

tacts

on

bit issionmosterteruringd of

The optional group address for the QAH card is established by three jumpers ofront-edge connector.

Figure3-23 shows the pin configuration of the front-edge connector. The “B” pof the connector are located on the component side and the “A” pins are locatethe solder side of the p-c card.

Field Input Connections

The QAH card uses a standard Q-series front edge connector. Eight pairs of conexist for the eight analog input points. One contact is for the signal (+) and thesecond is for its return (−). SeeFigure 3-23.

The analog common is also brought out with the field inputs. This analog commshould be tied to the system ground or earth ground.

Output Data

There are two status bits: overrange and system operational. The overrange determined by a digital comparison of the most positive or most negative converresults. If the input is overrange, the conversion result is the most positive or negative result. In the scan mode, the system operational bit is high if the convis operating. In the scan and hold mode, the system operational bit goes high dthe first point conversion and stays high for at least ten milliseconds after the enthe scan. QAH word formats are shown inFigure 3-24.

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3-4. QAH

Figure 3-23. QAH Card Front-Edge Connector Pin Assignments

Figure 3-24. QAH Word Formats

1A

2A

3A

4A

5A

6A

7A

8A

9A

10A

11A

12A

13A

14A

15A

16A

17A

18A

19A

20A

21A

22A

23A

24A

25A

26A

27A

28A

1B

2B

3B

4B

5B

6B

7B

8B

9B

10B

11B

12B

13B

14B

15B

16B

17B

18B

19B

20B

21B

22B

23B

24B

25B

26B

27B

28B

SolderSide

ComponentSide

Point 0 – InputPoint 0 + Input

Point 1 + Input

Point 2 + Input

Point 3 + Input

Point 4 + Input

Point 5 + Input

Point 6 + Input

Point 7 + Input

Point 1 – Input

Point 2 – Input

Point 3 – Input

Point 4 – Input

Point 5 – Input

Point 6 – Input

Point 7 – Input

Analog Common Analog Common

Group Address Line S0 Common Group Address Line S0

Group Address Line S1 Common

Group Address Line S2 Common

Group Address Line S1

Group Address Line S2

Address Line A3 Common

Address Line A4 Common

Address Line A5 Common

Address Line A6 Common

Address Line A7 Common

Address Line A3

Address Line A4

Address Line A5

Address Line A6

Address Line A7

BINARY xx xxxx xxxx x0 BIPOLAR

SIGN

0xxx xxxx xxxx x0

Card OK

UNIPOLAR

Overrange

Not Used

Card OK

Overrange

Not Used

5/99 3-55 M0-0053Westinghouse Proprietary Class 2C

Page 122: Ovation Q Line

3-4. QAH

n).

ed

A bipolar conversion produces a 12-bit 2’s complement result (11 bits plus sigThis number is left justified minus one with an extended sign in the MSB. SeeTable 3-18

A unipolar conversion produces a 12-bit binary result. This number is left justifiminus one with the MSB set to 0. SeeTable 3-19.

Table 3-18. QAH Bipolar Conversion Dataword

G01 Input G02 Input Result

+10.235 V +5.1175 V 3FFB

+10.230 V +5.115 V 3FF1

0.0 V 0.0 V 0001

-10.235 V −5.1175 V C009

−10.240 V −5.120 V C003

−0.005 V −0.0025 V FFF9

Table 3-19. QAH Unipolar Conversion Dataword

G03 Input G04 Input Result

+10.2375 V +5.11875 V 7FFB

+10.235 V +5.1175 V 7FF1

+0.0025 V +0.00125 V 0009

0.0 V 0.0 V 0003

High Byte Low Byte

Extended

Sign

System

Overrange

XXXX XXXX XXXX X0XX

Sign Operational2’s ComplementConversion

High Byte Low Byte

System

Overrange

0XXX XXXX XXXX X0XX

OperationalBinaryConversion

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Page 123: Ovation Q Line

3-4. QAH

canwill

rious

modee1, 2,lowthe

3-4.5. Controls and Indicators

The QAH normally scans eight input points. By positioning three jumpers, the scan be optionally truncated to one, two or four input points. Truncating the scanincrease the scan rate of the input points (seeFigure 3-25 andTable 3-20).

Jumper Settings

Two operating modes: Continuous and Scan and Hold are set by inserting vajumpers in the sockets shown inFigure 3-25. The jumpers control either whichpoints are scanned or set a scan and hold for all points. The Continuous scanthe RAM is continuously updated (seeFigure3-21). In the scan-and-hold mode, thdata is only written on command. The scan rate for the eight points for Groups3 and 4 is 0.64 milliseconds per point. When the data is read from the card, thebyte must be read first and the high byte must be read within 2 milliseconds oflow byte.

Figure 3-25. QAH Card Components

+16.5

+16.5

-16.5

-16.5

VDC

ADJ

VDC

ADJ

Common ModeNull Positive

JumpersClockAdjust

Span

SpanClock(Pin 8)

PS Osc(Pin 8)

PS OscAdj

TP6

TP7 TP5

VC VC ZeroOffset Adj

Common ModeNull Negative

W339

Jumper Detail

114

78

1 S/HS/H

S/H2 4

Output

5/99 3-57 M0-0053Westinghouse Proprietary Class 2C

Page 124: Ovation Q Line

3-4. QAH

Table 3-20. QAH Option Jumpers

QAH Operating Mode Pins Jumpered

Continuous Scan:Points 0, 1, 2, 3, 4, 5, 6,7

None

Continuous Scan:Points 0, 1, 2, 3

3 - 12

Continuous Scan:Points 0, 1

2 - 13

Continuous Scan:Point 0

1 - 14

Scan-and-holdPoints 0, 1, 2, 3, 4, 5, 6,7

5 - 10, 6 -9, 7 - 8(All S/H jumpers in place).

M0-0053 3-58 5/99Westinghouse Proprietary Class 2C

Page 125: Ovation Q Line

3-4. QAH

3-4.6. Installation Data Sheet

1 of 2

Figure 3-26. QAH Wiring Diagram

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

POINT 7

POINT 6

POINT 5

POINT 4

POINT 3

POINT 2

POINT 1

POINT 0

ANALOGCOMMON

CARD

COMMON*18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

(−)

(+)

POINT 7

POINT 6

POINT 5

POINT 4

POINT 3

POINT 2

POINT 1

POINT 0

REQUIRED ENABLE JUMPER TERMINAL BLOCK HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTOR CUSTOMER CONNECTIONS

INTERNALBUS STRIP

* Common is connected to system ground at one pointonly. Analog common used for all eight points.

5/99 3-59 M0-0053Westinghouse Proprietary Class 2C

Page 126: Ovation Q Line

3-4. QAH

For CE MARK Certified System

2 of 2

Figure 3-27. QAH CE MARK Wiring Diagram

POINT 2+

-

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

POINT 0

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

COMPRESSION-STYLE TERMINAL BLOCK

+

-

POINT 1+

-

POINT 3+

-

POINT 4+

-

POINT 5+

-

POINT 6+

-

POINT 7+

-

POINT 2+

-

POINT 0+

-

POINT 1+

-

POINT 3+

-

POINT 4+

-

POINT 5+

-

POINT 6+

-

POINT 7+

-

ANALOG COMMON

COMMON*

* Common is connected to system ground at one pointonly. Analog common used for all eight points.

M0-0053 3-60 5/99Westinghouse Proprietary Class 2C

Page 127: Ovation Q Line

3-5. QAI

Bushes

3-5. QAI

Analog Input Card(Style 2840A19G01 through G08)

3-5.1. Description

Groups 01 through G08 are applicable for use in the CE MARK Certified System

The QAI card contains four analog-to-digital (A/D) converters and a digitalmultiplexed interface to the DIOB of a process control system (seeFigure 3-28).Analog input systems consist of one or more QAI cards, a QTB card, and oneController; no other cards are required to perform the analog input function. Tsubsystem may be expanded in increments of four points by adding QAI card(48 QAI cards maximum).

Figure 3-28. QAI Block Diagram

SignalConditioning Integrator

MemoryControlLogic

A/D ControlLogic

InterfaceLogic

Field Input

OpticalIsolators

DataDIOB

Address and Control

Subtractorand

Offset Check

PointRAM

OffsetRAM

Counter

5/99 3-61 M0-0053Westinghouse Proprietary Class 2C

Page 128: Ovation Q Line

3-5. QAI

italbits.

lar

EEE

of

3-5.2. Features

Each A/D converter is dedicated to a process point in the plant environment,converting a bipolar analog field input to a 16-bit digital output. The 16-bit digdata includes the analog signal value (12 bits), polarity, overrange, and 2 errorThe QAI can be utilized in a system with any type of DIOB controller (such asMBU or MSQ), provided a QTB card is present. The card will accept four biposignals ranging from+20 mV to+10 V with 12-bit binary resolution. Inputs arefault-voltage protected and can withstand high common mode voltages and Isurge

The QAI card is available in eight groups (G01 through G08), providing a rangeanalog input parameters.

• G01:+20 mV analog inputs with a 700Ω source impedance (maximum)

• G02:+50 mV analog inputs with a 700Ω source impedance (maximum)

• G03:+100 mV analog inputs with a 1 kΩ source impedance (maximum)

• G04:+500 mV analog inputs with a 5 kΩ source impedance (maximum)

• G05:+1 V analog inputs with a 10 kΩ source impedance (maximum)

• G06:+10 V analog inputs with a 10 kΩ source impedance (maximum)

• G07: 0 to 20 mA of current for analog inputs

• G08:+50 mV analog inputs with a 1 kΩ source impedance (maximum)

The QAI card offers the following features:

• Accepts four bipolar signals ranging from+20 mV to+10 V, with 12-bit binaryresolution

• Fault-voltage protected inputs which withstand IEEE surge

• High ac normal mode and common mode rejection without any filters

• Open thermocouple detection

• Dual slope integration

• Line frequency tracking

• High conversion rate

• Digital auto-zeroing

• Auto-conversion check

• Isolated power supply for each point

• Digitized value readily available for transfer anytime

• Lock-out to facilitate system snap-shot

M0-0053 3-62 5/99Westinghouse Proprietary Class 2C

Page 129: Ovation Q Line

3-5. QAI

3-5.3. Specifications

DIOB Input Requirements

Logic 0: 0 V to 3 V

Logic 1: +8 V to +12 V

The signal lines at the DIOB interface are specified by the DIOB description.

Analog Input Capabilities

G01:−20 mV to+20 mV

G02:−50 mV to+50 mV

G03:−100 mV to+100 mV

G04:−500 mV to+500 mV

G05:−1V to +1V

G06:−10V to+10V

G07: 0 mA to+20 mA

G08:−50 mA to+50 mA

Input Impedance (minimum) Groups 1 through 6 and 8

Below 60 percent Relative humidity: 108Ω/volt

Below 90 percent Relative humidity: 107Ω/volt

Overload: 103Ω

Input Impedance Group 7

250Ω

Point Sampling (Rate/second)

60 Hz power line frequency: 30

50 Hz power line frequency: 25

Resolution

Full Scale: 12 bit

5/99 3-63 M0-0053Westinghouse Proprietary Class 2C

Page 130: Ovation Q Line

3-5. QAI

e,

g:

dB

he

Full Scale and Polarity: 13 bit

Reference Accuracy

99.7 percent confidence:+0.125 percent+10 µV+1/2 LSB of full scale

Reference Condition: 25°C ambient temperature, 0V (ac and dc) Common Mod0 VAC Normal Mode

Normal Mode Rejection

At power-line frequency and harmonics with frequency tracking: 60 dB

At power-line frequency+5 percent and harmonics without line frequency trackin20 dB

Common Mode Rejection

At DC, power line frequency and harmonics with line frequency tracking: 120

At nominal power line frequency+5 percent without line frequency tracking:100 dB

Line Frequency Tracking

Input Voltage: 120 VAC+10 percent (rms)

Input Voltage Frequency: 60 Hz+ 2Hz or 50 Hz+ 5Hz

Input Voltage Frequency Stability:+ 0.6 percent/sec (maximum change)

Frequency Tracking Compensation:+0.01 percent increments (hardwarecompensation)

Open Thermocouple Detection

Open thermocouple detection with a minus over-range signal is provided on tfollowing card groups:

• Group 1

• Group 2

• Group 3

M0-0053 3-64 5/99Westinghouse Proprietary Class 2C

Page 131: Ovation Q Line

3-5. QAI

Bnighs.

.

• Group 8 (no minus over-range)

Power Requirements

Output Codes

Functional Description

All QAIs in an analog input process control system utilize one QTB card per DIOto start continuous conversion of all four points and to establish the conversiocycle. The conversion is conducted for a full cycle of line frequency to provide hnoise rejection without relying on approximations from previous readings. Thienables the card to recover quickly from surges and continuous overvoltages

Minimum Nominal Maximum

Primary Voltage: + 12.4 V + 13.0V + 13.1 V

Backup Voltage: (optional) + 12.4 V -- + 13.1 V

Current -- 550 mA 600 mA

Output Data (Hexadecimal) Input

C000 0 input

C001 + 1

D000 + Full Scale

DXXX or 18000 + Over Range

FFFF - 1

F000 - Full Scale

EXXX - Over Range (Open thermocouple detection)18000 to BFFF Out of Range Offset

0000 to 7FFF Card Trouble

X – Don’t Care18000 may indicate either an out of range offset or an over range of at least 5%.

5/99 3-65 M0-0053Westinghouse Proprietary Class 2C

Page 132: Ovation Q Line

3-5. QAI

italtor,ted

nsise

redn

(forer, ifC)ed

Each QAI card contains four isolated A/D converters sharing a non-isolated diginterface to the DIOB. The digital section is composed of a counter accumulaRAM memory, and an interface to the DIOB. Signal coupling between the isolaand non-isolated sections is through optical isolators.

On cards rated up to+100 mV, open thermocouple detection is performed by meaof a high-impedance voltage source which is shorted out if the thermocouple good. If the thermocouple is open, the voltage for the open point is read by thconverter.

Each time a reading is completed, the digitized value is placed in RAM and stountil the next reading is complete. The stored value is unaffected by calibratiochecks.

Circuit Description

A functional block diagram of the QAI card is shown inFigure 3-29.

QAI Control Timing

A control timing diagram is shown inFigure 3-30. The Pre-Amp input and RAMselection is synchronized with the USYNC signal pulse. The integrator outputprovides the offset signal when the pre-amp input is shorted. UIOB transactionsexample, Read operations) may occur at any time during these pulses. Howeva UIOB transaction occurs at the same time as an END OF CONVERSION (EOpulse, the EOC pulse is ignored and RAM update does not occur. Similarly, thUCAL Lockout pulse (for taking a plant snapshot) overrides an EOC pulse aninhibits RAM updating.

M0-0053 3-66 5/99Westinghouse Proprietary Class 2C

Page 133: Ovation Q Line

3-5. QAI

Figure 3-29. QAI Card Block Diagram

CLO

CK

AN

ALO

GP

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TC

IRC

UIT

RY

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CC

ON

VE

RS

ION

ME

MO

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INT

RA

MO

FF

SE

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14-B

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LOG

ICC

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TR

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DIO

BIN

TE

RFA

CE

LOG

IC

TR

I-S

TAT

EB

US

DR

IVE

RS

SU

BT

RA

CTO

RO

FF

SE

TC

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12VGND

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TC

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VE

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FIE

LDS

IGN

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CW

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E

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R/W

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USYNCUCAL

UCLOCK

8UADDR

BITS

HI/LOUNITDATA-GATEDATA-DIR

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B

8

DATA

CLO

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A/DCONTROL

POWER

BUSCONTROL

ADDR

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FS

ET

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5/99 3-67 M0-0053Westinghouse Proprietary Class 2C

Page 134: Ovation Q Line

3-5. QAI

altor

Analog Point Circuitry

A general block diagram of the analog point circuitry is shown inFigure 3-31.

Figure3-32 shows Analog Point Timing. When USYNC goes high, the SIG signalso goes high and enables the summer output signal to pass into the integraamplifier. Consequently, the integrator begins ramping up as shown inFigure3-32.The integrator continues to ramp up until USYNC fails.

Figure 3-30. QAI Control Timing Diagram

POSITIVE

NEGATIVEFIELD INPUT

USYNC

UCAL

LOCK-OUT

UIOB

PRE-AMP INPUT FIELDFIELD

SHORTED

RAM SELECT POINT POINT

(ZERO)OFFSET

INTEGRATOR OUTPUT

END OF CONVERSION

RAM UPDATE

INHIBITED DUE TODIOB TRANSACTION

INHIBITED DUETO LOCKOUT

TRANSACTION OCCURRENCE

M0-0053 3-68 5/99Westinghouse Proprietary Class 2C

Page 135: Ovation Q Line

3-5. QAI

Figure 3-31. QAI Analog Point Block Diagram

OT

D

BU

FF

ER

ED

ATT

EN

UAT

OR

G06

, 7

SW

CN

MF

ILT

ER

CLA

MP

PR

E A

MP

INT

ER

FAC

ETO

NO

N-

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LAT

ED

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FS

ET

CO

NV

EO

C

RA

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CO

N-

CH

AR

GE

−+

SH

IELD

CO

NN

EC

TE

DTO

LO

W IN

PU

TAT

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UR

CE

1V F

. S.

PO

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/OF

FS

ET

SE

LEC

T

PO

WE

RS

UP

PLY

TR

OL

50K

HZ

SE

CT

ION

ANALOG INPUT

SU

MM

ER

RE

F. V

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AG

EG

EN

ER

ATO

R

INT

EG

RAT

OR

CO

MPA

R-

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R

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LC

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RG

E

ΣD

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/DΤΟ

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G F

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D

BIAS

REF

5/99 3-69 M0-0053Westinghouse Proprietary Class 2C

Page 136: Ovation Q Line

3-5. QAI

3-5.4. Card Addressing

Connectors and Terminations

The QAI card interfaces with the DIOB via a standard DIOB rear, card-edgeconnector (seeFigure 3-33).

Figure 3-32. QAI Analog Point Timing Diagram

10µsec coupling delay

USYNC

Signal

Reference

Clamp

Integrator

(RampControl)

Interval

Interval

Output

O.T.D.Charge

10V

5.5 V

1V

+ F.S Input

0V Input

- F.S Input

Signal Integration DischargeTime

CountAccumulation

Time

-F.S +F.S0V

Endof

ConversionE.O.C.

M0-0053 3-70 5/99Westinghouse Proprietary Class 2C

Page 137: Ovation Q Line

3-5. QAI

arere

The analog inputs enter the QAI on the front-edge of the card. The QAI inputsthree wire and use the same pin-outs for all groups. The contact allocations ashown inTable 3-21.

Table 3-21. QAI Analog Input Contact Allocations

Point Pin Out

Point 0 5A – (+ input)3A – (− input)3B – (shield)

Point 1 9A – (+ input)7A – (− input)7B – (shield)

Point 2 13A – (+ input)11A – (− input)11B – (shield)

Point 3 17A – (+ input)15A – (− input)15B – (shield)

Figure 3-33. QAI Card Components

Channel 0

Channel 2

Channel 1

Channel 3

DigitalCircuitry

5/99 3-71 M0-0053Westinghouse Proprietary Class 2C

Page 138: Ovation Q Line

3-5. QAI

3-5.5. Installation Data Sheet

1 of 2

Figure 3-34. QAI Wiring Diagram

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 0

(+)

(SHIELD)

(−)

(+)

(SHIELD)

(−)

POINT 3

CUSTOMER CONNECTIONS

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

POINT 0

TRANSDUCER

(+)

(−)

PLANT GROUND

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

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3-5. QAI

For CE MARK Certified System

2 of 2

Figure 3-35. QAI CE MARK Wiring Diagram

POINT 0

(−)

(SHIELD)

(+)

POINT 1

(−)

(SHIELD)

(+)

POINT 2

(−)

(SHIELD)

(+)

POINT 3

(−)

(SHIELD)

(+)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

PE

CUSTOMER CONNECTIONS

(−)

(SHIELD)

(+)

POINT 1

(−)

(SHIELD)

(+)

POINT 2

POINT 0

TRANSDUCER

(+)

(−)

PLANT GROUND

POINT 3

TRANSDUCER

(+)

(−)

Note

The QAI inputs may be grounded in the field or atthe B cabinet as shown.

5/99 3-73 M0-0053Westinghouse Proprietary Class 2C

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3-6. QAM

icee

ionctor

3-6. QAM

Automatic/Manual Station Controller(Style 7379A28G01 through G06)

3-6.1. Description

The Automatic/Manual (QAM) card provides the interface between the DIOBcontroller, the M/A station and a final controlled device. A final controlled devcan be a voltage to pressure (E/P) or a current to pressure (I/P) converter (seFigure 3-36).

The QAM card is available in six groups (G01 through G06). Electrical connectto the QAM card is made through a 9-pin connector, a 28-pin card edge conneand a 34-pin backplane connector. The QAM card connections are shown inFigure 3-40.

3-6.2. Features

The QAM card provides the following capabilities:

• Automatic or Manual mode operation

Figure 3-36. QAM Block Diagram

DIOB

UIOB or DIOBInterface Logic

Set PointUp/DownCounter

DemandUp/DownCounter

DemandD/A

Converter

Set PointD/A

Converter

Demand Set Point DigitalOutputs

DIMInputs

E/PI/P

Field Interface

M/A Interface

Data

ControlLogic

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3-6. QAM

e if

Note

The DIOB controller does not need to bepresent for Manual mode operation.

• Ability of DIOB controller to place QAM card in Manual mode

• Ability to place QAM card in either mode via external reject signals

• Switch selectable watchdog timer which places QAM card in Manual modnot periodically updated by the DIOB controller, during Automatic modeoperation.

• Ability to indicate the output demand and setpoint at the M/A station

• Ability to indicate Automatic or Manual mode selection at the M/A station

• Ability to indicate the demand’s high or low limit status at the M/A station

• Ability to input MANUAL/ AUTO, POWER OKAY, WATCHDOG ALIVE, andREJECT TO MANUAL status bits to the DIOB controller

• Ability of the QAM card to produce anALIVE digital output, which is used asa logic input in a redundant configuration

• Jumper selection and deselection of the QAM card options

• Ability of the QAM card to auctioneer two external power sources (+13 VDCto 26 VDC), supplying this voltage to the M/A station’s lamps

• Three plug in resistor variable rate clocks

• On-card Demand and Set Point zero and gain potentiometers

A QAM card functional block diagram is shown inFigure 3-37, and a systemsapplication block diagram is shown inFigure 3-38.Figure 3-39 shows a typicalQAM usage scheme.

5/99 3-75 M0-0053Westinghouse Proprietary Class 2C

Page 142: Ovation Q Line

3-6. QAM

Figure 3-37. QAM Card Functional Block Diagram

DIM

INP

UT

S

CO

NT

RO

LLO

GIC

DIG

ITA

LO

UT

PU

TS

M/A

INT

ER

FAC

E

DIO

BIN

TE

RFA

CE

LOG

IC

SE

TP

OIN

TU

P/D

OW

NC

OU

NT

ER

SE

TP

OIN

TD

/AC

ON

VE

RT

ER

SE

TP

OIN

TG

01, 2

, 3, 6

: 0 -

10

VD

C

DE

MA

ND

UP

/DO

WN

CO

UN

TE

R

DE

MA

ND

D/A

CO

NV

ER

TE

R

D I O B

+10

VD

CR

EF

G02

, 6

DE

MA

ND

RIM

G01

2

RIF

G02

, 4: 4

- 2

0 m

A

G01

: 0 -

10

VD

C

G02

, 4, 6

: 1-

5 V

DC

G01

: 0 -

10

VD

C

2

FIE

LDIN

TE

RFA

CE

G02

5

12

812

122

1212

G04

, 5: 1

- 5

VD

C

G03

: 0 to

5 V

DC

G03

: 0 -

180

mA

G05

, 6: 1

0 -

50 m

A

M0-0053 3-76 5/99Westinghouse Proprietary Class 2C

Page 143: Ovation Q Line

3-6. QAM

Figure 3-38. QAM Card Systems Application Block Diagram

QA

I/VC

AR

DS

QA

OC

AR

DQ

AC

CA

RD

QA

MC

AR

D

DIO

BC

ON

TR

OLL

ER

INF

OC

EN

TE

R

AI/D

M/A

ST

AT

ION

DE

M

SE

TP

OIN

TIN

C./D

EC

.

E/P

OH

I/P

CO

NV

ER

TE

RA

UX

.C

ON

TR

OL

(IN

FO

CE

NT

ER

RE

QU

IRE

D)

FE

ED

BA

CK

(4 -

20

mA

)P

RO

CE

SS

VA

RIA

BLE

DE

MA

ND

PR

OC

ES

S V

AR

IAB

LE A

ND

FE

ED

BA

CK

5/99 3-77 M0-0053Westinghouse Proprietary Class 2C

Page 144: Ovation Q Line

3-6. QAM

3-6.3. Specifications

Power Requirements

Primary Voltage:+12.4 V to 13.1 VDC

Backup Voltage:+12.4 V to 13.1 VDC

Figure 3-39. QAM Card Usage Scheme

MS

L

MB

U

(OR

MS

Q)

QA

WQ

AW

QA

MQ

CI

QA

O

PT

OU

TP

VS

P

OIM

BIA

S

C L

D E M A N D(E

)

IP

P B S

DI’s

/PB

’s

ME

TE

RS

PR

OC

ES

SV

AR

IAB

LE

DI

PB

= D

IGIT

AL

INP

UT

= P

US

HB

UT

TON

DE

MA

ND

(1)

BIA

S

M0-0053 3-78 5/99Westinghouse Proprietary Class 2C

Page 145: Ovation Q Line

3-6. QAM

ard

Current:

Note

For Groups 1, 2, 4, 5, and 6, QAM card shortcircuit protection is provided by 1.0 A plug-infuse. For Group 3 short circuit protection isprovided by 1.0 A plug-in fuse and a 1.5 Aplug-in fuse.

J1 Signal Specifications (DIOB Interface)

The QAM occupies the high and low byte of two DIOB addresses. The QAM caddress is established by seven jumpers on the J2 card-edge connector(Table 3-23). The insertion of a jumper encodes a “1” on the address line.

J2 Signal Specifications (Operator Interface)

Digital Inputs

These signals are typically connected to the operator panel pushbuttons.

• Voltage Limits: −0.5 VDC to+30 VDC

• VIH (Logic zero voltage): 10 VDC minimum

• IIH (Logic zero current): 0.1 mA maximum (at 30 VDC)

• VIL(Logic one voltage): 2.0 VDC maximum

• IIL (Logic one current):−3 mA maximum

• Delay: 0.75 msec maximum

Table 3-22. QAM Current Specification

Group Typical Maximum

01, 02, 04 0.4 A 0.75 A

03 1.00A 1.48 A

05, 06 0.65 A 0.90 A

5/99 3-79 M0-0053Westinghouse Proprietary Class 2C

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3-6. QAM

Digital Outputs

These signals typically drive the operator panel lamps.

• Voltage Limits: −0.5 VDC to+30 VDC

• LIH (Logic zero current): 0.1 mA maximum (e + 30 VDC)

• VOL(Logic one voltage)*: 1.3 VDC maximum

• LIL(Logic one current)*: 200 mA maximum

• LIL(Total)(Logic zero current)*: 450 mA maximum

Note

These values are true with the exception oftheALIVE signal, where the maximumlogic 1 voltage is 1.1 VDC and the maximumlogic 1 current is 50 mA.

Table 3-23. QAM J2 Connector Pin Assignments

Pin Number(Solder Side) Signal Name

Pin Number (ComponentSide) Signal Name

1A2A*3A*4A*5A*6A*7A*8A9A10A11A12A13A14A15A**16A17A

DIM Input CommonLOWER INHIBITRAISE INHIBITPRIORITY LOWERPRIORITY RAISEAUX MANAUX AUTO“CONNECTOR IN

PLACE” JumperSystem CommonIMASHLDIMADEM −IMADEM +System CommonALIVE OUTMA PWRAMA PWRB

1B2B*3B*4B*5B*6B*7B*8B9B10B11B12B13B14B**15B**16B**17B**

DIM Input CommonDECREASE SPINCREASE SPLOWER IN****RAISE IN***MAIN INAUTO INVMASHLDVMADEM −VMADEM +SPSHLDSETPOINT−SETPOINT+LO LIMIT OUTHI LIMIT OUTMAN OUTAUTO OUT

SLOT

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Page 147: Ovation Q Line

3-6. QAM

and.

12B

Output Demand Indication Signals

Voltage

This signal drives the operator panel meter or bargraph, indicating output dem

• G01

Span: 0 to 10 VDC

Load Resistance: 2 KΩ minimum

Current: 5 mA maximum

Common Mode Voltage:+ 10 V maximum

Accuracy: + 0.1 percent of span

Temperature coefficient: 20 ppm of span/˚C

• G02, 03, 04, 05, 06

19A20A21A22A23A24A25A26A27A28A

MA RTNDIOB GroundDIOB GroundDIOB GroundDIOB GroundDIOB GroundDIOB GroundDIOB GroundDIOB GroundDIOB Ground

19B20B21B22B23B24B25B26B27B28B

MA PWRUnusedUnusedASEL1 (LS)ASEL2 DIOBASEL3 AddressASEL4 SelectASEL5 JumpersASEL6ASEL7 (MS)

Where:

DIOB Ground = and System Common =

Notes

The following J2 connector pins are connected together on the QAM card: 10A, 11A, 14A, 8B, 9B, 11B, and* = These are DIM input signals.** = These are DIM output signals.*** = This signal is not connected on Group 3.**** = The signal provides a card reset on Group 3.

Table 3-23. QAM J2 Connector Pin Assignments (Cont’d)

Pin Number(Solder Side) Signal Name

Pin Number (ComponentSide) Signal Name

5/99 3-81 M0-0053Westinghouse Proprietary Class 2C

Page 148: Ovation Q Line

3-6. QAM

Span: 1 to 5 VDC, G03 = 0 to 5 VDC

Load Resistance: 2 KΩ minimum

Current: 2.5 mA maximum

Common Mode Voltage:+ 10 V maximum

Accuracy: + 0.25 percent of span

Temperature coefficient: 50 ppm of span/˚C

Note

Accuracy and temperature coefficientsdetermined with respect to the demandoutput.

M0-0053 3-82 5/99Westinghouse Proprietary Class 2C

Page 149: Ovation Q Line

3-6. QAM

AM

Current

This signal drives current meter on the operator panel via a series diode on the Qcard.

• Groups 02, 03, 04, 05, 06

Group 02, 04 Span: 4 to 20 mA

Group 03 Span: 0 to 180 mA

Group 05, 06 Span: 10 to 50 mA

Load Resistance G02, 04:20Ω maximum, 0Ω minimum

Load Resistance G03: 2.1Ω maximum, 0Ω minimum

Load Resistance G02, 04:8Ω maximum, 0Ω minimum

Common Mode Voltage:+ 10 V maximum

Accuracy: + 0.0%, -0.2% of span

Temperature coefficient: 50 ppm of span/˚C

Note

The load resistance is required to ensurecompliance of accuracy and temperaturespecifications. If desired, this load may be leftopen.

Accuracy and temperature coefficientsdetermined with respect to the demandoutput.

M/A Station Lamp Power

• Input Voltage: +12.4 VDC to+30 VDC

• Output Voltage: (Input Voltage) + 0.0 VDC to -1.3 VDC

• Current: 450 mA maximum

• Overcurrent Protection: 0.5 A Plug-in Fuse

5/99 3-83 M0-0053Westinghouse Proprietary Class 2C

Page 150: Ovation Q Line

3-6. QAM

Setpoint Indication Signal

• Span (G01, 02, 03, 06) 0 to 10.000 VDC

• Span (G04, 05) 1.000 to 5.000 VDC

• Load Resistance: 2 kΩ’s

• Current (G01, 02, 03, 06): 5 mA maximum

• Current (G04, 05: 2.5 mA maximum

• Common Mode Voltage: + 10 V maximum

• Accuracy: + 0.1 percent of span

• Temperature coefficient: 50 ppm of span/˚C

J3 Signal Specifications (Field Interface)

Output Demand Voltage (G01)

• Type: Unipolar Direct Positive (RIM)

• Span: 0 to 10 VDC

• Load Resistance: 500Ω’s minimum

• Current*: 20 mA maximum

• Common Mode Voltage: + 10 V maximum

• Accuracy: + 0.05 percent of span

Note

* The J3 Demand Output can be shorted tocommon without damage.

Output Demand Current

Table 3-24. QAM Output Demand Current

Parameter G02, 04 G03 G05, 06

Type RIF (UnipolarDirect Positive)

RIF (UnipolarDirect Positive)

RIF (UnipolarDirect Positive)

Span 0 to 20.000 mA 0 to 20.000 mA 0 to 20.000 mA

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Page 151: Ovation Q Line

3-6. QAM

C

Load Resistance (Min./Max.) 0Ω/1 KΩ 0 Ω/111Ω 0 Ω/400Ω

Common Mode Voltage + 10 V maximum + 10 V maximum + 10 V maximum

Accuracy + 0.05% of span + 0.05% of span + 0.05% of span

Temperature coefficient 50 ppm of span/˚C 50 ppm of span/˚C 50 ppm of span/˚

Table 3-24. QAM Output Demand Current

Parameter G02, 04 G03 G05, 06

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Page 152: Ovation Q Line

3-6. QAM

s,es

tial

Clock Timing

Manual Clock 1

This clock is used for the PRIORITY RAISE and PRIORITY LOWER commandproviding linear operation. This clock provides full scale output travel (span) timof from 18 to 490 seconds (30 seconds standard).

Manual Clock 2

This clock is used for the RAISE and LOWER commands, providing exponenoperation. The characteristics of this clock are as follows:

Table 3-25. QAM J3 Connector Pin Assignments

Pin Number Signal Name

1 Unused

2 VDEM+**

3* VDEM−**

4* VSHLD

5 Unused

6 IDEM+ ***

7* IDEM− ***

8* ISHLD

9 Unused

Notes* These pins are connected to SystemCommon.** These are RIM output signals.*** These are RIF output signals.

9 8 7 6

12345PRINTEDCIRCUITBOARD

M410 CONNECTOR

M0-0053 3-86 5/99Westinghouse Proprietary Class 2C

Page 153: Ovation Q Line

3-6. QAM

nds

vel

Where the frequency of the Priority Linear Clock is fl (140 Hz standard). Time (T)is selected by a plug-in resistor and ranges from 0.2 to 2.0 seconds (0.8 secostandard).

Setpoint Clock

This clock is used for SETPOINT INCREASE and SETPOINT DECREASEcommands, providing linear operation. This clock provides full scale output tratimes of 35 to 980 seconds (90 seconds standard).

Time Frequency

0 to 1/2 T fl/64

1/2 T to 1-1/2 T fl/32

1-1/2 T to 2-1/2 T fl/16

2-1/2 T to 3-1/2 T fl/8

3-1/2 T to 4-1/2 T fl/4

4-1/2 T to 5-1/2 T fl/2

5-1/2 T to 6-1/2 T fl

6-1/2 T to Infinite 2fl

5/99 3-87 M0-0053Westinghouse Proprietary Class 2C

Page 154: Ovation Q Line

3-6. QAM

vary

DIOB Data Format

The DIOB data format is shown inTable 3-26.Table 3-27 gives analog values forsome of the hex codes of the DIOB data field. These DIOB data hex codes mayfrom X’000’ to X’FFF’

Table 3-26. QAM DIOB Data Format

Type ofOperation

CommandWord

Data-DIR UADD0 HI- LO

DIOBData Word

Write

Write*

Read

Read

AutomaticDemand/Control

Setpoint/Control

AutomaticDemand/Control

Setpoint/Status

00

00

11

11

00

11

00

11

10

10

10

10

Where:K= KEEP ALIVE & reset timer when 1R = REJECT to MANUAL when 1P = POWER OK when 1M = MANUAL MODE =1, AUTO = 0A = ALIVE when 1MSB = Most Significant BitLSB = Least Significant Bit

* = Disable by changing field jumper.

UDAT Bits 7 6 5 4 3 2 1 0

Byte 1

Byte 2

Byte 1

Byte 2

Byte 1

Byte 2

Byte 1

Byte 2

MSB

MSB

MSB

MSB

LSB

LSB

LSB

LSB

Unused

Unused

R K

R K

P M R A

P M R A

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Page 155: Ovation Q Line

3-6. QAM

usttheords.

fenarying

Software Parameters

Due to the double DIOB cycle requirements for QAM card applications, care mbe taken in programming the DIOB controller. Two DIOB transfers to or from QAM card must be successive, in order to transfer the required 12-bit data w

Demand or Setpoint Outputs

The QAM card must be written to in the proper sequence. The normal order oDIOB transactions during a write to the QAM is to first write the Low Byte and thwrite the High Byte, during a successive DIOB cycle. However, it is not necessto send the High Byte to the QAM within any specific amount of time after sendthe Low Byte.

Note

The Low Byte cannot be changed at theUp/Down counter without also sending theHigh Byte. The Low Byte is received but isnot loaded into the appropriate Up/Downcounter (Demand or Setpoint) until thecorresponding High Byte is also received.

Table 3-27. QAM Analog Values versus Hex Codes

HEX

Demand/Setpoint

0-10.000 VSetpoint

1-5.000 VDemand

4 - 20.000 mADemand

10- 50.000 mADemand

0 - 180.00 mA

000 0.000 V 1.000 V 4.000 mA 10.000 mA 0.000 mA

001 2.442 mV 1.001 V 4.004 mA 10.010 mA 0.044 mA

200 1.250 V 1.500 V 6.000 mA 15.001 mA 22.505 mA

400 2.501 V 2.000 V 8.001 mA 20.002 mA 45.011 mA

800 5.001V 3.000 V 12.002 mA 30.005 mA 90.022 mA

C00 7.502 V 4.001 V 16.003 mA 40.007 mA 135.03 mA

E00 8.752 V 4.501 V 18.003 mA 45.009 mA 157.54 mA

FFE 9.998 V 4.999 V 19.996 mA 49.990 mA 179.96 mA

FFF 10.000 V 5.000 V 20.000 mA 50.000 mA 180.00 mA

5/99 3-89 M0-0053Westinghouse Proprietary Class 2C

Page 156: Ovation Q Line

3-6. QAM

Lit isbit Lowby

nd 0te

read thes.

tingher

Each time the Low Byte is written to the QAM card, the REJECT TO MANUAbit of this byte is latched and held on the QAM card. The latched state of this bmaintained by the QAM card until the next Low Byte is written. As a result, thisremains set, causing a continuous manual reject, until reset by a subsequentByte write. Additionally, the QAM card’s Reject to Manual latch may be reset the QAM RESET signal.

Unlike the REJECT TO MANUAL bit, the Low Byte’s KEEP ALIVE bit is notlatched and held. Therefore, it is not necessary to alternate this bit between 1 aon successive Low byte writes. A 1 state of the KEEP ALIVE bit on each Low bywrite keeps the QAM “alive”, providing these writes occur within the selectedWatchdog time-out period.

Demand or Setpoint Inputs

The QAM card must be read in the same sequence as it was written (Low Bytefirst and High Byte read second), during successive DIOB cycles. Again, as incase of a write, there can be a delay between reading the Low and High Byte

The appropriate up/down counter (Demand or Setpoint) is prevented from counduring and following each Low Byte read until a subsequent DIOB operation, otthan another Low Byte read, has taken place or a Watchdog time-out occurs.

Note

The DIOB controller should not beprogrammed for continuous QAM Low Bytereads of the demand with the Watchdog timerdisabled and no other DIOB activity. Thistype of programming would prevent manualmanipulation of the output demand.

M0-0053 3-90 5/99Westinghouse Proprietary Class 2C

Page 157: Ovation Q Line

3-6. QAM

andheing or

he

he an

ut onse

ornde the

3-6.4. Controls and Indicators

Automatic Mode

In the Automatic mode, the QAM card provides either a voltage or a current demoutput, which tracks the 12-bit demand signal output of the DIOB controller. Toperator or external device can prevent the output demand signal from changmore than 0.375 percent of span in one or both directions by using the RAISELOWER INHIBIT commands.

Additionally, while in the Automatic mode, the QAM card provides a voltageoutput which tracks the 12-bit setpoint signal output from the DIOB controller. Toperator can alter this signal via INCREASE or DECREASE SETPOINTcommands, which produce a constant rate of change in the setpoint signal. Toutput of the QAM card’s setpoint counter/register logic is in turn provided asinput to the DIOB controller.

Manual Mode

In the Manual mode, the QAM card increases or decreases the demand outpthe RAISE or LOWER signals from the M/A station. Exponential changes in thedemands are produced by a variable rate clock circuit. Commands to RAISE LOWER the demand may also be executed by using the PRIORITY RAISE aLOWER inputs. These commands reject the card to Manual mode and overridnormal directional commands. A linear clock is provided for these options,providing a constant rate of change in the demand output.

Figure 3-40. QAM Card Connections

DIOB BackplaneConnector To E/P

or I/P

J3

Power OKManual

AliveLED’s

J2

J1

Card EDGEConnector orM/A Station

5/99 3-91 M0-0053Westinghouse Proprietary Class 2C

Page 158: Ovation Q Line

3-6. QAM

is

from

The DIOB controller can monitor the output demand when the manual mode selected because the 12-bit demand counter/register is an input to the DIOBcontroller. This enables a bumpless transfer when the QAM card is switched Manual or Automatic mode.

The demand operation variations for the Manual mode are given inTable3-28 andTable 3-29.

Table 3-28. QAM Manual Mode Demand Operations (G03)

PriorityLower

PriorityRaise Lower Raise Action Clock Rate

ManualReject Jumpers

0 0 0 0 HOLD – No Don’t Care

0 1 0 1 RAISE LINEAR Yes Don’t Care

1 0 0 0 LOWER LINEAR Yes Don’t Care

1 1 0 0 HOLD – Yes Don’t Care

1 1 1 1 LOWER LINEAR Yes J Installed

X X 1 X Reset Card:Setpoint = 0

Yes H Removed

Where:0 = Inactive Signal1 = Active Signal

Table 3-29. QAM Manual Mode Demand Operations (G01, 2, 4, 5, 6)

PriorityLower

PriorityRaise Lower Raise Action Clock Rate

ManualReject Jumpers

0 0 0 0 HOLD – No Don’t Care

0 0 0 1 RAISE EXPONENTIAL Yes* Don’t Care

0 0 1 0 LOWER EXPONENTIAL Yes* Don’t Care

0 0 1 1 HOLD – No G Installed

0 0 1 1 LOWER EXPONENTIAL Yes* G Removed

0 1 0 0 RAISE LINEAR Yes Don’t Care

0 1 0 1 RAISE LINEAR Yes Don’t Care

0 1 1 0 RAISE LINEAR Yes Don’t Care

0 1 1 1 RAISE LINEAR Yes Don’t Care

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3-6. QAM

ichrd.

cardr the

Watchdog Timer

The QAM card must be periodically updated via the keep-alive bit (DIOBcontroller) to maintain selection of the Automatic mode. The period within whthe QAM card must be updated is selected by a 4-bit DIP switch on the QAM caIf this card is not updated before a timeout of the selected watchdog time, theautomatically reverts to the Manual mode. The available update period times fo4-bit Watchdog Timer switch settings are shown inTable 3-30.

1 0 0 0 LOWER LINEAR Yes Don’t Care

1 0 0 1 LOWER LINEAR Yes Don’t Care

1 0 1 0 LOWER LINEAR Yes Don’t Care

1 0 1 1 LOWER LINEAR Yes Don’t Care

1 1 0 0 HOLD – Yes H Installed

1 1 0 1 HOLD – Yes H Installed

1 1 1 0 HOLD – Yes H Installed

1 1 1 1 HOLD – Yes H Installed

1 1 0 0 LOWER LINEAR Yes H Removed

1 1 0 1 LOWER LINEAR Yes H Removed

1 1 1 0 LOWER LINEAR Yes H Removed

1 1 1 1 LOWER LINEAR Yes H Removed

Where:0 = Inactive Signal1 = Active Signal

* Manual Reject only if jumper F is installed, otherwise no manual reject occurs.

Table 3-30. QAM Watchdog Timer Switch Settings

Switch SegmentsUpdate Period Times

D C B A

0 0 0 0 62 msec. timeout

0 0 0 1 125 msec. timeout

0 0 1 0 250 msec. timeout

0 0 1 1 500 msec. timeout

Table 3-29. QAM Manual Mode Demand Operations (G01, 2, 4, 5, 6) (Cont’d)

PriorityLower

PriorityRaise Lower Raise Action Clock Rate

ManualReject Jumpers

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Page 160: Ovation Q Line

3-6. QAM

asIT

t

QAM Reset

The QAM card will reset under either of the two following conditions:

• When the+13 VDC input supply voltage drops below+9 VDC

• When the DIOB’s UNIT control is active.

A RESET causes the card to enter Manual Mode and the setpoint is defined 00016. The demand and Manual Mode operations will not be affected by the UNsignal, however, the demand will be set to 00016 whenever the +13 VDC inputvoltage drops somewhat below the +9VDC level.

With a Group 03 card, theLOWER signal from the M/A station will reset andprovide a zero setpoint within 5 msec of activating the lower signal. This resecauses the card to enter the Manual Mode. Because the UNIT signal is notconnected on a Group 03 card, a reset has no effect on the UNIT signal.

0 1 0 0 1 sec. timeout

0 1 0 1 2 sec. timeout

0 1 1 0 4 sec. timeout

0 1 1 1 8 sec. timeout

1 X X X no timeout

Where:0 = Open switch segment1 = Closed switch segmentX = Either open or closed.

All times have tolerance of+20 percent.

Table 3-30. QAM Watchdog Timer Switch Settings

Switch SegmentsUpdate Period Times

D C B A

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3-6. QAM

he

DIP

k

ff

Figure 3-41 illustrates the card components.

LED Indicators

The QAM card has three front edge LED’s which indicate:

Plug-In Resistors

The QAM card contains four plug-in resistors which determine the timing for tQAM clocks and timer. Each of these resistors is listed below.

• RW – Watchdog Timeout Period – value selected to control the range of theswitch selected Watchdog Timeout periods.

• RL – Linear Clock Frequency – value selected to determine the linear clocfrequency for demand operations (priority raise and lower). Refer toTable 3-31 for suggested resistor values and corresponding clock rates.

Figure 3-41. QAM Card Components

PWR OK – lights when proper DIOB power is applied to card

MANUAL – lights when QAM card is in Manual mode; off duringAutomatic mode operation.

ALIVE – lights when Watchdog Timer is in timeout period; goes owhen timer’s timeout period expires, indicating that DIOBcontroller has failed to update the KEEP ALIVE bit withinselected period.

RE

RS

RL

SP ZeroPot

SP GainPot

DIPSwitch

RW

Jumpers

SpeedSelection

EFGHJK

DEM Gain

DEM Zero

LEDs

PWR OK

MANUALALIVE

Pot.

Pot.

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3-6. QAM

er).tes.

lock

• RE – Exponential Clock Frequency – value selected to determine theexponential clock frequency for demand operations (normal raise and lowRefer toTable3-32 for suggested resistor values and corresponding clock ra

• RS – Setpoint Clock Frequency – value selected to determine the linear cfrequency for setpoint operations (setpoint increase or decrease). Refer toTable 3-33 for suggested resistor values and corresponding clock rates.

Table 3-31. QAM RL Selected or Demand Linear Clock Frequency

RL Values Selected Frequency Full Scale Ramp Change/Minute

2 kΩ 230 Hz 18 seconds 340 percent

5 kΩ* 135 Hz 30 seconds 200 percent

10 kΩ 90 Hz 45 seconds 135 percent

20 kΩ 60 Hz 70 seconds 85 percent

50 kΩ 30 Hz 140 seconds 43 percent

100 kΩ 16 Hz 260 seconds 23 percent

200 kΩ 8.5 Hz 490 seconds 12 percent

* Standard Value

Table 3-32. QAM RE Selection of Demand Exponential Clock Frequency Sweep Rates

RE Values Clock Period Time Selected FrequencyFrequency Sweep

Period

100 kΩ 0.23 seconds 4.4 Hz 1.5 seconds

200 kΩ* 0.45 seconds 2.2 Hz 2.9 seconds

365 kΩ* 0.83 seconds 1.2 Hz 5.4 seconds

750 kΩ 2.0 seconds 0.5 Hz 13.0 seconds

* Standard Value

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3-6. QAM

ding

.

.

Plug-In Jumpers

The QAM card contains six plug-in jumpers for option selections.Table3-34 liststhe selected options of each jumper. An option is selected when its corresponjumper is inserted.

Table 3-33. QAM RS Selection of Setpoint Linear Clock Frequency

RS Values Selected Frequency Full Scale Ramp Change/Minute

2 kΩ 115 Hz 35 seconds 170 percent

5 kΩ 68 Hz 60 seconds 100 percent

10 kΩ* 45 Hz 90 seconds 67 percent

20 kΩ 30 Hz 140 seconds 43 percent

50 kΩ 15 Hz 280 seconds 21 percent

100 kΩ 8 Hz 515 seconds 12 percent

200 kΩ 4.3 Hz 980 seconds 6 percent

* Standard Value

Table 3-34. QAM Jumper Selection of Options

Jumper Selected Option

E The REJECT TO MANUAL bit from the DIOB controller switches the card toManual mode.

F* TheRAISE IN orLOWER IN inputs switch card to Manual mode.NoteSimultaneousRAISE IN orLOWER IN signals do not switch card to Manual modeunless jumper G is removed.

G* SimultaneousRAISEIN or LOWERIN signals cause output to hold instead of lower

H SimultaneousRAISE IN andPRIORITY LOWER signals cause the output to holdinstead of lower.

J The DIOB controller may set the 12-bit setpoint word.

K Absence of the cable to the MA station does not reject the card to Manual mode

* On Group 03 cards, jumpers F and G have no effect. Activation of theLOWER will alwayscause a card reset.

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3-6. QAM

g

nd

Test Points

The QAM card contains thirteen test points (TP1 through TP13) for monitorinQAM card option.Table 3-35 lists these test points.

Potentiometers

The QAM card contains four potentiometers (pots), on each for the demand asetpoint gain adjustments (D/A converter), and one each for the demand andsetpoint zero adjustments.Table 3-36 lists each pot and its related adjustment.

Table 3-35. QAM Test Points

Test Point Frequency

TP1 G01 – OUTPUT DEMAND

G02 to 06 – V/I Converter Input Voltage

TP2 G02 to 06 – V/I Output Voltage

TP3 SETPOINT

TP4 System Common

TP5 M/A OUTPUT DEMAND

TP6 VREF (+10 VDC)

TP7 DIOB Ground

TP8 CLEAR

TP9 + 12 VDC

TP10 + 15 VDC

TP11 + 15 VDC

TP12 + 15 VA

TP13 − 15 VA

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3-6. QAM

by.

s

f

s

DIP Switch

The QAM card contains a four segment DIP switch which is used to selectWatchdog timeout periods. The range of switch selected times is determinedplug-in resistor RW.Table 3-30 lists the switch settings and the timeout periods

Table 3-36. QAM Potentiometer Adjustments

Pot Adjustment

DEM ZERO(M128-1)

Adjusted to zero the Demand D/A Converter logic, for a demand of X000(seeTable 3-24).

DEM GAIN(H61-1)

Adjusted to set the amount of span for the Demand D/A Converter logic’analog output, for a demand count of XFFF (seeTable 3-24).

SP ZERO(M128-2)

Adjusted to zero the Setpoint D/A Converter logic, for a setpoint count oX000 (seeTable 3-24).

SP GAIN(H61-2)

Adjusted to set the amount of span for the Setpoint D/A Converter logic’analog output, for a setpoint count of XFA0 (seeTable 3-24).

5/99 3-99 M0-0053Westinghouse Proprietary Class 2C

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3-7. QAO

s an for

nalst out

3-7. QAO

Analog Output(Style 2840A21G01 through G08)

3-7.1. Description

Groups 01 through 08 are applicable for use in the CE MARK Certified System

The QAO card accepts four 12-bit digital signals via the DIOB and individuallyconverts the data to analog field outputs. Each two-wire output (plus shield) haisolated, digital-to-analog (D/A) converter. Several output ranges are providedunipolar or bipolar voltage outputs (seeFigure 3-42).

The QAO interfaces to the DIOB through a rear-edge connector. The DIOB sigat this interface are defined by DIOB standards. The analog outputs are broughto the front edge of the card.

Figure 3-42. QAO Block Diagram

Address Data

OutputDrivers

(VDC or mA)

OutputDrivers

(VDC or mA)

OutputDrivers

(VDC or mA)

OutputDrivers

(VDC or mA)

To Field Process

Bus Control and4 X 12 Bit Memory

Multiplexer withOptical Isolation

DAC DAC DAC DAC

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3-7. QAO

dge

tputthetal

ge

ply

temsendedper

ms of

Digital data from the DIOB is fed to a 4-word by 12-bit memory. The data isperiodically multiplexed to the appropriate point register and presented to theD/A converter. The resultant analog value is buffered and provided at the card efor transmission to the field process.

There are four points available on the QAO Card. Each point is a three-wire oucomprised of negative, positive, and shield connections. The shield is tied to negative side of the outputs. Each D/A converter (point) converts a 12-bit diginumber to a current or voltage field output. These outputs may be unipolar orbipolar. Eight QAO groups are available.

• G01 provides four, 0 to 20.475 mA current outputs. A 40 VDC supply voltais supplied by the QAO Card.

• G02 provides four, 0 to 10.2375 VDC analog outputs.

• G03 provides four analog outputs with a range of−10.24 to+10.235 VDC.

• G04 provides four analog outputs with a range of 0 to 5.1187 VDC.

• G05 provides four analog outputs with a range of−5.12 to+5.1175.

• G06 provides one analog output with a range of−10.24 to+10.235 VDC.

• G07 provides four, 0 to 20.475 mA current outputs. An external 40 VDC supis required.

• G08 provides one analog output with a range of−10.24 to+10.235 VDC with ahigh-speed update.

The QAO Card is a self-contained, analog-output card. Analog output subsysconsist of one or more QAO Cards and one Bus Controller; no other cards arrequired to perform the analog output functions. The subsystem may be expain increments of four points by adding QAO Cards (48 QAO Cards maximum DIOB controller). The QAO Card complies with DIOB interface designspecifications and may be used in a Q-crate assembly. Functional block diagrathe QAO are shown inFigure3-43 andFigure3-45. Point block diagrams are shownin Figure 3-44 andFigure 3-46.

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3-7. QAO

Block Diagrams

Figure 3-43. QAO Card Functional Block Diagram, 5-Level

Com

para

tor

12 X 4

Control

MemoryD

rive

Writ

e

Rea

dMulti-Plexer

Clear

Strobe

Point 1 (Clear, Strobe)

Point 2 (Clear, Strobe)

Point 3 (Clear, Strobe)

Serial Data(Same to all

Clock(Same to all

Read

Cho

pper

Point 0

Front ConnectorJumper Address

Con

trol

Add

ress

Dat

a

DIOB

Point 3

Point 2

Point 1

Point 0

four points)

four points)

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3-7. QAO

Figure 3-44. QAO Point Block Diagram, 5- Level

Clear

Pow

erS

uppl

y

Strobe

+

Latc

h

D/A

Con

vert

er

Shi

ft R

egis

ter

Clock

Serial Data

+

Current

Shield

+ Voltage

Shield

Process Output

− 40 VDC (G01 Only)

+ 15 VDC

+ 5 VDC

Opt

ical

Isol

atio

n

Analog Offsetof 1/2 Spanfor BipolarOutput

Buffer(Voltage OutputGroups Only)

Jumper To InvertMsb of BipolarData Groups

Jumper RangeSelect

V/I Converter(G01 and G07 Only)

1112 G07

G01−40 VDC

MSB

5/99 3-103 M0-0053Westinghouse Proprietary Class 2C

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3-7. QAO

Figure 3-45. QAO Card Functional Block Diagram, 6-Level and Later

Com

para

tor

Control

Driv

e

Multi-plexer

Clear

Strobe

Point 1 (Clear, Strobe)

Point 2 (Clear, Strobe)

Point 3 (Clear, Strobe)

Serial Data(Same to all

Clock(Same to all

Read

Point 0

Front ConnectorJumper Address

Add

ress

Dat

a

DIOB

Point 3

Point 2

Point 1

Point 0

four points)

four points)

Driv

er3

Driv

er2

Driv

er1

Driv

er0

Ch

0

Ch

2

Ch

1

Ch

3 Mul

tiple

xer

MSB (Bit 11)

+

Rea

d

Writ

e

LatchClear

Control

Osc.

Remove to invertMSB of bipolar data

Bits 0 - 10

12 X 4Memory

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3-7. QAO

3-7.2. Specifications

Output Capabilities

G01: 0 to 20.475 mA (internal supply)

G02: 0 to+10.2375 VDC

G03: −10.24 to+10.235 VDC

G04: 0 to+5.1187 VDC

G05: −5.12 to+5.1175 VDC

G06: −10.24+ 10.235 VDC (single channel)

G07: 0 to 20.475 mA (external supply)

G08: −10.24+ 10.235 VDC (single channel, high speed update)

Figure 3-46. QAO Point Block Diagram, 6-Level

λ

λ

λ

λ

DA

Con

vert

er

GainAdj.

Voltage Output

Current Output

+10 -10

Offset Adj.

RangeSelectResistor

LightBulb

+

-shield

Buffer

+-

+- -10V

VoltageOutput

CurrentOutput

10VRef

15V

Clear

Strobe

Clock

Serial Data

φ

Pow

erS

uppl

y

-40 (G01 Only)±15V+ 5 V

Process OutputSurge Protected

Offset Adj.+10 -10

+

-shield

- 40 VG01

G07

(OverloadProtection)

5/99 3-105 M0-0053Westinghouse Proprietary Class 2C

Page 172: Ovation Q Line

3-7. QAO

Output Loading

• Current Outputs (G01, 7): 0 to 1KΩ resistance

• Voltage Outputs (G02, 3, 4, 5, 6, 8): 0 to 20 mA Output Current with 500Ωminimum load resistance, short circuit protected.

Throughput

• G01 through G07: 1.4 to 7.4 msec digital delay

• G08: 0.5 to 1.2 msec digital delay

Note

G08 should not be written to again for 1.5 msec.

Resolution

12-bit resolution (including polarity in bipolar group)

Reference Accuracy (including polarity in bipolar groups)

+0.05 percent of SPAN (SPAN = 20.475 mA for G01, 10.2375 VDC for G02,20.475 VDC for G03, etc.)

Temperature Coefficient

• 40 ppm RMS of Span/°C for Voltage Outputs

• 50 ppm RMS of Span/°C for Current Outputs

Power Supply

• Primary: +12.4 VDC minimum,+13.0 VDC nominal,+13.1 VDC maximum

• Backup: 12.4 VDC minimum, 13.1 VDC maximum

• Current: 1.3 A maximum

Electrical Environment

IEEE surge withstand capability (except G08)

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3-7. QAO

Aup.

Common Mode Voltage: 500 VDC or peak AC (line frequency)

Data Output

The analog outputs result from DIOB digital data which is presented to the D/converters. The output values and output codes are listed below for each gro

G01

Note

Accuracy specifications do not apply below4 mA. Do not operate below 80µA.

G02

Input Data (Data received fromController WRITE to QAO) Output Value

000X See Note

001X See Note

010X 80µA

320X 4.000 mA

400X 5.120 mA

800X 10.240 mA

C00X 15.360 mA

FFEX 20.470 mA

FFFX 20.475 mA

X = Any digit

Input Data (Data received fromController WRITE to QAO) Output Value

000X 0 VDC

001X +2.50 mV

400X +2.5600 VDC

800X +5.1200 VDC

C00X +7.6800 VDC

FFEX +10.2350 VDC

FFFX +10.2375 VDC

X = Any digit

5/99 3-107 M0-0053Westinghouse Proprietary Class 2C

Page 174: Ovation Q Line

3-7. QAO

G03

G04

G05

Input Data (Data received fromController WRITE to QAO) Output Value

800X −10.2400 VDC

C00X −5.1200 VDC

FFFX -0.00500 VDC

000X 0.0000 VDC

001X +0.0050 VDC

400X +5.1200 VDC

7FFX +10.2350 VDC

X = Any digit

Input Data (Data received fromController WRITE to QAO) Output Value

000X 0 VDC

001X +1.2500 mV

400X +1.2800 VDC

800X +2.5600 VDC

C00X +3.8400 VDC

FFEX +5.1175 VDC

FFFX +5.1187 VDC

X = Any digit

Input Data (Data received fromController WRITE to QAO) Output Value

800X −5.1200 VDC

C00X −2.5600 VDC

FFFX −0.0025 VDC

000X 0.0000 VDC

001X +0.0025 VDC

400X +2.5600 VDC

7FFX +5.1175 VDC

X = Any digit

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3-7. QAO

G06

G07

Note

Accuracy specifications do not apply below4 mA. Do not operate below 80µA.

Input Data (Data received fromController WRITE to QAO) Output Value

800X −10.2400 VDC

C00X −5.1200 VDC

FFFX −0.0050 VDC

000X 0.0000 VDC

001X +0.0050 VDC

400X +5.1200 VDC

7FFX +10.2350 VDC

X = Any digit

Input Data (Data received fromController WRITE to QAO) Output Value

000X See Note

001X See Note

010X 80µA

320X 4.000 mA

400X 5.120 mA

800X 10.240 mA

C00X 15.360 mA

FFEX 20.470 mA

FFFX 20.475 mA

X = any digit

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3-7. QAO

ainstand

nd

nd

G08

Figure3-47 shows the output value curves. The input data codes are plotted agthe output voltage. This graph applies to bipolar voltage groups (G03, G05, G06G08).

Figure 3-48 shows the output value curves for unipolar current groups (G01 aG07). The input data codes are plotted against output current.

Figure 3-49 shows the output value curves for unipolar voltage groups (G02 aG04). The input data codes are plotted against output voltage.

Input Data (Data received fromController WRITE to QAO) Output Value

800X −10.2400 VDC

C00X −5.1200 VDC

FFFX −0.0050 VDC

000X 0.0000 VDC

001X +0.0050 VDC

400X +5.1200 VDC

7FFX +10.2350 VDC

X = Any digit

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3-7. QAO

Figure 3-47. QAO Bipolar Output Voltage Curves

Hexadecimal Value (Two’s Complement)

FFF 1000

E00

C00

A00

800

600

400

200

C18

830

800

−10.240 V−5.120 V

−10 −8 −6 −4 −2 0 +2 +4 +6 +8 +10 +10.235G03, G06

−5 −4 −3 −2 −1 0 +1 +2 +3 +4 +5 +5.127G05, G08

Bipolar Voltage (V)

7FF7D0

3E8

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3-7. QAO

Figure 3-48. QAO Unipolar Output Current Curves

Hexadecimal Value (Binary)

E00

C00

A00

800

600

400

200

20

FAO

0 4 8G01, G07

Unipolar Current (mA)

FFF

12 16 20.475

000

960

320

NOTE

Accuracy Specifications Do Not Apply in Shaded Area

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3-7. QAO

dge

d is

3-7.3. Card Addressing

Address Jumpers

The QAO card address is established by six jumpers on the top, front, card-econnector. The insertion of a jumper encodes a “1” on the address line.

3-7.4. Controls and Indicators

If the QAO Card is not periodically updated, the card resets. The update perioset by four dual-in-line (DIP) switches as given inTable 3-37. The QAO Cardcomponents are shown inFigure 3-50.

Figure 3-49. QAO Unipolar Output Voltage Curves

Hexadecimal Value (Binary)

E00

C00

A00

800

600

400

200

10

FAO

0 2 4G02

FFF

6 8 10.2375

000

7D0

50 1 2G04 3 4 5.1187

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3-7. QAO

Figure 3-50. QAO Card Components

UpdatePeriodSwitch

PowerLED

M0-0053 3-114 5/99Westinghouse Proprietary Class 2C

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3-7. QAO

puts

3-7.5. Field Connections

The analog outputs are brought out to the front edge of the card. The QAO outare three wire bundles, and use the same pinouts for all groups. The contactallocations are shown inTable 3-38.

Table 3-37. QAO Card Reset Switch Position (Update Period)

Dip Switch

Reset TimeA B C D

0 0 0 0 62 ms+ 20 percent

0 0 1 0 125 ms+ 20 percent

0 1 0 0 250 ms+ 20 percent

0 1 1 0 500 ms+ 20 percent

1 0 0 0 1 sec+ 20 percent

1 0 1 0 2 sec+ 20 percent

1 1 0 0 4 sec+ 20 percent

1 1 1 0 8 sec+ 20 percent

X X X 1 No time out, data latched (X = 0 or 1)

Table 3-38. QAO Analog Output Contact Allocations

Point Pin Out

Point 0 5A – (+ output)3A – (− output)3B – (shield)

Point 1 9A – (+ output)7A – (− output)7B – (shield)

Point 2 13A – (+ output)11A – (− output)11B – (shield)

Point 3 17A – (+ output)15A – (− output)15B – (shield)

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3-7. QAO

3-7.6. Installation Data Sheet

1 of 3

Figure 3-51. QAO Wiring Diagram

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

EDGE CONNECTOR

POINT 3

(+)

(S)

(−)

POINT 2

(+)

(S)

(−)

POINT 1

(+)

(S)

(−)

POINT 0

(+)

(S)

(−)

(+)

(SHIELD)

(−)

POINT 3

CUSTOMER CONNECTIONS

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 0

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

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Page 183: Ovation Q Line

3-7. QAO

For CE MARK Certified System

2 of 3

Figure 3-52. QAO CE MARK Wiring Diagram (Groups 1 & 7)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(-)

POINT 0

Note

QAO groups 1 and 7 must have the shield and returnconnected together and to earth ground at the B cabinet asshown.

5/99 3-117 M0-0053Westinghouse Proprietary Class 2C

Page 184: Ovation Q Line

3-7. QAO

For CE MARK Certified System

3 of 3

Figure 3-53. QAO CE MARK Wiring Diagram (Groups 2 through 6, & 8)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(-)

POINT 0

Note

QAO Groups 2 through 6 and Group 8 may havethe shield and return connected together and toearth ground in the field or at the B cabinet.

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Page 185: Ovation Q Line

3-8. QAV

tiontiple

3-8. QAV

Analog Input Point(Syle 7379A21G01 through G09 )

3-8.1. Description

Groups 01through G09 are applicable for use in the CE MARK Certified System

The QAV card converts an analog field signal to digital data (seeFigure3-54). (Fornew applications, a QAX card is recommended). The digital data is the summaof a frequency that has been counted for a time period. The time period is a mulof the power line frequency (50 or 60 Hz).

Figure 3-54. QAV Block Diagram

DIOBData Address Control

DataBufferRAM

Address

µC, Counterand Control

Circuits

TransformerIsolation

TransformerIsolation

Channel 1Voltage toFrequencyConverter

Channel 6Voltage toFrequencyConverter

Decoder

...

...

...(-)(+) SHD (-)(+) SHD

Six Sets of Analog Field Inputs

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Each QAV card contains six individually isolated voltage-to-frequency convertcircuits (channels). The output of each input circuit is processed by a commomicrocomputer and the resulting digital data is multiplexed to the DistributedInput/Output Bus (DIOB) as a 13-bit word.

Figure 3-55 shows a typical control system configuration using QAV cards. ThQTB card is necessary for applications where large variations of power linefrequency exist to obtain a high normal mode rejection. Up to 30 QAV cards (channels) can be used with one DIOB controller.

Cards equipped with the thermocouple temperature compensation feature uschannel 6 for the on-card temperature sensor. The channel is read every timecard performs an auto-calibration cycle. The on-card temperature sensor eliminthe need for external sensor boards, and ensures field temperature accuracy

The QAV card uses an electrical isolation circuit (transformer) to separate theanalog input from the digital counting circuits. The isolation circuit provides powfor each analog input channel in addition to precise timing from a stable frequewhich is generated on the digital side of the QAV card circuits.

Each analog input circuit contains circuitry for signal conditioning, biasing,auto-zero and gain correction, open thermocouple detection (not available onand G05 QAV cards) and a clocked voltage-to-frequency converter.

Offset and gain correction factors are calculated on a periodic basis by the QAVmicrocomputer. The frequency of the offset and gain calibration cycle is determby a constant which has been programmed into the memory of the systemcontroller.

Two known potentials on the analog section of the QAV card are used as standfor offset and gain calibrations. One standard is a 0 VDC (shorted input), whicused to determine the offset correction factor. The second calibrating potentia(gain) is derived from a separate, stable voltage reference which is setapproximately−150% of the maximum expected analog input value. The gaincorrection factor is compared to a 16-bit calibration constant which is programminto the memory of the system controller at the time of factory card calibration. Tcalibration constant is necessary because the QAV card has no mechanical adjdevices (such as potentiometers, and so on). This method yields a trimmer (or-less calibrating method.

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The QAV card microcomputer is programmed to “limit check” (reasonabilitycheck) the offset correction factor for each analog input channel. Failure of threasonability check causes bit 14 (offset over-range) of the output data for thachannel to be set to a logical zero. A failure on two or more channels causes b(IMOK bit) of the output data to be set to a logical zero which indicates card trouto the system controller.

Note

The two-channel failure feature is availableon QAV cards at levels 1QAV through 4QAV.

Bit 15 is also set to zero during the power-up routine of the QAV card. The QAmicrocomputer is reset at this time and conversion of data is begun when thecontrol is removed and the QAV card buffer memory is updated. Bit 15 is resetlogical 1 after a warm-up pause is completed. The length of the warm-up paudetermined by a programmed constant in the memory of the system controlle

Figure 3-55. QAV Typical Control System Using QAV Cards

DIOB

FIELD INPUTS

FIELD INPUTS

POWER LINEINPUTQTB

QAV #1

QAV #30

DIOBCONTROLLER

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• G01 and G071: −5 to +20 mVDC (−20 to+20 mVDC at reduced accuracy2);500Ω maximum source impedance.

• G02 and G081: −12.5 to+50 mVDC (−50 to+50 mVDC at reduced accuracy2);500Ω maximum source impedance.

• G03 and G091: −25 to+100 mVDC (−100 to+100 mVDC at reducedaccuracy2); 1 KΩ maximum source impedance.

• G04: −12.5 to+50 mVDC (−50 to+50 mVDC at reduced accuracy2); 500Ωmaximum source impedance (G04 is not available with the Open ThermocoDetection feature).

• G05: −25 to+100 mVDC (−100 to+100 mVDC at reduced accuracy2); 1 KΩmaximum source impedance (G05 is not available with the Open ThermocoDetection feature).

• G06: −12.5 to+50 mVDC (−50 to+50 mVDC at reduced accuracy2); 1 KΩmaximum source impedance.

1Level 8 QAV and later artwork support groups 1-3without “On-Card” thermocouple compensation.Groups 7-9 are identical to Level 6 QAV groups 1-3with “On-Card” thermocouple compensation. If “On-Card” thermocouple compensation is required, order groups 7-9 in place of groups 1-3 respectively.

2Reduced reference accuracy is+0.20 percent of the upper range value (+10 µV, +1/2 LSB at 99.7 percentconfidence.

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3-8.2. Features

Each QAV card has the following features:

• IEEE surge withstand capability

• Auto zero, auto gain correction

• Electrical isolation on all channels

• On-card digital memory (buffer)

• Open thermocouple detection (This feature is not available on G04 and GQAV cards.)

• Common mode rejection

• Normal mode rejection

• Automatic reasonability test (shorted input)

• Auto-conversion check

• Jumper selectable 50/60 Hz operation

• On-card thermocouple temperature compensation (Available on QAV cardlevel 6 QAV)

The QAV card is designed to be mounted in a standard Q-line card cage. Conneto the control system is made by a 34-pin rear-edge backplane connector whinterfaces the UIOB or DIOB and a 56-pin front-edge connector, which connectfield terminals.

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Block Diagram

A block diagram of one of the six analog sections of the QAV card is shown inFigure3-56.Figure3-57 shows a block diagram of the QAV digital circuits.Figure3-58 shows a flow diagram of the QAV card analog-to-digital conversion proc

Figure 3-56. QAV Analog Input Circuits Block Diagram

+12VX1

C1

+12V −12V

T1

R5

C2

D1

CLOCK

PSD (250 KHZ)FREQUENCY

INPUT(FI1-FI6)

MULTIPLEXERCONTROLLER

POWERSUPPLY

SYNCHRONOUSCOMPARATOR

CAPACITORDISCHARGE

LOW PASSFILTER CLAMP

ANALOGINPUT(VIN)

+

SHVOLTAGE

REFERENCE

PREAMPLIFIER

(MULTIPLEXERSOLIDSTATE

SWITCH)

(−)

(+)

I1

R4

R3

R2

VBIAS

R1

VREF

VIN

IREF1

- - -

--

- -

--

-

INTEGRATOR

--

--

-

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Figure 3-57. QAV Card Digital Circuits Block Diagram

DIOB

ANALOGPOWER

CONTROL

RAM LOADENABLE

ADDRESSDECODER

LEVEL SHIFTAND

BUFFER

BUFFER RAM LOADCONTROLLER

BUFFERRAM

ADDRESSJUMPERS

PSDPOWERSUPPLY

DRIVE-250KHZ

AOK

DOUT

UADD0-7DATA-DIR

USYNCHI-LO

DATA GATE

UDAT0-7DEV BUSY

CL P15 TADD0-2HI-LO

I/O

TUSYNC

P13

ADDRESS

RD0-7

SSWRCL

P24 to P27

BUFFERLATCH

ADDRESSLATCH

PROGRAMMEMORY

CONTROL

ADDRESS

I/O

TRESET +5VP14P10-12A0A1

COUNTERS(6)

5 VOLTREGULATOR

POWER UPAND

RESET

+12V(FI1-FI6)

LEN WD0-7BUS (DB0-7)

PSEN

P20

MICRO-COMPUTER

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3-8.3. Specifications

Inputs

Point Sampling Rate (samples/second):

Figure 3-58. QAV Analog-to-Digital Conversion Process Flowchart

RESET

INITIALIZE

READOFFSET

(COS)

READREF(COS)

[COS − CREF]

RESETCALIBRATION

(COUNTER)

CALCULATESLOPE

(A)

OUTPUTTO BUFF

RAM

TESTREASONABILITY

A(CX − COS)

LIMITOVERRANGE

(CX − COS)

READ*INPUT(CX)

TESTCALIBRATION

CTR

TESTWARM-UP

CTR

SET“IMOK”

SETFLAG(S)S

COSOFFSETCONVERSION = VBIASCONVERSION DATA

*TIME BASE CORRECTION

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Note

QAV cards with prefixes of 5 or greater are selectedfor 50 or 60 Hz operation by jumper. The samplingrate is 4 per second and the sample period is 0.2seconds for both 50 or 60 Hz operation.

• 4 at a power line frequency of 60 Hz

• 3.4 at a power line frequency of 50 Hz

Note

Once every 32 conversion, auto gain and auto zerocalibration are performed; 8 seconds apart in 60 Hzsystems, and 9.4 seconds apart in 50 Hz systems.

Resolution: 13-bits (includes polarity bit)

Input Channel Sample Period:

• 0.20 seconds at a power line frequency of 60 Hz

• 0.24 seconds at a power line frequency of 50 Hz

Normal Mode Voltage

• Surge: Meets IEEE/SWC test specifications without damage; however, theaccuracy of data is reduced during, and up to 10 secs. after the removal of the

• Continuous: An overrange of+120 VDC or 120 VAC rms at 50 or 60 Hz willnot damage the input channels; however, a sustained overrange can affecsubsequent data for several minutes following the removal of the overrangvoltage.

Normal Mode Rejection

• 60 dB at 50 or 60 Hz using QTB card line frequency tracking or at 50 or 60+0.5 percent without QTB card

• 30 dB at 50 Hz+5 percent or 60 Hz+5 percent without QTB card linefrequency tracking

Note

The input (peak-to-peak) AC voltage must notexceed 100 percent of the upper range value forspecified accuracy and normal mode rejection.

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Common Mode Voltage

• Surge: Meets IEEE/SWC test specifications without damage; however, theaccuracy of data is reduced during, and up to 10 seconds following the remof the surge.

• Continuous: A maximum of+500 VDC or peak AC can be applied withoutdamage.

Common Mode Rejection

• 120 dB at DC and power line frequency and its harmonics with QTB card frequency tracking or at 50 or 60 Hz+0.5 percent without QTB card

• 100 dB for nominal line frequency at+5 percent and harmonics without QTBcard line frequency tracking

Note

Common mode rejection does not apply if the peakAC value exceeds 200,000 % of upper range value.

Input Impedance

• 107 Ω/Volt

• 103 Ω in overload

Reference Accuracy (per SAMA Standard PMC 20)

• +0.10 percent of the upper range value (+10µV); +1/2 of the Least SignificantBit (LSB) at 99.7 percent confidence.

• Reference Conditions: 25°C + 1°C Ambient Temperature; 50 percent+2 percent of relative humidity; 0 V common mode; 0 V normal mode

Drift

• 0.002 percent per month (typical)

• 0.02 percent long term (typical)

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Power Requirements

Input Signal Requirements

• G01 and G071cards: −5 to+20 mVDC,−20 to+20 mVDC at reducedaccuracy2

• G02 and G081 cards: −12.5 to+50 mVDC,−50 to+50 mVDC at reducedaccuracy2

• G03 and G091 cards: −25 to+100 mVDC,−100 to+100 mVDC at reducedaccuracy2

• G04 cards:−12.5 to+50 mVDC,−50 to+50 mVDC at reduced accuracy2

• G05 cards:−25 to+100 mVDC,−100 to+100 mVDC at reduced accuracy2

• G06 cards:−12.5 to+50 mVDC,−50 to+50 mVDC at reduced accuracy2

Field signals are input to a standard Q series front-edge connector (seeFigure 3-59). The DIOB address and DIOB address protection jumpers are alocated in this connector. Each field signal input requires a plus, minus and spin.

Minimum Nominal Maximum

Primary Voltage: 12.4 VDC + 13.0 VDC 13.1 VDC

Optional Backup: 12.4 VDC -- 13.1 VDC

Nominal Maximum

Power Supply Current: 1.0 ADC 1.2 ADC

Power Used: 13.0 Watts 15.7 Watts

1Level 8 QAV and later artwork support groups 1-3without “On-Card” thermocouple compensation.Groups 7-9 are identical to Level 6 QAV groups 1-3with “On-Card” thermocouple compensation. If “On-Card” thermocouple compensation is required, order groups 7-9 in place of groups 1-3 respectively

2Reduced reference accuracy is+0.20 percent of the upper range value (+10 µV, +1/2 LSB at 99.7 percentconfidence.

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Output Signal Requirements

Output signal requirements are specified for DIOB requirements.

DIOB connection is made to the QAV card through the Q-card backplane conneto connector pins located on the rear-edge of the card (seeFigure 3-60).

Figure 3-59. QAV Card Front-Edge Connector Pin Assignments

1A

2A

3A

4A

5A

6A

7A

8A

9A

10A

11A

12A

13A

14A

15A

16A

17A

18A

19A

20A

21A

22A

23A

24A

25A

26A

27A

28A

1B

2B

3B

4B

5B

6B

7B

8B

9B

10B

11B

12B

13B

14B

15B

16B

17B

18B

19B

20B

21B

22B

23B

24B

25B

26B

27B

28B

SOLDERSIDE

COMPONENTSIDE

POINT 0 + INPUTPOINT 0 SHIELD

POINT 1 − INPUT

POINT 1 + INPUT

POINT 2 SHIELD

POINT 3 − INPUT

POINT 3 + INPUT

POINT 4 SHIELD

POINT 5 − INPUT

POINT 1 SHIELD

POINT 2 – INPUT

POINT 2 + INPUT

POINT 3 SHIELD

POINT4 – INPUT

POINT 4 + INPUT

POINT 5 SHIELD

POINT 5 + INPUT UNUSED

DIOB ADDRESS PROTECTION GROUND DIOB ADDRESS PROTECTION

UNUSED

UNUSED

UNUSED

UNUSED

ADDRESS LINE A3 GROUND

ADDRESS LINE A4 GROUND

ADDRESS LINE A5 GROUND

ADDRESS LINE A6 GROUND

ADDRESS LINE A7 GROUND

ADDRESS LINE A3

ADDRESS LINE A4

ADDRESS LINE A5

ADDRESS LINE A6

ADDRESS LINE A7

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

POINT 0 – INPUT SIGNAL

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

JUMPER MUST BE IN PLACE FORPROPER CARD OPERATION

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3-8.4. Card Addressing and Data Output

Address Jumpers

The QAV card address is established by five jumper fixtures which are locatethe front-edge connector. The insertion of a jumper encodes a “1” on the seleaddress line (ADD3 through ADD7) which when matched by the DIOB addresignals selects the QAV card by the system controller.

Figure3-59 shows the pin configuration of the front-edge connector. The “B” pof the connector are located on the component side and the “A” pins are locatethe solder side of the card.

QAV card addresses are programmed in groups of eight addresses in order tmaintain the address recognition circuits at a minimum. However, cards equipwith the thermocouple temperature compensation feature use all eight addreAddress 7 provides the temperature data, and address 8 is used during cardcalibration.

Figure 3-60. QAV Card Rear-Edge Connector Pin Assignments

+V PRIMARY

+V BACKUP

GROUND

UADD1

UADD3

UADD5

UADD7

DATA-DIR

DATA-GATE

DEV-BUSY

UDAT1

UDAT3

UDAT5

UDAT7

UFLAG*

USYNC

GROUND

COMPONENT SIDE SOLDER SIDE

+V PRIMARY

+V BACKUP

GROUND

UADD0

UADD2

UADD4

UADD6

HI-LO

UNIT*

GROUND

UDAT0

UDAT2

UDAT4

UDAT6

GROUND

UCAL*

UCLOCK*

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

POWER

CARDADDRESSING

CONTROL

BIDIRECTIONALDATA BUS

CONTROL

* NOT USED ON QAV CARD

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The addressing method allows up to 30 QAV cards to be used which means thaanalog input channels can be provided (30 possibilities at a maximum of 6 chanper card yields 180 channels per DIOB controller).

Address protection is provided by a jumper insert on the front-edge connectopair (20A and 20B). This contact has been machined to be shorter than the ofront-edge contacts so that it disconnects before the other contacts when thecard-edge connector is removed from the QAV card.

Output Data

Figure3-61 shows a general, 16-bit, QAV card output data pattern format. The12 bits (0 through 11) are binary data obtained through a software routine in QAV card microcomputer circuit.

The actual binary data that is sent to the system controller over the DIOB iscalculated by the microcomputer using data from a precision voltage networkfrom an analog-to-digital converter circuit. Data from the precision voltage netwis used to adjust the converted analog input (digital data) for offset and gaincorrection before it is output to the DIOB as point data.

Bit 12 is an overrange bit and bit 13 is a sign bit. A logic one signal at bit 12indicates that the count data is in the positive overrange when bit 13 is at a logicand that the count data is in the negative range when bit 13 is a logical one. A logzero at bit 12 indicates that the count data is in the negative overrange when bis a logical one and in the positive range when bit 13 is a logical zero. A logical oat bit 13 indicates the count is in the negative range and a logical zero at bit 1indicates that the count is in the positive range.

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Bits 14 and 15 are flag bits. A logical one at bit 14 indicates that the offset facdata that was obtained during the auto-zero calibration microcomputer routinwithin reasonable limits and a logical zero indicates unreasonable auto-zero dalogical one at bit 15 (called IMOK bit) indicates that the hardware is operatingproperly (power is present, warm-up is complete, and the controller is operatinglogical zero at bit 15 indicates hardware trouble or that the offset factors fromauto-zero calibration are unreasonable on more than one input channel.

Note

Multiple channel offset errors will not setbit 15 on QAV cards with prefixes of 5 orgreater.

Figure 3-61. QAV Card Output Data Pattern Format

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OVERRANGE BIT

1 = COUNT IS IN POSITIVEOVERRANGE WHEN SIGN BIT13 = 0, AND IN NEGATIVERANGE WHEN SIGN BIT 13 = 1

SIGN BIT

1 = COUNT IS NEGATIVE

FLAG BIT SET BY QAV CARDMICROCOMPUTER

1 = OFFSET DATA OBTAINEDDURING AUTO CALIBRATIONIS WITHIN REASONABLELIMITS

FLAG BIT (SET BY MICROCOMPUTER)

1 = HARDWARE IS OPERATINGPROPERLY

BINARY DATA

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cardfore,

Table 3-39 shows the nomenclature and the hexadecimal ranges for the QAVoutput data. Note that bits 14 and 15 are set by QAV card microcomputer; therethe positive range to negative transitions occurs in 14 bits.

3-8.5. Controls and Indicators (Level 6 and earlier)

The (Level 6 and earlier) QAV components are shown inFigure 3-62.

Light Emitting Diodes (LED)

The QAV card has one LED which is used to indicate power “on”.

Table 3-39. QAV Card Output Data Ranges

Data Classification Output Data Hexadecimal Code

Zero Input C000

Positive Range C001 to CFFF

Positive Full Scale D000

Positive Overrange D001 to DFFF

Negative Overrange E001 to EFFF

Negative Full Scale F000

Negative Range F001 to FFFF

Out of Range Offset 8000 to BFFF

Card Hardware Trouble 0000 to 7FFF

Figure 3-62. QAV Card Components (Level 6 and earlier)

J1,J2

J3,J4

LED

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Jumpers

Table3-40 lists the jumper numbers, locations and functions of the jumpers usethe QAV card.

Table 3-40. QAV Card Jumpers, Locations and Functions (Level 6 and earlier)

Jumper Number Function(Jumper in Place)

J1 For future use

J2 ORs signal IMOK (P13) to W274-2 Inverter

J31,2 Installed for 50 Hz systems

J41,2 Installed for 60 Hz systems

J51 For future use

J63 For future use

1 Jumpers J3, J4 and J5 are not used on QAV cards with prefixes lower than 5.2 The QAV card operates on its own time base when jumpers J3 or J4 are not inserted.3 Jumper J6 is not shown on cards with prefixes lower than 5.

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3-8.6. Controls and Indicators (Level 8 and later)

Switches

The (Level 8 and later) QAV card uses a four-position DIP switch (seeFigure 3-63 for the location of the switch). The definitions of the switches arefollows:

Notes

Any other switch combination is not valid and the QAVcard will not operate.

The QAV also has several factory preset jumpers.Changing these jumpers will affect calibration,therefore, no changes are recommended.

Figure 3-63. QAV Card Components (Level 8 and later)

Table 3-41. QAV Jumper Configuration

Configuration SW1 SW2 SW3 SW4

50Hz operation X ON OFF X

60Hz operation X OFF ON X

No QTB1 X ON ON X

1The QTB card is necessary in installations where large variations of the power line frequeexist to provide for large normal mode rejection.

X = Reserved (Don’t Care)

LE1

LE2

43

21

SW

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upard

LEDs

The QAV card has two LED’s (seeFigure3-63). LE1 indicates that power is appliedto the board. LE2 is used during the initial calibration of the board.

For on-line applications, LE2 will illuminate for about 1/2 second during power-and will remain off thereafter. Should this LED remain on or flash, return the boto Westinghouse for repair.

Notes

Before returning the board for repair, check thefollowing:

1. Ensure that the DIOB power supplies are intolerance.

2. Ensure that the DIP switch is set according tothe valid configurations in the previous tables.

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Thermocouple Information

Table 3-42 shows the standard WDPF thermocouple coefficient definitions.Coefficients may also be user-defined. For additional information on selecting tcoefficients, refer to the CI record field discussion in“RecordTypesUser’sGuide”(U0-0131).

Table 3-42. QAV Thermocouple Coefficient Definitions (WDPF System)

Thermocouple Type Coefficients

B 70% Platinum+ 30% Rhodiumor94% Platinum+ 6% Rhodium427-1093°C800-2000°F

C0 = 0.3516470E+ 03C1 = 0.6138849E+ 03C2 = −0.1539774E+ 03

C3 = 0.3359373E+ 02C4 = −0.4051826E+ 01C5 = 0.2003933E+ 00

E Chromel/Constantan−18-982°C0-1800°F

C0 = 0.3167283E+ 02C1 = 0.3030628E+ 02C2 = −0.3344949E+ 00

C3 = 0.6849588E− 02C4 = −0.6975349E− 04C5 = 0.2923653E− 06

J Iron/Constantan−96-760°C−140-1400°F

C0 = 0.3112531E+ 02C1 = 0.3607027E+ 02C2 = −0.4288617E+ 00

C3 = 0.2261382E− 01C4 = −0.5174379E− 03C5 = 0.3972783E− 05

K Chromel/Alumel−18-1093°C0-2000°F

(The upper range may be extended to2500 with less accuracy)

C0 = 0.3034473E+ 02C1 = 0.4403191E+ 02C2 = 0.1615839E+ 00

C3 = −0.1616257E− 01C4 = 0.4401109E− 03C5 = −0.3599650E− 05

R Platinum+ 13% Rhodium260-1093°C500-2000°F

C0 = 0.8362848E+ 02C1 = 0.2273716E+ 03C2 = −0.1248286E+ 02

C3 = 0.1206254E+ 01C4 = −0.7422128E− 01C5 = 0.1899300E− 02

S Platinum+ 10% Rhodium399-1093°C750-2000°F

C0 = 0.1180344E+ 03C1 = 0.1985918E+ 03C2 = −0.1973096E− 01

C3 = −0.5009329E+ 00C4 = 0.4110488E− 01C5 = −0.1155794E− 02

T Copper/Constantan46-399°C−50-750°F

C0 = 0.3189224E+ 02C1 = 0.4669328E+ 02C2 = −0.1325739E+ 01

C3 = 0.6962067E− 01C4 = −0.2327808E− 02C5 = 0.3330646E− 04

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When selecting a Q-card or Ovation I/O module for a thermocouple, you neeselect the proper card/group number to ensure an accurate reading. The informshown below provides the millivolt (MV) to temperature range for 20, 50, and 1mv cards.

This range limitation exists for Ovation I/O modules 1C31113G01/1C31116G1C31113G02/1C31116G04, and 1C31113G03/1C31116G04 as well as Q-LinI/O cards: QAI, QAV, and QAX.

Note that for a low millivolt reading, you could use a G01, G02 or G03 card, bbetter accuracy is obtained by using a G01, the group that provides a better fitnot use lower millivolt cards for the higher temperature (millivolt) readings.

The coefficients listed inTable 3-42 are the recommended coefficients for theranges shown for WDPF systems.

The coefficients listed inTable 3-43 are the recommended coefficients for theranges shown for Ovation systems.

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Table 3-43. QAV Thermocouple Coefficient Definitions (Ovation System)

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

B or TB 400 to 1100 Degrees C800 to 2000 Degrees F

0.000 to 13.814 (0 to 1820)0.006 to 13.814 (0 to 3308)

20 mv card20 mv card

FahrenheitCOEF_1 = 3.5164700E+02COEF_2 = 6.1388490E+05COEF_3 = -1.5397740E+08COEF_4 = 3.3593730E+10COEF_5 = -4.0518260E+12COEF_6 = 2.0039330E+14

COEF_7 = -2.0E-06COEF_8 = 0.0

CentigradeCOEF_1 = 1.7758167E+02COEF_2 = 3.4104717E+05COEF_3 = -8.5543000E+07COEF_4 = -8.5543000E+07COEF_5 = -8.5543000E+07COEF_6 = 1.1132961E+14

COEF_7 = -2.0E-06COEF_8 = 0.0

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

E or TE -18 to 286 Degrees C 0 to 550 Degrees F-18 to 661 Degrees C 0 to 1200 Degrees F-18 to 1000 Degrees C 0 to 1832 Degrees F

-9.835 to 19.945 (-270 to 286)-9.835 to 19.945 (-450 to 548)-9.835 to 49.992 (-270 to 661)-9.835 to 49.956 (-450 to 1221)-9.835 to 76.358 (-270 to 1000)-9.835 to 76.358 (-450 to 1832)

20 mv card20 mv card50 mv card50 mv card100 mv card100 mv card

FahrenheitCOEF_1 = 3.1672830E+01COEF_2 = 3.0306280E+04COEF_3 = -3.3449490E+05COEF_4 = 6.8495880E+06COEF_5 = -6.9753490E+07COEF_6 = 2.923653E0+08

COEF_7 = -1.0939E-03COEF_8 = 3.365E-05

CentigradeCOEF_1 = -1.8176111E-01COEF_2 = 1.6836822E+04COEF_3 = -1.8583050E+05COEF_4 = 3.8053267E+06COEF_5 = -3.8751939E+07COEF_6 = 1.6242517E+08

COEF_7 = -1.71E-05COEF_8 = 6.057E-05

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3-8. QAV

J or TJ -18 to 365 Degrees C-140 to 700 Degrees F-18 to 760 Degrees C-140 to 1400 Degrees F

-8.096 to 19.971 (-210 to 366)-8.137 to 19.977 (-350 to 691)-8.096 to 42.922 (-210 to 760)-8.137 to 42.922 (-350 to 1400)

20 mv card20 mv card50 mv card50 mv card

FahrenheitCOEF_1 = 3.112531E+01COEF_2 = 3.6070270E+04COEF_3 = -4.2886170E+05COEF_4 = 2.2613820E+07COEF_5 =-5.1743790E+08COEF_6 = 3.9727830E+09

COEF_7 =-9.256E-04COEF_8 = 2.862E-05

CentigradeCOEF_1 = -4.8593889E-01COEF_2 = 2.0039039E+04COEF_3 = -2.3825650E+05COEF_4 = 1.2563233E+07COEF_5 = -2.8746550E+08COEF_6 = 2.2071017E+09

COEF_7 = -9.76E-06COEF_8 = 5.1516E-05

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

K or TK -18 to 480 Degrees C 0 to 900 Degrees F-18 to 1230 Degrees C 0 to 2250 Degrees F-18 to 1370 Degrees C 0 to 2500 Degrees F

-6.458 to 19.959 (-270 to 484) 6.456 to 19.978 (-450 to 904) 6.458 to 49.988 (-270 to 1232) 6.456 to 49.996 (-450 to 2250)

-6.458 to 54.875 (-270 to 1372)-6.456 to 54.845 (-450 to 2500)

20 mv card20 mv card50 mv card50 mv card100 mv card100 mv card

FahrenheitCOEF_1 = 3.0344730E+01COEF_2 = 4.4031910E+04COEF_3 = 1.615839E+05COEF_4 = -1.616257E+07COEF_5 = 4.4011090E+08COEF_6 = -3.599650E+09

COEF_7 = -7.259E-04COEF_8 = 2.243E-05

CentigradeCOEF_1 = -9.1959444E-01COEF_2 = 2.4462172E+04COEF_3 = 8.9768833E+04COEF_4 = -8.9792056E+06COEF_5 = 2.4450606E+08COEF_6 =- 1.9998056E+09

COEF_7 = -8.14E-06COEF_8 = 4.0374E-05

Table 3-43. QAV Thermocouple Coefficient Definitions (Ovation System) (Cont’d)

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

5/99 3-141 M0-0053Westinghouse Proprietary Class 2C

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3-8. QAV

R or TR 260 to 1100 Degrees C500 to 2000 Degrees F

0.000 to 19.998 (0 to 1684)0.089 to 19.997 (0 to 3063)

20 mv card20 mv card

FahrenheitCOEF_1 = 8.3628480E+01COEF_2 = 2.2737160E+05COEF_3 = -1.2482860E+07COEF_4 = 1.2062540E+09COEF_5 = -7.4221280E+10COEF_6 = 1.89930000E+12

COEF_7 =-1.084E-04COEF_8 = 3.24E-06

CentigradeCOEF_1 = 2.8682489E+01COEF_2 = 1.2631756E+05COEF_3 = -6.9349222E+06COEF_4 = 6.7014111E+08COEF_5 = -4.1234044E+10COEF_6 = 1.0551667E+12

COEF_7 = 4.72E-06COEF_8 = 5.832E-06

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

S or TS 400 to 1100 Degrees C 750 to 2000 Degrees F

0.000 to 18.698 (0 to 1768)-0.092 to 18.696 (0 to 3214)

20 mv card20 mv card

FahrenheitCOEF_1 = 1.1803440E+02COEF_2 = 1.9859180E+05COEF_3 = -1.9730960E+04COEF_4 = -5.0093290E+08COEF_5 = 4.1104880E+10COEF_6 = -1.1557940E+12

COEF_7 = -1.0847E-04COEF_8 = 3.26E-06

CentigradeCOEF_1 = 4.7796889E+01COEF_2 = 1.1032878E+05COEF_3 = -1.0961644E+04COEF_4 = -2.7829606E+08COEF_5 = 2.2836044E+10COEF_6 = -6.4210778E+11

COEF_7 = -4.15E-06COEF_8 = 5.868E-06

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

T or TT -46 to 400 Degrees C -50 to 750 Degrees F

-6.258 to 19.945 (-270 to 385)-6.254 to 19.979 (-450 to 726)

20 mv card20 mv card

FahrenheitCOEF_1 = 3.1892240E+01COEF_2 = 4.6693280E+04COEF_3 = -1.3257390E+06COEF_4 = 6.9620670E+07COEF_5 = -2.3278080E+09COEF_6 = 3.3306460E+10

COEF_7 = -7.3333E-04COEF_8 = 2.243E-05

CentigradeCOEF_1 =-5.9866667E+02COEF_2 = 2.5940711E+04COEF_3 = -7.3652167E+05COEF_4 = 3.8678150E+-7COEF_5 = -1.2932267E+09COEF_6 = 1.8503589E+10

COEF_7 = -1.55700E-05COEF_8 = 4.0374E-05

Table 3-43. QAV Thermocouple Coefficient Definitions (Ovation System) (Cont’d)

ThermocoupleType

Standard TemperatureRange

Actual rangein MV / TEMP

Best Fit

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3-8. QAV

holeown for

3-8.7. Installation Data Sheet

1 of 3

Installation Notes: QAV Groups 1 through 5 (Refer to Figure 3-64)

1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the located near the shield terminal on Terminal Block A. Then add two jumpers as shbelow. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilledthis purpose.

Figure 3-64. QAV Wiring Diagram (QAV Groups 1 through 5)

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

EDGE CONNECTOR

(+)

(SHIELD)

(−)

POINT 5

PLANT

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

#8-32 SCREW

POINT 4

(+)

(SHIELD)

(−)

20B

20A

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 0

(+)

(SHIELD)

(−)

POINT 5

(+)

(SHIELD)

(−)

(+)

(SHIELD)

(−)

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 4

POINT 0TRANSDUCER

(+)

(−)

GROUND

REQUIRED ENABLE JUMPER

NOTE: THISDRAWING ISFOR PLANTGROUNDEDTRANSDUCERS.

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3-8. QAV

2. If inputs are to be grounded at the signal source, ground both the (−) side of the signaland the cable shield as shown below.

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

#6 SCREW

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

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3-8. QAV

holeown for

Installation Data Sheet

2 of 3

Installation Notes (Refer to Figure 3-65):

1. If inputs are to be grounded at the system end, insert a #6 screw and nut in the located near the shield terminal on Terminal Block A. Then add two jumpers as shbelow. Six holes, located next to terminals 2, 5, 8, 11, 14, & 17, have been drilledthis purpose.

Figure 3-65. Wiring Diagram, QAV to TSC Card

Edge Connector

Point5

Point4

Point3

Point2

Point1

Point0

(+)Shield

(-)

(+)

Shield(-)

(+)

Shield(-)

(+)

Shield

(-)

(+)

Shield

(-)

(+)

Shield(-)

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

Note: This drawing is for plant grounded transducers.

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

S1

(-)1

(+)1

S2

(-)2

(+)2

S4

(-)4

(+)4

S6

(-)6

(+)6

S5

(-)5

(+)5

S3

(-)3

(+)3

S4

(-)4

(+)4

S6

(-)6

(+)6

S5

(-)5

(+)5

S3

(-)3

(+)3

S1

(-)1

(+)1

S2

(-)2

(+)2

Point5

Point4

Point3

Point2

Point1

Point0

RequiredEnable Jumper

Terminal Block#8-32 Screw

UIOB/DIOB13 V Power Supply

C +

TB3

TB1orTB2

TB1orTB2

2 1

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

AA

TSC Card

Terminal Block#6-32 Screw

Card

5/99 3-145 M0-0053Westinghouse Proprietary Class 2C

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3-8. QAV

2. If inputs are to be grounded at the signal source, ground both the (−) side of the signaland the cable shield as shown below.

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

#6 SCREW

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

M0-0053 3-146 5/99Westinghouse Proprietary Class 2C

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3-8. QAV

For CE MARK Certified System

3 of 3

Figure 3-66. QAV CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

POINT 0TRANSDUCER

(+)

(−)

PLANT

POINT 4

(+)

(SHIELD)

(−)

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 0

(+)

(SHIELD)

(−)

POINT 5

(+)

(SHIELD)

(−)

GROUND

POINT 4

TRANSDUCER

(+)

(−)

Note

The QAV inputs may be grounded in the field orat the B cabinet as shown.

5/99 3-147 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

eatais a

3-9. QAW

Analog High Level Input Point(Style 7379A31G01 through G06)

3-9.1. Description

Groups 01through G06 are applicable for use in the CE MARK Certified System

The QAW card is designed to convert an analog field signal to digital data (seFigure3-67). (For new applications, a QAX card is recommended). The digital dis the summation of a frequency that has been counted for a time period whichmultiple of the power line frequency (50 or 60 Hz).

Figure 3-67. QAW Block Diagram

DataBufferRAM

Address

µC, Counterand Control

Circuits

TransformerIsolation

TransformerIsolation

Channel 1Voltage toFrequencyConverter

Channel 6Voltage toFrequencyConverter

Decoder

...

...

...(-)(+) SHD (-)(+) SHD

Six Sets of Analog Field Inputs

DIOBData Address Control

M0-0053 3-148 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

tern

he

80

eerncy

pply

AW

e

ards isl

gainedhe

mer

et

it 15ble

Each QAW card contains six individually isolated voltage-to-frequency convercircuits (channels). The output of each input circuit is processed by a commomicrocomputer and the resulting digital data is multiplexed to the DistributedInput/Output Bus (DIOB) as a 13-bit word.

Figure 3-68 shows a typical control system configuration using QAW cards. TQTB card is necessary for applications where large variations of power linefrequency exist, to obtain a high normal mode rejection. Up to 30 QAW cards (1channels) can be used with one DIOB controller.

The QAW card uses an electrical isolation circuit (transformer) to separate thanalog input from the digital counting circuits. The isolation circuit provides powfor each analog input channel in addition to precise timing from a stable frequewhich is generated on the digital side of the QAW card circuits.

Only card Group 5 provides an on-board current loop power supply. By usingGroup 5 cards for current transducers requiring 4-20 mA, a separate power suis not needed. On a Level 7 or earlier QAW, the power supply is activated byinstalling jumper number 6. On a Level 9 or later QAW, the power supply isactivated by setting jumpers 7 - 17 to the 2-3 position.

Each analog input circuit contains circuitry for signal conditioning, biasing,auto-zero and gain correction, and a clocked voltage-to-frequency converter.

Offset and gain correction factors are calculated on a periodic basis by the Qcard microcomputer. The frequency of the offset and gain calibration cycle isdetermined by a constant which has been programmed into the memory of thsystem controller.

Two known potentials on the analog section of the QAW card are used as standfor offset and gain calibration. One standard is a 0 VDC (shorted input), whichused to determine the offset correction factor. The second calibrating potentia(gain) is derived from a separate, stable voltage reference which is set toapproximately 100 percent of the maximum expected analog input value. Thecorrection factor is compared to a 16-bit calibration constant which is programminto the memory of the system controller at the time of factory card calibration. Tcalibration constant is necessary because the QAW card has no mechanicaladjusting devices (such as potentiometers, and so on). This method yields a trim(or pot) -less calibrating method.

The QAW card microcomputer is programmed to “limit check” (reasonabilitycheck) the offset correction factor for each analog input channel. Failure of threasonability check causes bit 14 (offset over-range) of the output data for thachannel to be set to a logical zero. A failure on two or more channels causes b(IMOK bit) of the output data to be set to a logical zero which indicates card trouto the system controller.

5/99 3-149 M0-0053Westinghouse Proprietary Class 2C

Page 216: Ovation Q Line

3-9. QAW

ontrolafter a

um

Note

The two-channel failure feature is availableon QAW card with prefixes of 1 and 2.

Bit 15 is also set to zero during the power-up routine of the QAW card. The QAWmicrocomputer is reset at this time and conversion of data is begun when the reset cis removed and the QAW card buffer memory is updated. Bit 15 is reset to a logical 1a warm-up pause is completed. The length of the warm-up pause is determined byconstant which is programmed into the memory of the system controller.

3-9.2. Features

The QAW card is available in six design groups (G01 through G06) toaccommodate a variety of analog input voltages. The group numbers, maximsource impedance, and input voltage range are as follows:

• G01: 0 to+1 VDC 1 KΩ maximum source impedance.

• G02: 0 to+5 VDC 5 KΩ maximum source impedance.

• G03: 0 to+10 VDC; 10 KΩ maximum source impedance.

• G04: 0 to+20 mA

Figure 3-68. QAW Typical Control System Using QAW Cards

DIOB

FIELD INPUTS

FIELD INPUTS

POWER LINEQTB

QAW NO. 1

QAW NO. 30

~~

DIOBCONTROLLER

INPUT

M0-0053 3-150 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

ich

tal

• G05: 0 to+20 mA, on-board current loop power supply

• G06: 0 to+50 mA

Each QAW card has the following features:

• IEEE surge withstand capability

• Auto zero, auto gain correction

• Electrical isolation on all channels

• On-card digital memory (buffer)

• Common mode rejection

• Normal mode rejection

• Automatic reasonability test (shorted input)

• Auto-conversion check

• Jumper selectable 50/60 Hz operation

• On-board current loop power supply (G05 only)

The QAW card is designed to be mounted in a standard Q-line card cage.Connection to the control system is made by a 34-pin rear-edge backplaneconnector which interfaces to the DIOB, and a 56-pin front-edge connector, whconnects to field terminals.

3-9.3. Specifications

Figure 3-69 andFigure 3-70 show block diagrams of the QAW analog and digicircuits.

Inputs

Point Sampling Rate (samples/second):

Note

QAW cards with prefixes of 3 or greater areselected for 50 or 60 Hz operation by jumper.The sampling rate is 4 per second and thesample period is 0.2 seconds for both 50 or60 Hz operation.

• 4 at a power line frequency of 60 Hz

• 3.4 at a power line frequency of 50 Hz

5/99 3-151 M0-0053Westinghouse Proprietary Class 2C

Page 218: Ovation Q Line

3-9. QAW

Note

Once every 32 conversions, auto gain andauto zero calibration are performed;8 seconds apart in 60 Hz systems, and9.4 seconds apart in 50 Hz systems.

Resolution: 13-bits (includes polarity bit)

Input Channel Sample Period:

• 0.20 seconds at a power line frequency of 60 Hz

• 0.24 seconds at a power line frequency of 50 Hz

M0-0053 3-152 5/99Westinghouse Proprietary Class 2C

Page 219: Ovation Q Line

3-9. QAW

Figure 3-69. QAW Analog Input Circuits Block Diagram

+12VX1

+15V

−15V

T1

R5

C2

D1

CLOCK

PSD (250 KHZ)FREQUENCY

INPUT(FI1-FI6)

MULTIPLEXERCONTROLLER

POWERSUPPLY

SYNCHRONOUSCOMPARATOR

CAPACITORDISCHARGE

LOW PASSFILTER CLAMP

+

SHVOLTAGE

REFERENCE

PREAMPLIFIER

(MULTIPLEXERSOLIDSTATE

SWITCH)

(−)

(+)

R4

R3

R2

V0

RD (FOR GROUPS

VREF

VIN

IREF1

- - -

--

- -

-

INTEGRATOR

18 V (NOM)

4, 5, & 6)

R1

SURGEPROTECTION

CURRENTLIMITER

18V(NORMAL)

GROUP 5ONLY

I1

-

--

--

-

5/99 3-153 M0-0053Westinghouse Proprietary Class 2C

Page 220: Ovation Q Line

3-9. QAW

f the

te

Normal Mode Voltage

• Surge: Meets IEEE/SWC test specifications without damage; however, theaccuracy of data is reduced during, and up to 10 seconds after the removal osurge.

• Continuous: An overrange of+120 VDC or 120 VAC rms at 50 or 60 Hz willnot damage the input channels; however, a sustained overrange can affecsubsequent data for several minutes following the removal of the overrangvoltage.

Figure 3-70. QAW Digital Circuits Block Diagram

DIOB

ANALOGPOWER

CONTROL

RAM LOADENABLE

ADDRESSDECODER

LEVEL SHIFTAND

BUFFER

BUFFER RAM LOADCONTROLLER

BUFFERRAM

ADDRESSJUMPERS

PSDPOWERSUPPLY

DRIVE-250KHZ

AOK

DOUT

UADD0-7DATA-DIR

USYNCHI-LO

DATA GATE

UDAT0-7DEV BUSY

CL P15 TADD0-2HI-LO

I/O

TUSYNC

P13

ADDRESS

RD0-7

SSWR

CLP24 to P27

BUFFERLATCH

ADDRESSLATCH

PROGRAMMEMORY

CONTROL

ADDRESS

I/O

TRESET +5VP14P10-12A0A1

COUNTERS(6)

5 VOLTREGULATOR

POWER UPAND

RESET

+12V(FI1-FI6)

LEN WD0-7BUS (DB0-7)

PSEN

P20

MICRO-COMPUTER

M0-0053 3-154 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

oval

line

Note

This specification does not apply to Group 4,5, and 6 cards.

Normal Mode Rejection

• 60 dB at 50 or 60 Hz using QTB card line frequency tracking

• 25 dB at 50 Hz+5 percent or 60 Hz+5 percent without QTB card linefrequency tracking

Note

The input (peak-to-peak) AC voltage mustnot exceed 50 percent of the upper rangevalue or 2V, for specified accuracy andnormal mode rejection.

Common Mode Voltage

• Surge: Meets IEEE/SWC test specifications without damage; however, theaccuracy of data is reduced during, and up to 10 seconds following the remof the surge.

• Continuous: A maximum of+500 VDC or peak AC can be applied withoutdamage.

Common Mode Rejection

• 120 dB at DC and power line frequency and its harmonics with QTB card frequency tracking

• 100 dB for nominal line frequency at+5 percent and harmonics without QTBcard line frequency tracking

Note

Common mode rejection does not apply if the peakAC value exceeds 200,000 percent of upper rangevalue.

5/99 3-155 M0-0053Westinghouse Proprietary Class 2C

Page 222: Ovation Q Line

3-9. QAW

Input Impedance

250Ω

Reference Accuracy (per SAMA Standard PMC 20)

• +0.10 percent of the upper range value (+10µV); +1/2 of the Least SignificantBit (LSB) at 99.7 percent confidence.

• Reference Conditions: 25°C + 1°C Ambient Temperature; 50 percent+2 percent of relative humidity; 0 V common mode; 0 V normal mode

Power Requirements

On-Board Power Supply for Each Channel (G05 Only)

• Current Limit: 60 mA

• Loop Resistance (excluding transducer): not greater than 60 ohms

• Worst Case VDC Output: 14 VDC (for a 7 level and earlier QAW), or20 VDC (for 9 level and later QAW) @ 20 mA (DIOB power supply @12.4 VDC)

• Minimum Transducer Operating Voltage: 12 VDC with no load

Input Signal Requirements

• G01 cards: 0 to+1 VDC

• G02 cards: 0 to+5 VDC

• G03 cards: 0 to+10 VDC

Minimum Nominal Maximum

Primary Voltage: 12.4 VDC + 13.0 VDC 13.1 VDC

Optional Backup: 12.4 VDC -- 13.1 VDC

Nominal Maximum

Power Supply Current: 1.0 ADC 1.2 ADC

Power Used: 13.0 Watts 15.7 Watts

M0-0053 3-156 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

ctor.

• G04 cards: 0 to+20 mA

• G05 cards: 0 to+20 mA (on-board current loop power supply)

• G06 cards: 0 to+50 mA

Field signals are input to a standard Q series front-edge connector. The DIOBaddress and DIOB address protection jumpers are also located in this conneEach field signal input requires a plus, minus and shield pin.

Output Signal Requirements

Output signal requirements are specified for DIOB requirements.

DIOB connection is made to the QAW card through the Q-card backplaneconnector to connector pins located on the rear-edge of the card (seeFigure 3-71).

Figure 3-71. QAW Card Rear-Edge Connector Pin Assignments

+V PRIMARY

+V BACKUP

GROUND

UADD1

UADD3

UADD5

UADD7

DATA-DIR

DATA-GATE

DEV-BUSY

UDAT1

UDAT3

UDAT5

UDAT7

UFLAG*

USYNC

GROUND

COMPONENT SIDE SOLDER SIDE

+V PRIMARY

+V BACKUP

GROUND

UADD0

UADD2

UADD4

UADD6

HI-LO

UNIT*

GROUND

UDAT0

UDAT2

UDAT4

UDAT6

GROUND

UCAL*

UCLOCK*

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

POWER

CARDADDRESSING

CONTROL

BIDIRECTIONALDATA BUS

CONTROL

* NOT USED ON QAW CARD

5/99 3-157 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

d inctedss

insd on

toused

r, the

that

r pinther front

3-9.4. Card Addressing and Data Output

Address Jumpers

The QAW card address is established by five jumper fixtures which are locatethe front-edge connector. The insertion of a jumper encodes a “1” on the seleaddress line (ADD3 through ADD7) which when matched by the DIOB addresignals selects the QAW card

Figure3-72 shows the pin configuration of the front-edge connector. The “B” pof the connector are located on the component side and the “A” pins are locatethe solder side of the p-c card.

QAW card addresses are programmed in groups of eight addresses in order maintain the address recognition circuits at a minimum. Two addresses are notby the QAW card since each card contains six analog input channels; howeveunused address can be used by other cards when required.

The addressing method allows up to 30 QAW cards to be used which means180 analog input channels can be provided.

Address protection is provided by a jumper insert on the front-edge connectopair (20A and 20B). This contact has been machined to be shorter than the ofront-edge contacts so that it disconnects before the other contacts when thecard-edge connector is removed from the QAW card.

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3-9. QAW

firste in

Output Data Bit Patterns

Figure3-73 shows a general, 16-bit, QAW card output data pattern format. The12 bits (0 through 11) are binary data that is obtained through a software routinthe QAW card microcomputer circuit.

Figure 3-72. QAW Card Front-Edge Connector Pin Assignments

1A

2A

3A

4A

5A

6A

7A

8A

9A

10A

11A

12A

13A

14A

15A

16A

17A

18A

19A

20A

21A

22A

23A

24A

25A

26A

27A

28A

1B

2B

3B

4B

5B

6B

7B

8B

9B

10B

11B

12B

13B

14B

15B

16B

17B

18B

19B

20B

21B

22B

23B

24B

25B

26B

27B

28B

SOLDERSIDE

COMPONENTSIDE

POINT 0 + INPUTPOINT 0 SHIELD

POINT 1 − INPUT

POINT 1 + INPUT

POINT 2 SHIELD

POINT 3 − INPUT

POINT 3 + INPUT

POINT 4 SHIELD

POINT 5 − INPUT

POINT 1 SHIELD

POINT 2 – INPUT

POINT 2 + INPUT

POINT 3 SHIELD

POINT 4 – INPUT

POINT 4 + INPUT

POINT 5 SHIELD

POINT 5 + INPUT UNUSED

DIOB ADDRESS PROTECTION GROUND DIOB ADDRESS PROTECTION GROUND

UNUSED

UNUSED

UNUSED

UNUSED

ADDRESS LINE A3

ADDRESS LINE A4

ADDRESS LINE A5

ADDRESS LINE A6

ADDRESS LINE A7

ADDRESS LINE A3 GROUND

ADDRESS LINE A4 GROUND

ADDRESS LINE A5 GROUND

ADDRESS LINE A6 GROUND

ADDRESS LINE A7 GROUND

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

POINT 0 – INPUT SIGNAL

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

UNUSED

JUMPER MUST BE IN PLACE FORPROPER CARD OPERATION

5/99 3-159 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

andorkfore

zeroicalit 13ne3

tore ista. A

). A the

The actual binary data that is sent to the system controller over the DIOB iscalculated by the microcomputer using data from a precision voltage networkfrom an analog-to-digital converter circuit. Data from the precision voltage netwadjusts the converted analog input (digital data) for offset and gain correction beit is output to the DIOB as point data.

Bit 12 is an overrange bit and bit 13 is a sign bit. A logic one signal at bit 12indicates that the count data is in the positive overrange when bit 13 is at a logicand that the count data is in the negative range when bit 13 is a logical one. A logzero at bit 12 indicates that the count data is in the negative overrange when bis a logical one and in the positive range when bit 13 is a logical zero. A logical oat bit 13 indicates the count is in the negative range and a logical zero at bit 1indicates that the count is in the positive range.

Bits 14 and 15 are flag bits. A logical one at bit 14 indicates that the offset facdata that was obtained during the auto-zero calibration microcomputer routinwithin reasonable limits and a logical zero indicates unreasonable auto-zero dalogical one at bit 15 (called IMOK bit) indicates that the hardware is operatingproperly (power is present, warm-up is complete, and the controller is operatinglogical zero at bit 15 indicates hardware trouble or that the offset factors fromauto-zero calibration are unreasonable on more than one input channel.

Note

Multiple channel offset errors will not setbit 15 on QAW cards with prefixes of 5 orgreater.

M0-0053 3-160 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

card

Table3-44 shows the nomenclature and the hexadecimal ranges for the QAWoutput data. Note that bits 14 and 15 are set by QAW card microcomputer;therefore, the positive range to negative transitions occurs in 14 bits.

Figure 3-73. QAW Card Output Data Pattern Format

Table 3-44. QAW Card Output Data Ranges

Data Classification Output Data Hexadecimal Code

Zero Input C000

Positive Range C001 to CFFF

Positive Full Scale D000

Positive Overrange D001 to DFFF

Negative Full Scale F000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OVERRANGE BIT

1 = COUNT IS IN POSITIVEOVERRANGE WHEN SIGN BIT13 = 0, AND IN NEGATIVERANGE WHEN SIGN BIT 13 = 1

0 = COUNT IS IN POSITIVE RANGE

SIGN BIT

1 = COUNT IS NEGATIVE

FLAG BIT SET BY QAW CARDMICROCOMPUTER

1 = OFFSET DATA OBTAINEDDURING AUTO CALIBRATIONIS WITHIN REASONABLELIMITS

FLAG BIT (SET BY MICROCOMPUTER)

1 = HARDWARE IS OPERATINGPROPERLY

BINARY DATA

Bit Number

5/99 3-161 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

.

gp to

d on

Controls and Indicators (Level 7 and earlier)

Figure 3-74 shows the card components for 7 level and earlier QAW.

Light Emitting Diodes (LED)

The QAW card (Level 7 and earlier) has one LED which indicates power “on”

For Group 5 QAWs, a current limiting lamp is part of each current loop. Durinnormal operation, the lamp is off. However, a short in the circuit causes the lamturn on.

Jumpers

Table3-45 lists the jumper numbers, locations and functions of the jumpers usethe QAW card.

Negative Range F001 to FFFF

Out of Range Offset 8000 to BFFF

Card Hardware Trouble 0000 to 7FFF

Figure 3-74. QAW Card Components (Level 7 and earlier)

Table 3-44. QAW Card Output Data Ranges

Data Classification Output Data Hexadecimal Code

J1,J2

J3,J4

LEDJ6,J7

G05 Only

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3-9. QAW

3-9.5. Controls and Indicators (Level 9 and later)

Figure 3-75 shows the card components for 9 level and later QAW.

Table 3-45. QAW Card Jumpers and Functions (Level 7 and earlier)

Jumper Number Function(Jumper in Place)

J1 For future use

J2 ORs signal IMOK (P13) to W274-2 Inverter

J31,2 Installed for 50 Hz systems

J41,2 Installed for 60 Hz systems

J51 For future use

J63 Selects on-board current loop supply for Group 5 only

J74 Selects external current loop supply for Group 5 only

1 Jumpers J3, J4 and J5 are not used on QAW cards with prefixes lower than 5.

2 The QAW card operates on its own time base when jumpers J3 or J4 are not inserted.

3 Jumper J6 is not shown on cards with prefixes lower than 3.

4 Jumper J7 is not shown on cards with prefixes lower than 5.

Figure 3-75. QAW Card Components (Level 9 and later)

LE1

LE2

43

21

JS14

SW

JS13

JS12JS11

JS16JS15

JS10JS9

JS18JS17

JS8JS7

5/99 3-163 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

as

83);

upard

ncy

Switches

The (Level 9 and later) QAW card uses a four-position DIP switch (seeFigure 3-75 for the location of the switch). The definitions of the switches arefollows:

Notes

Any other switch combination is not valid and theQAW card will not operate.

The QAW also has several factory preset jumpers.Changing these jumpers will affect calibration,therefore, no changes are recommended.

Jumpers

On Group 5 QAW cards, jumpers J7 and J8 (channel 0); jumpers J17 and J1(channel 1); jumpers J9 and J10 (channel 2); jumpers J15 and J16 (channel jumpers J11 and J12 (channel 4); and jumpers J13 and J14 (channel 5)MUST BEin the 2-3 position to enable on-card loop Power Supply. Refer toFigure 3-75 forthe jumper locations.

LEDs

The QAW card has two LED’s (seeFigure 3-75). LE1 indicates that power isapplied to the board. LE2 is used during the initial calibration of the board.

For on-line applications, LE2 will illuminate for about 1/2 second during power-and will remain off thereafter. Should this LED remain on or flash, return the boto Westinghouse for repair.

Table 3-46. QAW Jumper Configuration

Configuration SW1 SW2 SW3 SW4

50Hz operation X ON OFF X

60Hz operation X OFF ON X

No QTB1 X ON ON X

1The QTB card is necessary in installations where large variations of the power line frequeexist to provide for large normal mode rejection.

X = Reserved (Don’t Care)

M0-0053 3-164 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

Notes

Before returning the board for repair, check thefollowing:

1. Ensure that the DIOB power supplies are intolerance.

2. Ensure that the DIP switch is set according tothe valid configurations in the previous tables.

3-9.6. Installation Data Sheets

1 of 4

Figure 3-76. Wiring Diagram, QAW Groups 1,2,3,4, and 6

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

EDGE CONNECTOR

(+)

(SHIELD)

(−)

POINT 5

PLANT

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

POINT 4

(+)

(SHIELD)

(−)

20B

20A

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 0

(+)

(SHIELD)

(−)

POINT 5

(+)

(SHIELD)

(−)

(+)

(SHIELD)

(−)

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

(+)

(SHIELD)

(−)

POINT 4

POINT 0TRANSDUCER

(+)

(−)

GROUND

REQUIRED ENABLE JUMPER

NOTE: THISDRAWING ISFOR PLANTGROUNDEDTRANSDUCERS.

5/99 3-165 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

in the

, &

uts

te 1

Installation Notes: QAW Groups 1, 2, 3, 4, 6 (Refer to Figure 3-76)

1. If inputs are to be grounded at the system end, insert a #6 screw and nut hole located near the shield terminal on Terminal Block A. Then add twojumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 1417, have been drilled for this purpose.

2. If inputs are to be grounded at the signal source, ground both the (−) side of thesignal and the cable shield as shown below.

Installation Notes: QAW Groups 4, 6 (Refer to Figure 3-76)

If loop power is supplied by the customer but is external to the transducer, inpare grounded as follows:

3. If inputs are to be grounded at the system end, ground as described in Noand as shown below:

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

#6 SCREW

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

TRANSDUCER

(−)

(+)

(+)

(−)

S

A

#6 SCREW POWERSUPPLY

+−

M0-0053 3-166 5/99Westinghouse Proprietary Class 2C

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3-9. QAW

ote 2

4. If inputs are to be grounded at the signal source, ground as described in Nand as shown below:

TRANSDUCER

(−)

(+)

(+)

(−)

S

A

POWERSUPPLY

− +

5/99 3-167 M0-0053Westinghouse Proprietary Class 2C

Page 234: Ovation Q Line

3-9. QAW

in the

, &

Installation Data Sheet

2 of 4

Installation Notes: QAW Group 5 (Refer to Figure 3-77)

1. If inputs are to be grounded at the system end, insert a #6 screw and nut hole located near the shield terminal on Terminal Block A. Then add twojumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 1417, have been drilled for this purpose.

Figure 3-77. Wiring Diagram: QAW Group 5

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

EDGE CONNECTOR

RTN

SHIELD

SRC

POINT 5

PLANT

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

POINT 4

(+)

SHIELD

(−)

20B

20A

POINT 3

(+)

SHIELD

(−)

POINT 2

(+)

SHIELD

(−)

POINT 1

(+)

SHIELD

(−)

POINT 0

(+)

SHIELD

(−)

POINT 5

(+)

SHIELD

(−)

RTN

SHIELD

SRC

POINT 3

RTN

SHIELD

SRC

POINT 2

RTN

SHIELD

SRC

POINT 1

RTN

SHIELD

SRC

POINT 4

POINT 0TRANSDUCER

(−)

(+)

GROUND

REQUIRED ENABLE JUMPER

NOTE: THISDRAWING ISFOR PLANTGROUNDEDTRANSDUCERS.

RTN

SRC

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3-9. QAW

2. If inputs are to be grounded at the signal source, ground both the (−) side of thesignal and the cable shield as shown below.

(+)

(−)

S

A

#6 SCREW

RETURN

SOURCETRANSDUCER

(−)

(+)

(+)

(−)

S

ARTN

SRC

TRANSDUCER

(−)

(+)

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3-9. QAW

in the

, &

Installation Data Sheet

3 of 4

Installation Notes (Refer to Figure 3-78):

1. If inputs are to be grounded at the system end, insert a #6 screw and nut hole located near the shield terminal on Terminal Block A. Then add twojumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 1417, have been drilled for this purpose.

Figure 3-78. Wiring Diagram, QAW to TSC Card

Edge Connector

Point5

Point4

Point3

Point2

Point1

Point0

(+)Shield

(-)

(+)

Shield(-)

(+)

Shield(-)

(+)

Shield

(-)

(+)

Shield

(-)

(+)

Shield(-)

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

Note: This drawing is for plant grounded transducers.

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

S1

(-)1

(+)1

S2

(-)2

(+)2

S4

(-)4

(+)4

S6

(-)6

(+)6

S5

(-)5

(+)5

S3

(-)3

(+)3

S4

(-)4

(+)4

S6

(-)6

(+)6

S5

(-)5

(+)5

S3

(-)3

(+)3

S1

(-)1

(+)1

S2

(-)2

(+)2

Point5

Point4

Point3

Point2

Point1

Point0

RequiredEnable Jumper

Terminal Block#8-32 Screw

UIOB/DIOB13 V Power Supply

C +

TB3

TB1orTB2

TB1orTB2

2 1

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

Shield

(+)

(-)

AA

TSC Card

Terminal Block#6-32 Screw

Card

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

#6 SCREW

M0-0053 3-170 5/99Westinghouse Proprietary Class 2C

Page 237: Ovation Q Line

3-9. QAW

2. If inputs are to be grounded at the signal source, ground both the (−) side of thesignal and the cable shield as shown below.

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

5/99 3-171 M0-0053Westinghouse Proprietary Class 2C

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3-9. QAW

For CE MARK Certified System

4 of 4

Figure 3-79. QAW CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

POINT 4

(−)

(SHIELD)

(+)

POINT 3

(−)

(SHIELD)

(+)

POINT 2

(−)

(SHIELD)

(+)

POINT 1

(−)

(SHIELD)

(+)

POINT 0

(−)

(SHIELD)

(+)

POINT 5

(−)

(SHIELD)

(+)

(+)

(SHIELD)

(−)

POINT 5

(+)

(SHIELD)

(−)

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(−)

POINT 1

POINT 0TRANSDUCER

(+)

(−)

PLANTGROUND

POINT 4

TRANSDUCER

(+)

(−)

Note

The QAW inputs may be grounded in the field or at theB Cabcabinet as shown. This diagram is shown forGroup 5 QAWs.

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3-10. QAX

is aiodsxrdsed

3-10. QAX

12 Point Analog Input Card(Style 4256A64G01 through G06 )

3-10.1. Description

G01 through G06 are applicable for use in the CE MARK Certified System

The QAX card converts an analog field signal to digital data. The digital data summation of a frequency that has been counted for a period of time.Time perare a multiple of the nominal power line frequency (50 or 60Hz). There are sipossible card groupings, representing various input ranges. Up to 15 QAX ca(180 points) may be used with one DIOB controller. The QAX is the recommendfunctional replacement for two QAV (or QAW) cards.

Figure 3-80. QAX Block Diagram

DIOBData Address Control

DataBufferRAM

Address

µC, Counterand Control

Circuits

TransformerIsolation

TransformerIsolation

Channel 1Voltage toFrequencyConverter

Channel 12Voltage toFrequencyConverter

Decoder

...

...

...(-)(+) SHD (-)(+) SHD

Twelve Sets of Analog Field Inputs

5/99 3-173 M0-0053Westinghouse Proprietary Class 2C

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3-10. QAX

The design groups are as follows:

Note

The kit drawing which comes with each ofthe specified groups lists additional details oncabling, jumper settings, and installation.

3-10.2. Features

Each QAX card has the following features:

• IEEE surge withstand capability

• Auto zero - Auto gain correction

• Electrical isolation on all channels

• On card buffer memory for DIOB data transfers

• Open thermocouple detection (low level cards only)

• Common mode noise rejection

• Normal mode noise rejection

• Automatic reasonability test on the offset

Table 3-47. QAX Card Groups and Capabilities

Group Range

Resistance(Maximum

SourceImpedance)

Low-Level Groups

GO1 -5mV to 20mV (-20mV to 20mV at reduced accuracy) 500Ω

GO2 -12.5mV to 50mV (-50mV to 50mV at reduced accuracy) 500Ω

GO3 -25mV to 100mV (-100mV to 100mV at reduced accuracy) 1KΩ

High-Level Groups

GO4 0 to 1V 1KΩ

GO5 0 to 5V 5KΩ

GO6 0 to 10V 10KΩ

M0-0053 3-174 5/99Westinghouse Proprietary Class 2C

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3-10. QAX

ndsard.

ectorge

ys therds

ata

hter. Incise

ds for

g.

ng.

• Operation with a QTB timebase (in 50 or 60 Hz) or without a QTB

Each daughter board features:

• Signal conditioning

• Biasing

• Auto-zero and auto-gain correction

• Open thermocouple detection (low-level configurations only)

• Synchronous voltage to frequency converter.

• Offset and gain calibration factors are calculated approximately every 8 secofor each daughter board channel by the microprocessor on the mother bo

The QAX card is designed to be mounted in a standard Q-line card cage.Connection to the control system is made by a 34 pin rear edge backplane connfor the DIOB interface. Interface to the field wiring is made by a 56 pin front edconnector.

Each QAX card consists of a mother board and 12 Surface Mount Technologdaughter boards. Each daughter board handles one A/D channel and containcircuitry for an independent voltage to frequency converter. The daughter boainterface to the mother board via 30 pin SIMM connectors. The mother boardprovides for the DIOB interface, field interface, daughter board control, and dprocessing.

The QAX card uses a transformer based electrical isolation circuit on each daugcard which separate the 12 cards from each other and from the mother boardaddition, the isolation circuit provides power for each daughter board and pretiming from a stable frequency generated on the mother board.

The QAX card features electronic (non-mechanical) auto-calibration whichbehaves as follows:

• Two known potentials on the analog daughter boards are used as standaroffset and gain calibration.

• One standard is 0 volts (shorted input) which is used for offset calibration.

• On high-level cards, the second standard is derived from a stable voltagereference and is approximately 100% of the maximum analog input readin

• On low-level cards, the second standard is derived from a stable voltagereference and is approximately -150% of the maximum analog input readi

5/99 3-175 M0-0053Westinghouse Proprietary Class 2C

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3-10. QAX

into

eter)

ic 0.

15 of

med.

• The gain calibration value is compared against a calibration constant loadedan EEPROM on the mother board during initial calibration. This calibrationconstant is necessary in order to provide a non-mechanical (no potentiomcalibration system.

The QAX processor also provides on-card diagnostics. One feature is areasonability check for the offset calibration factor. Failure of the reasonabilitycheck causes bit 14 (offset-out-of-range) in the data package to be set to logWith this feature, any one channel can fail while the others are still active andaccurate. When the card is warmed up (about 15 seconds after power up), bitthe data package is set to logic one to indicate the card is ready.

Note

All daughter boards located on a given motherboard MUST be of the same design group.

3-10.3. Specifications

Power Supply Voltage

Inputs

Point Sampling rate (samples/second): 4

Once every 32 conversions, auto zero and auto gain calibration are perfor

Resolution: 13 bits (including polarity bit)

Input Channel Sample Period: 0.20 seconds

Table 3-48. QAX Power Requirements

Minimum Nominal Maximum

Primary Voltage 12.4VDC 13.0VDC 13.1VDC

Backup 12.4VDC 13.1VDC

Power supply current 0.9 A DC 1.1 A DC

Power dissipation 11.7 Watts 14.5 Watts

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3-10. QAX

cy off the

t data

cy ofe.

e

Normal Mode Voltage

Surge: Meets IEEE test specification without damage; however, the accurathe reading is reduced during, and up to 10 seconds following the removal osurge.

Continuous: An overvoltage of±120 VDC or VAC RMS at 50 or 60 Hz will notdamage the card; however, a sustained overvoltage can affect subsequenfor several minutes following the removal of the overvoltage.

Normal Mode Rejection

60 DB at 50 or 60 Hz using QTB line frequency tracking or at 50 or 60 Hz+0.5 percent without QTB line frequency tracking.

25 DB at 50 HZ± 5% or 60 Hz± 5% without QTB line frequency tracking.

Note

The input peak to peak AC voltage must not exceed100% of the upper range value for specified accuracyand normal mode rejection.

Common Mode Voltage

Surge: Meets IEEE test specification without damage; however, the accurathe data is reduced for up to 10 seconds following the removal of the surg

Continuous: A maximum of 500 VDC or peak AC can be applied withoutdamage.

Common Mode Rejection

120 DB at DC and power line frequency including harmonics with QTB linfrequency tracking.

100 DB for nominal line frequency±5% including harmonics with QTB linefrequency tracking or at 50 or 60 Hz±0.5% w/o QTB line frequency tracking.

Note

Common mode rejection does not apply ifpeak AC input exceeds 200,000% of theupper range value.

Input Impedance: 10 MΩ4 KΩ in overload or powered down

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Reference Accuracy:± 0.1% of the upper range value±10µV±1/2 LSB @ 99.7% confidence.

Reference conditions: 25±1°C ambient temperature, 50±2% relativehumidity, 0V common mode noise, 0V normal mode nois

Drift: 0.002% per month (typical)0.02% long term (typical)

3-10.4. Card Addressing

The QAX card address is established by four jumpers on the top, front, card-connector. The insertion of a jumper encodes a “1” on the address line. The fijumper is used for Address Protection. This addressing method allows up to 1QAX cards or a total of 180 analog points.

The front edge connector pin pair 24A-B. This contact has been machined toshorter than the other front edge contacts so that it disconnects before the otcontacts when the front edge connector is removed. This gap eliminates thepossibility of a momentary false address while the card is being removed.

Table 3-49. QAX Input Signal Requirements

Group Signal Requirements

G01 -5 to 20 mV (-20 mV to 20 mV at reduced accuracy)500Ω maximum source impedance.

G02 GO2: -12.5mV to 50mV (-50mV to 50mV at reduced accuracy)500Ω max source impedance.

G03 -25mV to 100mV (-100mV to 100mV at reduced accuracy)1KΩ max source impedance.

G04 0 to 1 V1KΩ max source impedance.

G05 0 to 5 V5KΩ max source impedance.

G06 0 to 10 V10KΩ max source impedance.

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Point Addressing on the QAX Card (WDPF System)To specify the desired grouping, the Card Type Index (CD) and the Hardware O(HW) fields of the analog input point record must be initialized with the propevalues to ensure that the point will be processed correctly by the analog scanroutines of the DPU.The QAX card allows for as many as 12 analog inputs per card. Each QAX requa block of 16 DIOB addresses. Since there can only be a maximum of 12 pointsQAX, but 16 DIOB addresses taken, 4 of the 16 addresses are not used. Thefollowing illustrates point addressing on the QAX card:Each point's hardware offset calculation is as follows:

For analog points 1 though 6: HW = 2 [ADD + (PN-1)] + MBUFor analog points 7 though 12: HW = 2[ADD + (PN-7)] + 10H + MBU

where:

ExampleFor a QAX at card address (ADD) of 80H, the following addresses must be usedthe Hardware Offset (HW) field of each analog input:

Note that if thermocouple compensation is selected (CD = 71, 72, 73) on any oanalog inputs, ANALOG INPUT 12 must not be used as a field input. It is reserby the QAX, so that it can read the temperature of the terminal block from the QA

HW = point's hardware offset

ADD = card address (in hexadecimal)

PN = relative point number on card

MBU = MBU offset

Table 3-50. QAX Address Offsets (WDPF Systems)

Input IdentificationHexadecimal

Address Input IdentificationHexadecimal

AddressANALOG INPUT 1 100H ANALOG INPUT 7 110HANALOG INPUT 2 102H ANALOG INPUT 8 112HANALOG INPUT 3 104H ANALOG INPUT 9 114HANALOG INPUT 4 106H ANALOG INPUT 10 116HANALOG INPUT 5 108H ANALOG INPUT 11 118HANALOG INPUT 6 10AH ANALOG INPUT 12 11AHAVAILABLE 10CH AVAILABLE 11CHAVAILABLE 10EH AVAILABLE 11EH

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Point Addressing on the QAX Card (Ovation System)

To specify the desired grouping, the Card Type Index (CD) and the Hardware O(HW) fields of the analog input point record must be initialized with the propevalues to ensure that the point will be processed correctly by the analog scanroutines of the Controller.The QAX card allows for as many as 12 analog inputs per card. Each QAX requa block of 16 DIOB addresses. Since there can only be a maximum of 12 pointsQAX, but 16 DIOB addresses taken, 4 of the 16 addresses are not used.

Ovation automatically assigns the correct addresses and adjusts for the sparaddresses (identified as AVAILABLE inTable 3-51 shown below). However, thefour AVAILABLE addresses can still be used by other Q-Line cards, if needed

Example

For a QAX at card address (ADD) of 80H, the following addresses must be usedthe Hardware Offset (HW) field of each analog input:

Note that if thermocouple compensation is selected (CD = 71, 72, 73) on any oanalog inputs, ANALOG INPUT 12 must not be used as a field input. It is reserby the QAX, so that it can read the temperature of the terminal block from the QA

Table 3-51. QAX Address Offsets (Ovation System)

Input IdentificationHexadecimal

Address Input IdentificationHexadecimal

AddressANALOG INPUT 1 100H ANALOG INPUT 7 110HANALOG INPUT 2 102H ANALOG INPUT 8 112HANALOG INPUT 3 104H ANALOG INPUT 9 114HANALOG INPUT 4 106H ANALOG INPUT 10 116HANALOG INPUT 5 108H ANALOG INPUT 11 118HANALOG INPUT 6 10AH ANALOG INPUT 12 11AHAVAILABLE 10CH AVAILABLE 11CHAVAILABLE 10EH AVAILABLE 11EH

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Thermocouple Information

Table 3-52 shows the standard WDPF thermocouple coefficient definitions.Coefficients may also be user-defined. For additional information on selecting tcoefficients, refer to the CI record field discussion in“RecordTypesUser’sGuide”(U0-0131).

Table 3-52. QAX Thermocouple Coefficient Definitions

Thermocouple Type Coefficients

B 70% Platinum+ 30% Rhodiumor94% Platinum+ 6% Rhodium427-1093°C800-2000°F

C0 = 0.3516470E+ 03C1 = 0.6138849E+ 03C2 = −0.1539774E+ 03

C3 = 0.3359373E+ 02C4 = −0.4051826E+ 01C5 = 0.2003933E+ 00

E Chromel/Constantan−18-982°C0-1800°F

C0 = 0.3167283E+ 02C1 = 0.3030628E+ 02C2 = −0.3344949E+ 00

C3 = 0.6849588E− 02C4 = −0.6975349E− 04C5 = 0.2923653E− 06

J Iron/Constantan−96-760°C−140-1400°F

C0 = 0.3112531E+ 02C1 = 0.3607027E+ 02C2 = −0.4288617E+ 00

C3 = 0.2261382E− 01C4 = −0.5174379E− 03C5 = 0.3972783E− 05

K Chromel/Alumel−18-1093°C0-2000°F

(The upper range may be extended to2500 with less accuracy)

C0 = 0.3034473E+ 02C1 = 0.4403191E+ 02C2 = 0.1615839E+ 00

C3 = −0.1616257E− 01C4 = 0.4401109E− 03C5 = −0.3599650E− 05

R Platinum+ 13% Rhodium260-1093°C500-2000°F

C0 = 0.8362848E+ 02C1 = 0.2273716E+ 03C2 = −0.1248286E+ 02

C3 = 0.1206254E+ 01C4 = −0.7422128E− 01C5 = 0.1899300E− 02

S Platinum+ 10% Rhodium399-1093°C750-2000°F

C0 = 0.1180344E+ 03C1 = 0.1985918E+ 03C2 = −0.1973096E− 01

C3 = −0.5009329E+ 00C4 = 0.4110488E− 01C5 = −0.1155794E− 02

T Copper/Constantan46-399°C−50-750°F

C0 = 0.3189224E+ 02C1 = 0.4669328E+ 02C2 = −0.1325739E+ 01

C3 = 0.6962067E− 01C4 = −0.2327808E− 02C5 = 0.3330646E− 04

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Low-Level Analog Inputs

The following card type indices must be used when low-level analog inputs are to be read fthe QAX card:

Low-Level Analog Inputs with QAXT Thermocouple Compensation

The following card type indices must be used when low-level analog inputs are to be read fthe QAX card and thermocouple compensation using the QAXT Temperature Sensor Boarbe performed:

Special Considerations with Card Types 71, 72, 73:

1. When Card Types 71, 72, 73 are used the QAX is limited to handling onlyanalog inputs. The 12th input is reserved for sensing the thermocoupletemperature from the QAXT. The temperature can be read by using an aninput point addressed to channel 12 of the QAX, and using a Card Type o69, or 70.

2. The CV field of the analog input record must be initialized to 7 to indicate tha thermocouple conversion is to be done.

3. The CI field of the analog must be initialized according to the thermocouptype and temperature range. Values for CI are listed in the“RecordTypesUser’sGuide” (U0-0131).

Table 3-53. QAX Low-Level Inputs

Group/Rev.Range Index Input/Output Voltage Range Units

G01 68 Input - 20 to + 20 mV

G02 69 Input - 50 to + 50 mV

G03 70 Input -100 to +100 mV

Table 3-54. QAX Low-Level Inputs with Compensation

Group/Rev. Index Input/Output Voltage Range Units

G01 71 Input - 20 to + 20 mV

G02 72 Input - 50 to + 50 mV

G03 73 Input -100 to +100 mV

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High-Level Analog Inputs

The following card types must be used when high-level analog inputs are to befrom the QAX card:

Output Data

The analog signal is converted to the output data pattern below and sent to the DIO

The following chart shows the data pattern ranges for each of the two channeoutput data

Table 3-55. QAX High Level Inputs

Group/Rev. Index Input/Output Voltage Range Units

G04 74 Input 0 to + 1 V

G05 75 Input 0 to + 5 V

G06 76 Input 0 to + 10 V

Figure 3-81. QAX Output Data Pattern

Table 3-56. QAX Data Pattern Range

Classification Output Data

Zero Input C000

Positive range C001 to CFFF

PCSO DDDD DDDD DDDD

Binary digital data representing the analog input voltage,as computed by the A/D converter on the QAX

Overrange bit. Logic 1 represents positive overrange if sign bit“S”=0. Logic 0 represents negative overrange if sign bit “S”=1.

Offset Quality. Logic 1 indicates that a reasonable offset orzero was read during auto-calibration.

I’m OK bit. Set if the card is warmed up (15 seconds after powerup) and the hardware is operating properly.

Sign bit. Logic 1 indicates a negative value.

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3-10. QAX

3-10.5. Controls and Indicators

Note

If the QAXT card is to be used to providethermocouple compensation, the resistorprovided in the QAXT kit must be installed.

Positive Full Scale D000

Positive Overrange D001 to DFFF

Negative Overrange and Open Thermocouple Detect E000 to EFFF

Negative Full Scale F000

Negative range F001 to FFFF

Offset out of range 8000 to BFFF

Card Trouble or Not Warmed Up 0000 to 7FFF

Figure 3-82. QAX Card Components

Table 3-56. QAX Data Pattern Range

Classification Output Data

LE1LE2

SW1

Spring socketsfor QAXT withhalf-shellthermocouplecompensation

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Switches

The QAX card uses a four-position DIP switch (seeFigure3-82 for the location ofthe switch). The definitions of the switches are as follows:

Notes

Any other switch combination is not valid and theQAX card will not operate.

The QAX also has several factory preset jumpers.Changing these jumpers will affect calibration,therefore, no changes are recommended.

LED

The QAX card has two LED’s (seeFigure3-82). LE1 indicates that power is appliedto the board. LE2 is used during the initial calibration of the board.

For on-line applications, LE2 will illuminate for about 1/2 second during power-and will remain off thereafter. Should this LED remain on or flash, return the boto Westinghouse for repair.

Notes

Before returning the board for repair, check thefollowing:

1. Ensure that the DIOB power supplies are intolerance.

2. Ensure that the DIP switch is set accordingto the valid configurations in the previoustables.

Table 3-57. QAX Jumper Configuration

Configuration SW1 SW2 SW3 SW4

50Hz operation X ON OFF X

60Hz operation X OFF ON X

No QTB1 X ON ON X

1The QTB card is necessary in installations where large variations of the power line frequeexist to provide for large normal mode rejection.

X = Reserved (Don’t Care)

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3-10.6. Installation Data Sheet

1 of 2

Figure 3-83 shows inputs grounded at the signal source. If signals are to begrounded at the system end, insert a #6 screw in the hole located near the shterminal on halfshell block “A” and add two jumpers as shown inFigure3-84. Sixholes on each halfshell block have been drilled for this purpose.

Figure 3-83. QAX Wiring Diagram

171618141315111012879546213

171618141315111012879546213

23B22B

23A22A21A19B18B17B19A18A17A15B14B13B15A14A13A

24A24B

21B

11B10B

11A10A

9A7B6B5B7A6A5A3B2B1B3A2A1A

9B

sh-+sh-+sh-+sh-+sh-+sh-+

sh-+sh-+sh-+sh-+sh-+sh-+

Point 5

Point 4

Point 3

Point 2

Point 1

Point 0

Point 11

Point 10

Point 9

Point 8

Point 7

Point 6

6 Pair TwistedShielded Cable

6 Pair TwistedShielded Cable

“A”Block

Halfshell#2

“A”Block

Halfshell#1

Transducer(-)(+)

(Dotted line indicatesshielding)

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Notes

1. Field Signals interface to the standard 56 pin Q-line front edge connector.DIOB address and address protection jumpers are located on this connecEach input requires a+, -, and shield pin.

2. The density of the card requires unique cabling to the field termination hashells. The QAX requires the use of the Enhanced Q-line B cabinet andterminations (2 halfshell termination blocks per card) (seeFigure 3-83).

3. If it is necessary to interface to current loops, appropriate termination resiswill be required to be placed across to (+) and (-) inputs on the “A” terminablock to convert the current to the proportional voltage. For example, with Group 5 card at 5V and 20mA current, a 250Ω resistor is used. (Using Ohm’slaw of V=IR, rearranging to V/I = R, R = 5/0.02 = 250Ω.

Figure 3-84. QAX Shield Wiring

(+)

(S)

(-)

(+)

Transducer(-)

(+)

(S)

(-)Transducer

(-)

Jumpering to shield for loop power developed internal to transducer.

Jumpering to shield for loop power by customer but external to transducer.

PowerSupply

(-)

(+)

(+)

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3-10. QAX

AX

Recommended Standard B-Cabinet Configuration

The following Q-Crate configuration is recommended when using 15 or less Qcards.

Figure 3-85. QAX Recommended Configuration

B-Cabinet Halfshell Terminal Blocks

1 2 3 4 5 6

Zone A5 QAX #1 11 QAX #3 QAX #5

0 Q102 6 Q110 Q118

Zone B QAX #2 QAX #4 QAX #6

Q104 Q112 Q120

Zone C QAX #7 QAX #9 QAX #11

Q202 Q210 Q218

Zone D QAX #8 QAX #10 QAX #12

Q204 Q212 Q220

Zone E QAX #13 QAX #15

Q31

8

Q32

2

Q302 Q310

Zone F QAX #14

Q31

2

Q31

6

Q32

0

Q32

4Q304

Zone G

Q40

2

Q40

6

Q41

0

Q41

4

Q41

8

Q42

2

Zone H

Q40

4

Q40

8

Q41

2

Q41

6

Q42

0

Q42

4

ChannelNumber

Q-CrateLocation

NumberSlot

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For CE MARK Certified System

2 of 2

Figure 3-86. QAX CE MARK Wiring Diagram

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 4

(+)

(SHIELD)

(−)

POINT 3

(+)

(SHIELD)

(−)

POINT 2

(+)

(SHIELD)

(-)

POINT 1

POINT 0TRANSDUCER(+)

(−)

1

3A

1A

2B

3B

1B

6A

7A

5A

6B

7B

5B

10A

11A

9A

10B

11B

9B

2A

15A

13A

14B

15B

13B

18A

19A

17A

18B

19B

17B

22A

23A

21A

22B

23B

21B

14A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

POINT 10

(+)

(SHIELD)

(−)

POINT 9

(+)

(SHIELD)

(−)

POINT 8

(+)

(SHIELD)

(-)

POINT 7

POINT 6TRANSDUCER(+)

(−)

2

NoteThe QAW inputs may be grounded in the field or at the Bcabinet as shown.

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3-11. QAXD

QAX Digital Daughter Board(Style 4256A65G01 through G06)

3-11.1. Description

The 12 point analog input module may consist of the mother board (referred the QAX) with a set 12 low level daughter boards (referred to as QAXD boardThe daughterboards attach to the mother board via SIMM connectors located oQAX mother board. The QAX mother board contains the DIOB interface, theprocessor for data manipulation and buffering, the timing and power control fordaughter boards and the termination and signal conditioning for the field interfThe daughter boards contain the A/D circuitry.

Note

All daughter boards on the configuredmodule must be the same voltage range.

The features of each daughter board are provided by the custom resistor netThe resistor networks are used to generate calibration voltages from the precvoltage reference and to scale the preamplifier so that the output of the preampprovides the same voltage swing for all groups.

Table 3-58. QAXD Card Groups and Capabilities

Group Range

Low-Level Groups

GO1 -5mV to 20mV (-20mV to 20mV at reduced accuracy)

GO2 -12.5mV to 50mV (-50mV to 50mV at reduced accuracy)

GO3 -25mV to 100mV (-100mV to 100mV at reduced accuracy)

High-Level Groups

GO4 0 to 1V

GO5 0 to 5V

GO6 0 to 10V

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ycleload0

ouit onncyAV/

The input multiplexer switches between the input voltage and the calibrationvoltages provided by the precision voltage reference and the resistor network.the QAV/QAW the counter is incremented by short duration stoppages of PSD (µ sec.) and the counter is reset by longer stoppages of PSD (~194µ sec.). Thecounter nodes are different depending on whether the card is high-level or low-las shown in theTable 3-59:

Since the low-level card has the OTD (open thermocouple detect node) and torder of the other nodes is slightly different, it is necessary for the QAX mothboard’s processor to know which type of daughter board is installed. A 1Ω resistoris installed on the high-level board between pin 6 at the SIMM connector and loground. On the low-level board, this resistor is absent. Therefore, pin 6 is essengrounded on the high-level board and left floating on the low-level board. All 1“pin sixes” on the mother board are daisy chained, pulled-up, and routed to bitthe mother board’s status register. When bit 4 of the status register is logic 1/0,high-level boards are present.

As mentioned in the QAX reference sheets, the PSD signal has a 25% duty cwhich necessitates the need for a transformer discharge circuit. To provide a for the discharge circuit (FET and Schottkey diode on the mother board), a 15Ωresistor is provided between the transformer primary and pin 4 of the SIMMconnector.

The integrator/synchronous comparator circuit used to generate the voltage tfrequency conversion operate essentially the same as the corresponding circthe QAV/QAW. Also the capacitor discharge circuit used to generate the frequeinput pulse for the 12 counters on the mother board operates similar to the QQAW.

The +/-15 volt power supply on each daughter board uses shunt regulation toprovide a low input to output voltage dropout.

Table 3-59. QAXD Counter Nodes

Node High Level Low level

Q0 VIN VIN

Q1 REF (+100% full scale) OTD (-150% full scale)

Q2 ZERO (0% full scale) BIAS (0% full scale)

Q3 N/A REF (+100% full scale)

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The QAXD cards provide consistent counts among all groups on a% full scalebasis. While the high-level boards can read negative values, no accuracyspecification is provided at this time. The approximate counts for each QAXD apercentage of full scale over a 200 msec sampling time is as follows:

Percent of full scale Counts

+100 12,600

0 8,400

-100 4,200

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ocks

ure

the

d

3-12. QAXT

Terminal Block Temperature Sensing(Style 4256A86G01)

3-12.1. Description

Applicable for use in the CE MARK Certified System

The QAXT printed circuit board provides temperature sensing of the terminal bl(at the point where the thermocouple wire is terminated). The QAXT facilitate“Cold Junction” or “Reference Junction” compensation in a QAX basedthermocouple input temperature measuring system.

The QAXT printed circuit board complements the QAX card when used to meastemperatures with thermocouple inputs. The QAX senses the QAXT outputbetween the (+) and (-) input terminals. The QAX card powers the QAXT via Channel #12 (Shield) (+12V). The power return is via the “B” cabinet’s “PG”ground. With this configuration, the “B” and “A” cabinet “PG” grounds must be tietogether.

Figure 3-87. QAXT Block Diagram

VoltageReference

ZeroAdjust

GainAdjust

Sensor(Temperature tocurrent conversion)

OpAmp

SwitchedCapacitorConverter

VoltageDivider

Output

Common

Common

Common

Common

-12V

+12V

+12V

J1

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rd.

3-12.2. Features

The QAXT provides half-shell temperature compensation for the QAX card. TQAXT can be configured to match the input ranges of any of the following thr“low level” QAX scales. (For a listing of thermocouples and their temperatureranges see “Record Types User’s Guide” (U0-0131) or QAX card reference pagein this manual).

• + 20 mV

• +50 mV

• +100 mV

The output of the QAXT is automatically scaled to Engineering Units. This meathat in any of the three configurations, the “0” output from the QAXT represen0°C and the (+ Full Scale) output equals 100°C.

Note

Due to operating limits of the QAXT, thetemperature output is limited to the range of0°C to 60°C.

3-12.3. Specifications

Table 3-60. QAXT Power Supply Voltages (from QAX)

Minimum Nominal Maximum

10.8 V 10.0 V 13.1 V

Table 3-61. QAXT Accuracy

Parameter Specification*

Absolute error +1.0°C over the ambient temperature range of 0 - 60°C.

Drift +0.1°C - typical

*Does not include errors introduced during initial card calibration and errors of the QAX ca

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3-12.4. Controls and Indicators

Table 3-62. QAX/QAXT Based Thermocouple Compensation Kit Group Usage

QAX/QAXT Based ThermocoupleCompensation Kit Range

3A99722 G01 ± 20 mV - Standard half-shells

3A99722 G02 ± 50 mV - Standard half-shells

3A99722 G03 ± 100 mV - Standard half-shells

3A99722 G04 ± 20 mV - Remote I/O Assembly

3A99722 G05 ± 50 mV - Remote I/O Assembly

3A99722 G06 ± 100 mV -Remote I/O Assembly

Figure 3-88. QAXT Card Components

642

531

SHLD (-)(+)

Header (JS1)

150%of

Full Size

Jumper (J1)

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3-12. QAXT

ows 100

Subet

l

Jumpers

The QAXT board contains a dual row, 3 - position header (JS1)(seeFigure3-88). A program jumper (J1) is used to short posts on the adjacent rof the header. The jumper selects one of the three possible ranges (20, 50 ormV) to match the QAXT to the corresponding QAX Group:

3-12.5. Wiring

B-Cabinet Installation

1. The “B” type cabinets must be equipped with an isolated bus bar (1B299122 or later) (seeFigure3-90). This bus bar must be connected to the “A” cabinPG ground to facilitate the power return for the QAXT.

2. Half shells for QAX cable must be adjacent (side-by-side, not vertically)

Table 3-63. QAXT Jumpers

HeaderReferenceDesignator

PostsShorted Result

JS1 *1-2 Scales to 1.0 mV/°C for Group03 and06 QAX cards.

JS1 3-4 Scales to 0.5 mV/°C for Group02 and05 QAX cards.

JS1 5-6 Scales to 0.2 mV/°C for Group01 and04 QAX cards.

*Default QAXT jumper configuration.

Table 3-64. QAXT Terminations

TerminalIndicator Signal Description

(+) Output 20 mV, 50 mV, or 100 mV Full Scale, jumper selectable.

SHLD +12V The cable shield supplies power from the QAX.

(-) Common Output reference.

Point Number Termination Point

1 Terminal 1, bottom of left half-shell

12 Terminals 16, 17, 18, top of the adjacent (right) half-shel

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3-12. QAXT

rd.

Installing R75 Jumper

A jumper must be installed across R75 on the QAX card (as shown inFigure3-89) when using the 12th input point on a QAX card, with the QAXT ca

This QAX card (with R75 jumper installed) is no longer exchangeable with astandard QAX card.

Figure 3-89. QAX Card with R75 Jumper Installed

LE1

LE2

R75

R76

R70

R69

REMOVING MODULES WILL VOID CALIBRATION

POK

CAL

WESTINGHOUSE MADE IN U.S.A.

QAX Card

Install Jumper

5/99 3-197 M0-0053Westinghouse Proprietary Class 2C

Page 264: Ovation Q Line

3-12. QAXT

Figure 3-90. QAXT Standard Half-Shell Cabinet Installation

2019181716151413121110987654321

QAXT

Half-Shell

Ground Bar

Protective Cover

Component sideof QAXT towardsterminal block.

Note:

Card

M0-0053 3-198 5/99Westinghouse Proprietary Class 2C

Page 265: Ovation Q Line

3-12. QAXT

Figure 3-91. QAXT Remote I/O Half-Shell Cabinet Installation

2019181716151413121110987654321

Protective Cover

Ground Bar

Half-Shell

QAXT

Component sideof QAXT towardsterminal block.

Note:

Card

5/99 3-199 M0-0053Westinghouse Proprietary Class 2C

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3-13. QBE

d

ratee

3-13. QBE

Q-Line Bus Extender(Style 7379A84G01 through G02 )

3-13.1. Description

Applicable for use in the CE MARK Certified System

The QBE card links DIOB backplanes between different card cages. This carprovides DIOB extension within the microprocessor-based or WDPF processcontrol systems while reducing transient potential differences between card cgrounds to a safe level. The QBE card, together with compatible flat-flex cablassemblies, provides a continuous DIOB for multiple card-cage systemconfigurations (seeFigure 3-92).

Figure 3-92. QBE Block Diagram

DIOB

LevelShift and

DMAClamp

“ UCLOCK”

On-CardPower

Supplies

DIOB Bus Expansion +12 VDCTo/From Adjacent

QBE cards

Common

ClampCircuit

BusDischarge

Circuit“G01”

MBUPower

M0-0053 3-200 5/99Westinghouse Proprietary Class 2C

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3-13. QBE

ate

re

r

perablee, it

d cagehup.

ntes

rtion.

thetible

ges.

theer

e

3-13.2. Features

The QBE card provides the following functions for Q-line applications:

• Signal transfer from one Q-line card crate to another with provision to elimindriver latch-up

• Distributed Input/Output Bus (DIOB) discharge to eliminate data errors.

• Signal-level clamping for all DIOB signals.

• Signal-level shifting for signalUCLOCK.

The thirty-four conductor Distributed I/O Bus (DIOB) is the protocol and structufor Q-Line I/O data collection and distribution. The DIOB permits an eight-bit,byte-oriented digital exchange of information between a multiplexing controlleand a variety of Q-line point cards.

Physically, the DIOB consists of a number of printed circuit backplanes (one card cage) which are linked together by interposing paddle cards and flat-flex cassemblies. When a DIOB is extended beyond a single printed circuit backplanbecomes susceptible to problems caused by transient differences between carDIOB ground potentials. The problems that occur are data errors and driver latc

The QBE card is designed to link the printed circuit DIOB backplanes in differecard cages together and at the same time reduce transient potential differencbetween card crate ground to a safe level (seeFigure3-93). These transient groundpotential differences may be due to industrial noise, IEEE surge, or card inse

A DIOB may be extended beyond a single card cage backplane by transferring25 DIOB signals to adjacent card cage backplanes via the QBE card and compaflat-flex cable assemblies, thus providing a continuous bus for multiple card caThe QBE card also links the DIOB grounds in each cage together, but has noprovision for distributing or transferring power to the DIOB. Studs mounted onrear of each DIOB printed circuit backplane receive power from the 13 VDC powsupply, and transfer the power to the printed circuit backplane DIOB powerconductors. A two-point terminal block located near the upper front edge of thQBE card is used to supply power to the Multibus-to-DIOB interface card(MBU/MSQ).

5/99 3-201 M0-0053Westinghouse Proprietary Class 2C

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3-13. QBE

OBo

ards

.

The QBE card’s 34-pin J1 backplane connector is normally inserted into the DIbackplane’s right-most card-edge connector. On the front edge of the QBE, tw50-pin connectors (J2 and J3) interface with 50-conductor flat-flex cableassemblies, transferring the 25 DIOB signals via the cable assemblies to QBE clocated in adjacent card cages (seeFigure 3-94). The DIOB grounds of adjacentcard crates are linked together by the same QBE cards and cable assemblies

Note

The QBE card will not interface to the front edgeconnectors of the QMT, QPD, or QPP cards.

Figure 3-93. Typical, Multicrate, Q-Line System Using QBE Card Interfacing

J2 Connector

J3 Connector

J2

J3

J2

J3

DIOB Backplane

DIOB Backplane

DIOB Backplane

To 50-pin DIOB Edge Connector

G01 QBE Card

G01 QBE Card

G01 QBE Card

50-conductorFlat-Flex CableAssembly

Q-Line Card Crate

To 50-pin DIOB Edge Connectorof the MBU/MSQ Card(Redundant DPU Only)

13 VDCPrimarySupply

13 VDCBackupSupply

of the MBU/MSQ Card

To MBU/MSQ CardPower Terminals(Redundant DPU Only)

Note:In this configuration, the DIOB iscontrolled by a Multibus controllercard. The MBU or MSQ card servesas an interface between the DIOBand the Multibus.

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3-13. QBE

cyf

oink

ese

he

ging

If the QBE card’s fuse blows, the QBE card “pulls down” the DIOB if the frequenof DIOB word cycles is less than 200/sec. A word cycle involves the transfer otwo-bytes of data between the controller and a point card.

All DIOB signals exceptUCLOCK are nominally+11 VDC logic signals.UCLOCK is a nominal+5 VDC logic signal which is inverted and level shifted ta+11 VDC logic level for transmission over the flat-flex cable assemblies that lthe QBE cards of adjacent crates together. The card cage that houses theUCLOCKsignal source has a QBE mounted in it that takes the+5 VDC UCLOCK signal offthe card cage DIOB backplane, inverts it, and shifts it to+11 VDC level(UCLOCK). UCLOCK is transferred to the QBE card’s J2 and J3 front edgeconnectors where it is transmitted to other QBE cards on the same DIOB. ThQBE cards receive the+11 VDCUCLOCK signal via their J2 and J3 front edgeconnectors.UCLOCK is then inverted, level shifted to a+5 VDC level (UCLOCK)and is transferred to the card cage’s DIOB backplane via the QBE card’s J1connector. The user may use jumpers to select what type ofUCLOCK level shift isrequired for a specific QBE card.

The QBE card is available in two assembly groups:

• Group 1 provides DIOB signal transfer and clamping, bus discharging of tDIOB data lines (UDAT 0-7) and the DEV-BUSY line,UCLOCK level shifting,and distributes twelve volt power to the MBU/MSQ card (seeFigure 3-95).

• Group 2 provides the same functions as Group 1 minus the DIOB discharfeature.

5/99 3-203 M0-0053Westinghouse Proprietary Class 2C

Page 270: Ovation Q Line

3-13. QB

E

M0-0053

3-204 5/99

Westinghouse P

roprietary Class 2C

J2

J3

DIOB Signalsand Commonto and fromAdjacentQBE Card

25

MBU/MSQCard

Power

+12 VDC

DIOB Common

Figure 3-94. Q

BE

Card F

unctional Block D

iagram

UDAT0-7and

DEV-BUSY

R/W

Data-gate

Level Shiftand Clamp

Circuits UCLOCKUCLOCK

5Volt

Supply

15Volt

Supply

Clamp Circuit

25

24

To24

DIOBCrate

BackplaneJ1

BusDischarge

Circuit(Group 1

Only)

9

0.8Volt

Supply

(All DIOB SignalsExcept UCLOCK)

Page 271: Ovation Q Line

3-13. QBE

3-13.3. Specifications

Power Requirements

Figure 3-95. QBE Timing Diagram of the Operation of the Bus Discharge Circuit

Table 3-65. QBE Power Supply Voltage

Minimum Nominal Maximum

Primary Voltage: 12.4 VDC + 13.0 VDC 13.1 VDC

Optional Backup: 12.4 VDC -- 13.1 VDC

Table 3-66. QBE Internal Power Supply Voltages

Minimum Maximum

5 VDC Supply 4.80 VDC 5.20 VDC

Read ExistingPoint Card

Data Gate

Read MissingPoint Card

Write to aPoint Card

R/W

Typical DIOBData line(UDAT 0 -7)

Input

Output

Read“One” Read

“Zero”

Data line voltagewithout bus discharging

Clamp Initiation Delay

UDAT 0-7BUS CLAMP ENABLESignal (TP1)

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3-13. QBE

Current (Supplied by the DIOB)

Group 1: 500 mA maximum

Group 2: 350 mA maximum

Maximum Power Required

Group 1: 6.6 watts

Group 2: 4.6 watts

UCLOCK Signal Static Parameters

Clamp Voltage Supply 0.60 VDC 1.00 VDC

15 VDC Supply 13.5 VDC 16.50 VDC

Table 3-67. QBE +5 VDC to +11 VDC Level Shift Circuit

Min. Max. Condition

Voltage Output VOL Low -0.6 VDC 1.0 VDC IOL = 15.2 mA

Voltage Output VOH High 10.0 VDC IOH = 5.0 mA

Voltage Input VIL Low −0.6 VDC 0.8 VDC

Voltage Input VIH High 2.0 VDC 5.2 VDC

Input Current IIH High 0.10 mA VI = 2.0 VDC

Input Current IIL Low −1.20 mA VI = 0.5 VDC

Table 3-68. QBE +11 VDC to +5 VDC Level Shift Circuit

Min. Max. Condition

Voltage Output VOL Low −0.6 VDC 0.4 VDC IOL = 5 mA

Voltage Output VOH High 5.2 VDC IOH = 0 mA

Table 3-66. QBE Internal Power Supply Voltages (Cont’d)

Minimum Maximum

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3-13. QBE

om

at

hift

3-13.4. Controls and Indicators

Light Emitting Diodes (LED)

The QBE card uses two LEDs shown inFigure3-96. The QBE PWR LED indicates(when lit) that the QBE card fuse is intact and that the card is receiving power frthe DIOB power supply.

The MBU PWR LED indicates (when lit) that the MBU/MSQ card is intact and thDIOB power for the MBU/MSQ card is available.

Jumpers

Jumpers are used to select the Transmit Mode, Receive Mode, or No Level SMode for the DIOB signalUCLOCK. Figure 3-97 throughFigure 3-99 show therequired jumper configurations.

Voltage Output VOH High 2.5 VDC IOH = −8 mA

Voltage Input VIL Low −0.6 VDC 3.0 VDC

Voltage Input VIH High 8.5 VDC

Figure 3-96. QBE Card Components

Table 3-68. QBE +11 VDC to +5 VDC Level Shift Circuit

Min. Max. Condition

Jumpers

LEDsQBE PWR

MBU PWR

5/99 3-207 M0-0053Westinghouse Proprietary Class 2C

Page 274: Ovation Q Line

3-13. QBE

Figure 3-97. QBE Transmit Mode Jumper Configuration

Figure 3-98. QBE Receive Mode Jumper Configuration

C A

JU5 (ITEM 54)

XMIT

OG

NOLEVELSHIFT

OH

UCLOCK

OE RECV

JU5 (ITEM 54)

XM

IT

F

DOB

RE

CV

XMIT

RE

CVJU5

(ITEM 54)

OA

UCLOCKJU5 (ITEM 54)

E RECV FX

MIT

OD

NOLEVELSHIFT

OG

OH

C

B

M0-0053 3-208 5/99Westinghouse Proprietary Class 2C

Page 275: Ovation Q Line

3-13. QBE

1s.

Signal Interface

DIOB signals are input to the QBE card through the DIOB backplane to the Jconnector. Signals are output from the QBE card on the J2 and J3 connectorFigure3-94 shows the location of the J1, J2 and J3 connectors.Table3-69 gives theJ1 connector pin assignments and signal names andTable3-70 gives the J2 and J3connector pin assignments and signal names.

Figure 3-99. QBE No Level Shift Mode Jumper Configuration

Table 3-69. QBE J1 Connector Pin Assignments and Signal Names

Solder Side Signals Card-Edge Pin Numbers Component Side Signals

PRIMARY 1 2 PRIMARY

BACKUP 3 4 BACKUP

GROUND 5 6 GROUND

UADD 0 7 8 UADD 1

UADD 2 9 10 UADD 3

UADD 4 11 12 UADD 5

UADD 6 13 14 UADD 7

HI-LO 15 16 R/W**

UNIT 17 18 DATA-GATE

GROUND 19 20 DEV-BUSY

NOJU5

HG LEVELSHIFT

UCLOCK

O

A

O

E

O

C XMIT

RE

CV

O

B

RECV

O

E

XM

IT

O

D

5/99 3-209 M0-0053Westinghouse Proprietary Class 2C

Page 276: Ovation Q Line

3-13. QBE

UDAT 0 21 22 UDAT 1

UDAT 2 23 24 UDAT 3

UDAT4 25 26 UDAT 5

UDAT6 27 28 UDAT 7

GROUND 29 30 UFLAG

UCAL 31 32 USYNC

UCLOCK* 33 34 GROUND

*UCLOCK is a+5 VDC TTL level signal**Formally signal DATA-DIR.

Table 3-69. QBE J1 Connector Pin Assignments and Signal Names (Cont’d)

Solder Side Signals Card-Edge Pin Numbers Component Side Signals

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Page 277: Ovation Q Line

3-13. QBE

Table 3-70. QBE J2 and J3 Connector Pin Assignments and Signal Names

Solder Side Signals Card-Edge Pin Numbers Component Side Signals

GROUND 1 2 UADD 0

GROUND 3 4 UADD 1

GROUND 5 6 UADD 2

GROUND 7 8 UADD 3

GROUND 9 10 UADD 4

GROUND 11 12 UADD 5

GROUND 13 14 UADD 6

GROUND 15 16 UADD 7

GROUND 17 18 HI-LO

GROUND 19 20 R/W**

GROUND 21 22 UNIT

GROUND 23 24 DATA-GATE

GROUND 25 26 DEV-BUSY

GROUND 27 28 UDAT 0

GROUND 29 30 UDAT 1

GROUND 31 32 UDAT 2

GROUND 33 34 UDAT 3

GROUND 35 36 UDAT 4

GROUND 37 38 UDAT 5

GROUND 39 40 UDAT 6

GROUND 41 42 UDAT 7

GROUND 43 44 UFLAG

GROUND 45 46 UCAL

GROUND 47 48 USYNC

GROUND 49 50 UCLOCK*

*UCLOCK is a+11 VDC CMOS level signal**Formally signal DATA-DIR.

5/99 3-211 M0-0053Westinghouse Proprietary Class 2C

Page 278: Ovation Q Line

3-14. QBI

er to:

3-14. QBI

Digital Input(Style 2840A80G01 through G11)

3-14.1. Description

The QBI card had been superseded by the QID card. For new applications, refthe following table to determine the equivalence between QID and QBI cards

Table 3-71. QBI QID Card Equivalents

QBIGroup

EquivalentQID Group Input Level Inputs

G01 G01 5 VDC 16

G02 G08 12 VDC 16

G03 G09 12 VAC/DC 16

G04 G03 24 VAC/DC 16

G05 G05 48 VAC/DC 16

G06 G05 48 VDC 16

G07 G07 125 VDC 16

G08 G07 120 VAC/DC 16

G09 G09 12 VAC/DC 16

G10 G03 24 VAC/DC 16

G11 G12 120 VAC 16

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Page 279: Ovation Q Line

3-14. QBI

and

ugh

The QBI card provides signal conditioning for 16 digital voltage process inputs,interfaces these signals to the DIOB (seeFigure 3-100). The 16 single-ended(one-wire) inputs share a common line. Eleven different QBI groups (G01 throG11) provide a variety of input voltage ranges (Table 3-72).

3-14.2. Features

The QBI has the following features:

• IEEE surge-withstand protection.

• 500 VDC common mode voltage.

• Separate status indicating LED’s for each input.

• Optional 5V, 12V, 24V, 48V or 120V input ranges.

• Optical isolation for each input.

• Any DIOB controller card can read the QBI.

• The common wire can be connected to either+ or − input supply voltage

Figure 3-100. QBI Block Diagram

5/99 3-213 M0-0053Westinghouse Proprietary Class 2C

Page 280: Ovation Q Line

3-14. QBI

al iso ah

The field signals enter the card through the 16 single-ended inputs. Each signrectified and turns on an optical isolator. The signal is conditioned, latched intbuffer, and upon request, transferred to the DIOB. As data appears at the latcinputs, a LED lights to indicate the digital input status.

Table 3-72. QBI Card Group Specifications

GroupNumber Input Level

Propagation Time(Typical) Common Line Connection

IEEESWC

G01 5 V Logic 0.1 msec +5 VDC No

G02 12 V Logic 0.1 msec +12 VDC No

G03 12 VDC 4 msec +12 VDC Yes

G04 24 VDC 4 msec +24 VDC Yes

G05 48 VDC 4 msec +48 VDC Yes

G06 48 VDC 4 msec 48 VDC RETURN Yes

G07 125 VDC 4 msec 125 VDC RETURN Yes

G08 120 VAC 11 msec – Yes

G09 12 VDC 4 msec 12 VDC RETURN Yes

G10 24 VDC 4 msec 24 VDC RETURN Yes

G11 120 VAC 17 msec – Yes

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Page 281: Ovation Q Line

3-14. QBI

Block Diagram

A functional block diagram of the QBI is shown inFigure 3-101.

3-14.3. Specifications

Input specifications are defined inTable 3-73.

Figure 3-101. QBI Card Functional Block Diagram

Table 3-73. QBI Card Input Specifications

Group

ONInput

Voltage(VDC)

Min/Max

OFFInput

Voltage(VDC)

OFFInput

Current(mA dc)

ONInput

Current(mA dc)Min/Max

PropagationTime

(msec)Min/Max

Power InFront End-All with

UnitsOn, (Nominal Voltage)

(Watts)

G01 4 6 2 0.19 7.75 16.0 – 0.2 1

G02 10 15 2.5 0.19 7.5 16.25 – 0.2 2.3

G03 10 15 2.5 0.19 7.5 16.25 1.1 7.0 2.3

G04 20 30 3 2.0 8.0 16.0 1.1 7.0 4.6

G05 40 60 4 0.35 8.5 16.75 1.1 7.0 9.2

JumperAddressSelection

Add

ress

Com

para

tor

Car

d E

dge

Indi

cato

rs

Sig

nal

Con

ditio

ning

Opt

ical

Cou

plin

gA

nd R

-cF

ilter

ing

2:1

Mul

tiple

xer

Bus

Driv

ers

Point 15

Point 0

CircuitCommon

16 16

16

SelectHi-lo1

DIOB

Add

ress

Data-dir

Enable

1

8(16)

DIOBGround

Dat

a

5/99 3-215 M0-0053Westinghouse Proprietary Class 2C

Page 282: Ovation Q Line

3-14. QBI

Group Characteristics

Refer to the following table.

Power Supply

Primary: +13 VDC + 0.1 VDC

G06 40 60 4 0.35 8.5 16.75 1.1 7.0 9.2

G07 100 150 6 0.5 7.0 14.2 1.1 7.0 19.0

G08 100* 150* 6* 0.8* 7.0* 14.2* 2.5 30.0 19.0

G09 10 15 2.6 0.17 7.75 16.25 1.0 7.0 2.3

G10 20 30 3 2.0 8.0 16.0 1.1 7.0 4.6

G11 100* 150* 26.0* 0.8* 6.0* 2.5* 5.5 43.0 19.0

Notes* VAC RMS or mA ac RMS as indicated

Group Description

1 5 VDC logic with+5 VDC common line connection (0.1 msec propagation),

2 12 VDC logic with+12 VDC common line connection (0.1 msec propagation).

3 12 VDC logic with+12 VDC common line connection (4 msec propagation).

4 24 VDC logic with+24 VDC common line connection (4 msec propagation).

5 48 VDC logic with+48 VDC common line connection (4 msec propagation).

6 48 VDC with 48 VDC return common line connection (4 msec propagation)

7 125 VDC with 125 VDC return common line connection (4 msec propagation).

8 120 VAC (11 msec propagation).

9 12 VDC with 12 VDC return common line connection (4 msec propagation).

10 24 VDC with 24 VDC return common line connection (4 msec propagation).

11 120 VAC high threshold (17 msec propagation).

Table 3-73. QBI Card Input Specifications (Cont’d)

Group

ONInput

Voltage(VDC)

Min/Max

OFFInput

Voltage(VDC)

OFFInput

Current(mA dc)

ONInput

Current(mA dc)Min/Max

PropagationTime

(msec)Min/Max

Power InFront End-All with

UnitsOn, (Nominal Voltage)

(Watts)

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Page 283: Ovation Q Line

3-14. QBI

e

Backup: +12.6 VDC+0.2 VDC

Current: 200 mA (maximum) supplied by DIOB

Electrical Environment

IEEE Surge withstand capability (not available on G01 and G02).

Common Mode Voltage: 500 VDC or peak ac (line frequency)

3-14.4. Card Addressing and Data Output

The QBI card address is established by eight jumpers on the front card-edgeconnector as shown inFigure3-102. The insertion of a jumper encodes a “1” on thaddress line.

Connections and Field Cabling

The digital inputs enter the QBI card on the front-edge connector. The pinassignments for the connector are listed inTable 3-74.

Figure 3-102. Example of a QBI Card Address Jumper Assembly

Table 3-74. QBI Card Front-Edge Connector Pin Allocations

Input Digital Bit Number PC Card Edge PinField Terminal Block Terminal

Number

B15 17B 17

A7 = 0

A6 = 0

A5 = 1

A4 = 0

A3 = 0

A2 = 0

A1 = 1

A0 = 1

Blank:

Blank:

Jumper:

Blank:

Blank:

Blank:

Jumper:

Jumper:

Card-edge Connector(Front View)

Card Address = 00100011(X' 23')

5/99 3-217 M0-0053Westinghouse Proprietary Class 2C

Page 284: Ovation Q Line

3-14. QBI

e

Figure3-103 throughFigure3-106 show typical wiring to the various groups of thQBI card.

Note

The common terminal (terminal 1) for G01, G02,G03, G04, and G05 is tied to the positive supplyvoltage. The common terminal (terminal 1) is tied tothe negative supply voltage for G06, G07, G09 andG10. G08 and G11 are used for AC inputs and thecommon terminal is tied to one of the 120 VACsupply leads.

B14 17A 16

B13 15B 15

B12 15A 14

B11 13B 13

B10 13A 12

B9 11B 11

B8 11A 10

B7 9B 9

B6 9A 8

B5 7B 7

B4 7A 6

B3 5B 5

B2 5A 4

B1 3B 3

B0 3A 2

Common or Return 1A and 1B

Table 3-74. QBI Card Front-Edge Connector Pin Allocations (Cont’d)

Input Digital Bit Number PC Card Edge PinField Terminal Block Terminal

Number

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Page 285: Ovation Q Line

3-14. QBI

by:

Field Cable Length

When 120 VAC is used to wet contacts (G08 and G11), cable length is limited

Cable Stray Capacitance: 15,000 pF (maximum)

Stray Capacitance: 50 pF/ft. (typical)

Maximum Cable Length: 250 ft.

Figure 3-103. Typical G01 and G02 QBI Card – Point Wiring Diagram

Logic VoltageG01G02

5 V12 V

POINT 0

COMMON

POINT 15

QB1G01 and G02

16

LogicVoltage

+-

5/99 3-219 M0-0053Westinghouse Proprietary Class 2C

Page 286: Ovation Q Line

3-14. QBI

Figure 3-104. Typical G03, G04 and G05 QBI Card – Point Wiring Diagram

Figure 3-105. Typical G06, G07, G09 and G10 QBI Card – Point Wiring Diagram

M0-0053 3-220 5/99Westinghouse Proprietary Class 2C

Page 287: Ovation Q Line

3-14. QBI

card

3-14.5. Controls and Indicators

Separate status-indicating LEDs for each input are located at the front of the (seeFigure 3-107).

Figure 3-106. Typical G08 and G11 QBI Card – Point Wiring Diagram

Figure 3-107. QBI Card Components

LEDs

76543210

15141312111098

LED Detail

PWR

5/99 3-221 M0-0053Westinghouse Proprietary Class 2C

Page 288: Ovation Q Line

3-14. QBI

3-14.6. Installation Data Sheet

1 of 1

Installation Notes (Refer to Figure 3-108):

Figure 3-108. QBI Wiring Diagram

Group TP Bus - Black (QBI -1A) TP Bus - Red (QBI -19B)

3 + 12 V + 12 V Return

4 + 24 V + 24 V Return

5 + 48 V + 48 V Return

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

3/4 A18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTOR CUSTOMER CONNECTIONS

INTERNALBUS STRIP

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

5A

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

BLACK RED

~+ −

TP BUS

M0-0053 3-222 5/99Westinghouse Proprietary Class 2C

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3-14. QBI

6 48 V Return + 48 V

7 125 V Return + 125 V

8 120 VAC (Hot) 120 VAC (Neutral)

9 12 V Return 12 V

10 24 V Return 24 V

11 120 VAC (HOT) 120 VAC (Neutral)

Group TP Bus - Black (QBI -1A) TP Bus - Red (QBI -19B)

5/99 3-223 M0-0053Westinghouse Proprietary Class 2C

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3-15. QBO

trbit

3-15. QBO

Digital Output(Style 2840A79G01 through G05 )

3-15.1. Description

G01 through G05 are applicable for use in the CE MARK Certified System

The QBO card receives DIOB signals and provides up to 48 VDC, 300 mA,field-level signals for relay coils, stepping motors, lamps, etc., within the planenvironment (seeFigure 3-109). This card contains 16 current sinking transistooutputs with a common return line. An on card read/write latch provides an 8-memory function. This card also contains switch-selectable dead-computertime-out and flasher circuitry.

Figure 3-109. QBO Block Diagram

AddressDecoder

Card-EdgeLED

Indicators

CurrentSinkingDrivers

Data AddressDIOB

...

RTN0 15

Source

Field Process Outputs

OpticalIsolators

Flash/Non-Flash

Select

DataLatch

BusDrivers

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3-15. QBO

of

and

e of

the

e of

ard

3-15.2. Features

This card provides the following features:

• IEEE surge-withstand protection

• Read/write output data operation

• On-card power-up, bus, and dead-computer time-out resets

• Card-edge LED indicator for each output

• Optional flashing output to drive field process lamps

• Switch-selectable time-out periods

• Switch-selectable flasher periods

• Compatible with any DIOB controller

The QBO card is available in five groups (G01 through G05), offering a varietyoutput parameters.

• G01 provides a high-voltage output and a capability of flashing the outputvarying the dead computer timeout

• G02 has high-voltage outputs with steady operation (no flash) and a set valu62 msec for timeout

• G03 provides logic outputs and is capable of flashing the output and varyingtimeout

• G04 has logic level outputs with steady operation (no flash) and a set valu62 msec for timeout

• G05 is the same as G03 except that a 10 kΩ on card pull-up resistor is connectedbetween pins 19A and 19B.

The QBO Card complies with the DIOB interface design specifications. This cmay be used in a Q-crate assembly.

5/99 3-225 M0-0053Westinghouse Proprietary Class 2C

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3-15. QBO

Block Diagram

A functional block diagram of the QBO is shown inFigure 3-110.

Figure 3-110. QBO Detailed Block Diagram

ADDRESSDATA

PO

WE

R-

UP

CA

RD

RE

FR

ES

H

COMPARE

EIG

HT

FR

ON

T C

ON

NE

CTO

RJU

MP

ER

AR

RA

NG

EM

EN

T

LAT

CH

RE

SE

TO

R

EIG

HT

UN

IT

LATCH

OPTICAL

FLASH/

CURRENT

ISOLATORS

NON-FLASHSELECTION

SINKINGDRIVERS

DRIVERS

LED’s

ON

E B

IT E

NA

BLE

,T

WO

BIT

S R

ATE

ON

E B

IT D

UT

Y C

YC

LE

TH

RE

E B

ITS

RAT

E S

ELE

CT,

ON

E B

IT D

ISA

BLE

/EN

AB

LE

SU

PP

LY

PO

INT

15

PO

INT

0

(CLA

MP

)

(16)

4

~ ~

RE

TU

RN

(16)

4

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3-15. QBO

3-15.3. Specifications

Output Capabilities

Power Supply

• Primary: +13 V +0.1 VDC

• Backup: +12.6 V+ 0.2 VDC

• Current: 250 mA (maximum) supplied by DIOB

Electrical Environment

IEEE Surge withstand capability

Common Mode Voltage: 500 VDC or peak AC (line frequency)

Parameter G01 and 2 G03, 4, and 5

OFF Voltage 60 VDC (maximum) 20 VDC (maximum)

OFF Current .5 mA (maximum) .1 mA (maximum)

ON Voltage 2 VDC (maximum) .5 VDC (maximum)

ON Current 300 mA (maximum) 16 mA (maximum)

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3-15. QBO

edge

3-15.4. Card Addressing

The QBO card address is established by eight jumpers on the top, front, card-connector. The insertion of a jumper encodes a “1” on the address line(Figure 3-111).

Figure 3-111. QBO Card Address Jumper Assembly

JUMPER:

JUMPER:

BLANK:

BLANK:

JUMPER:

BLANK:

JUMPER:

BLANK:

CARD ADDRESS =A7 = 1

A6 = 1

A5 = 0

A4 = 0

A3 = 1

A2 = 0

A1 = 1

A0 = 0

11001010(X ‘CA’)

CARD EDGE CONNECTOR(FRONT VIEW)

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3-15. QBO

e

Field Connections

Figure 3-112 shows typical field wiring for a QBO card. The digital outputs arbrought out on the front edge of the card. The contact allocations are listed inTable 3-75.

Note

The QBO may be used to drive the coils ofinterposing relays. These relay contactsmay be connected to the AC mains. For CEMark certified systems, field wiring thatcarries the AC mains must have doubleinsulation.

Figure 3-112. QBO Typical Point Wiring

Load 15

Load 0

PowerSupply (16)

Io

Io

Ir (Max) = 16 X Io

Supply

Point 15

Point 0

Return

~~

+

QBO

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3-15. QBO

Table 3-75. QBO Digital Output Contact Allocations

Output Digital Bit No. P-C Card Edge Pin No.Field Terminal Block Terminal

No.

SUPPLY CLAMP 19A and B 18

B15 17B 17

B14 17A 16

B13 15B 15

B12 15A 14

B11 13B 13

B10 13A 12

B9 11B 11

B8 11A 10

B7 9B 9

B6 9A 8

B5 7B 7

B4 7A 6

B3 5B 5

B2 5A 4

B1 3B 3

B0 3A 2

RETURN 1A and B 1

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3-15. QBO

theand

s set

3-15.5. Controls and Indicators

Separate LEDs for each output are located at the front of the card to indicatestatus of each output. The flash option is available on G01, G03, and G05. G02G04 cards have a steady only operation

If the QBO card is not periodically updated, the card resets. The update period iby four DIP switches as given inTable 3-76 and shown inFigure 3-113.

Figure 3-113. QBO Card Components

Table 3-76. QBO Card Reset Switch Position

Dip SwitchReset TimeA B C D

0 0 0 0 62 ms+ 20%

0 0 1 0 125 ms+ 20%

0 1 0 0 250 ms+ 20%

0 1 1 0 500 ms+ 20%

1 0 0 0 1 sec+ 20%

1 0 1 0 2 sec+ 20%

1 1 0 0 4 sec+ 20%

1 1 1 0 8 sec+ 20%

X X X 1 No time out, data latched (X = don’t care)

LEDs

Output FlashSwitch

UpdatePeriodSwitch

A B C D

ABCD

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3-15. QBO

t the

For the QBO card groups that have optional output flashing, DIP switches selecrate at which the outputs are turned on and off.Table 3-77 lists the DIP switchpositions and available selections. QBO card components are shown inFigure 3-113.

Table 3-77. QBO DIP Switch Positions

Switch A

Switch B, C = Result

Switch DSwitch B Switch C

0, open = output steady1, closed = output

flashing

0011

0 = 5 flashes/sec1 = 2.5 flashes/sec0 = 1.25 flashes/sec1 = 0.625 flashes/sec

0 = 33% ON, 67% OFF1 = 67% ON, 33% OFF

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3-15. QBO

3-15.6. Installation Data Sheet

1 of 2

Figure 3-114. QBO Wiring Diagram

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

Card 3/4 A

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

Terminal Block#6-32 Screw

Half Shell Extension(B-block)

Edge-connectorCustomer Connections Internal

Bus Strip

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

Bit 0

Common

Load

20

19

20

19

External Power Supply

- +

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3-15. QBO

For CE MARK Certified System

2 of 2

Figure 3-115. QBO CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

20

PE

20

PE

19

20

19

20

-

+External Power

18 .75A

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3-16. QCA

Thes

revingheto

the

euce

andhe

3-16. QCA

Current Amplifier(Style 3A99118G01 through G02)

3-16.1. Description

Groups 01, 02 are applicable for use in the CE MARK Certified System

The Q-Line Current Amplifier (QCA) card provides variable offset and currentamplification stages for Q-line servo driver cards used to drive EH actuators. card is strictly an analog card where the DPU does not interact with the card'function or status.

Two channels are available on the QCA. The input to each channel is anotheQ-card's actuator position request (Coil Drive Output) wired into the front-edgconnector. Two outputs are available for each QCA channel. For an actuator haredundant coils, both channel outputs (Coil Drive A and B) are used to drive tcoils. Otherwise, only one of the channel outputs (Coil Drive A) is necessary drive the actuator.

Before a QCA channel can drive an actuator, it must be calibrated according toactuator position request coming from a Q-line servo driver card that is to beamplified by the QCA. By adjusting potentiometers and selecting resistors, thappropriate offset and current amplification is applied to the input signal to prodthe desired coil drive signal range.

The current boosting stage for each channel of the QCA is powered by + 21V- 21V on board DC-DC converters derived from the +13V backplane supply. Ttwo on-board supplies are not isolated from DIOB ground.

The QCA is assembled to provide two groups:

Group 1 Group 2

Input Voltage 0 to -10V 0 to -10V

Output Voltage 0 to 12.5V

Maximum Output Current Drive(per coil drive)

400mA 250mA

Maximum Load Resistance(per coil drive)

50 ohms

Maximum Total Current Drive(all channels combined)

800mA 500mA

Channel Configuration voltage input, voltage output,two channels, redundant outputs

on each channel

voltage input, true currentoutput, two channels, non-redundant channel outputs

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3-16. QCA

3-16.2. Features

The QCA card is available in two groups and provides the following features:

• Two channels configured as voltage inputs

• Redundant voltage outputs (Group 1)

• Non-redundant true current outputs (Group 2)

• Maximum current drive capability:

— 400mA per Group 1 channel

— 250mA per Group 2 channel

— 800mA total, all channels combined

• Outputs are NOT isolated from DIOB ground

3-16.3. Specifications

Power Requirements

DIOB Supply Voltage: +12.4 VDC to 13.1 VDC

Current (supplied by DIOB): 2.5A typ 3.0A max for Groups 1 and 2 undermaximum load conditions

Input Stage (See Figure 3-116 and Figure 3-117)

Actuator Position Request Range (Vin): -12V to +12V

Range Adjustment Stage (See Figure 3-116 and Figure 3-118)

Resistor Ladder: RA2 + RB≥ 2KΩ

Output Voltage Range: adjust V2 to fall within -12V to +12V.

Offset Adjustment Stage (See Figure 3-116 and Figure 3-119)

Resistor Ladder: RC2 + RD≥ 2KΩOffset Voltage Range: adjust V3 to fall within 0 to -12V

Output Voltage Range: adjust V4 to fall within -12V to +12V

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3-16. QCA

in

asrs:

ch

Output Gain Stage (See Figure 3-116, Figure 3-120, and Figure 3-121)

Output Voltage of Control Amp: adjust gain of booster amp so that V5 falls with- 12 to + 12V

Output Voltage of Booster Amp:±15V max

Closed Loop Gain (Group 1 only):

Choose Rf-B so that the overall loop gain (Vout/V4) is 1 to 5 V/V, keeping close to unity gain as possible. When selecting Rf-B, use precision resistoWestinghouse drawing number - 669A664.

Output Coil Drives - Group 1 (See Figure 3-116 and Figure 3-120)

Tolerance: may be adjusted to desired value initially

Voltage Output Temperature Coefficient:±200 ppm/oC (±0.02%/oC) over thetemperature range 0-60oC

Tracking Accuracy:±0.3% between a channel's redundant outputs at roomtemperature

Tracking Temperature Coefficient: 30 ppm/oC between redundant output over thetemperature range 0 - 60oC

Maximum Load Current:±400mA per channel (If redundant drives are used, eacoil drive can drive up to 200mA each.)

Output Coil Drives - Group 2 (See Figure 3-116 and Figure 3-121)

Tolerance: may be adjusted to desired value initially

Current Output Temperature Coefficient:±400 ppm/oC (±0.02%/oC) over thetemperature range 0-60oC

Maximum Load Current:±250mA per channel

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3-16. QCA

ctorn

. Alllly

essed

3-16.4. Signal Interface

DIOB Connector

The QCA draws power from the DIOB bus through a 34 pin card-edge conneon the DIOB backplane. The card-edge DIOB signal assignments are given iTable 3-78.

Field/Addressing Connector

The front card edge of the QCA provides the connections to the field deviceswires to the front-edge connector must be of 18 AWG wiring to support potentiahigh current draw. There are no card addressing pins since the card is not accby the DPU.

Note

For the QCA, no points on the half-shell or in the fieldat the actuator coil should be tied to earth ground. AllGROUND points inTable 3-79 are DIOB ground.

Table 3-78. QCA DIOB Card Edge Connector Pinout

Signal NameComponent Side Pin # Pin # Signal Name

Solder Side

PRIMARY +V 2 1 PRIMARY +V

BACKUP +V 4 3 BACKUP +V

GROUND 6 5 GROUND

No Connection 8 7 No Connection

No Connection 10 9 No Connection

No Connection 12 11 No Connection

No Connection 14 13 No Connection

No Connection 16 15 No Connection

No Connection 18 17 No Connection

No Connection 20 19 GROUND

No Connection 22 21 No Connection

No Connection 24 23 No Connection

No Connection 26 25 No Connection

No Connection 28 27 No Connection

No Connection 30 29 No Connection

No Connection 32 31 No Connection

GROUND 34 33 No Connection

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3-16. QCA

Table 3-79. QCA Field Front Card Edge Connector

Signal Name Component Side Pin # Pin # Signal Name Solder Side

No Connection 28B 28A No Connection

No Connection 27B 27A No Connection

No Connection 26B 26A No Connection

No Connection 25B 25A No Connection

No Connection 24B 24A No Connection

No Connection 23B 23A No Connection

No Connection 22B 22A No Connection

No Connection 21B 21A No Connection

No Connection 20B 20A No Connection

No Connection 19B 19A GROUND

No Connection 18B 18A No Connection

No Connection 17B 17A No Connection

No Connection 16B 16A No Connection

COIL DRIVE 2B * 15B 15A GROUND

No Connection 14B 14A No Connection

GROUND 13B 13A COIL DRIVE 2A

No Connection 12B 12A No Connection

VIN2 11B 11A GROUND

No Connection 10B 10A No Connection

GROUND 9B 9A COIL DRIVE 1B *

No Connection 8B 9A No Connection

COIL DRIVE 1A 7B 7A GROUND

No Connection 6B 6A No Connection

GROUND 5B 5A VIN1

No Connection 4B 4A No Connection

No Connection 3B 3A No Connection

No Connection 2B 2A No Connection

GROUND 1B 1A No Connection

* For Group 2 (True Current Output) these signals areNo Connection.

VIN = Actuator Position Request

COIL DRIVE 1A, 1B = redundant outputs of channel 1 (1B available only on Group 1 boards)

COIL DRIVE 2A, 2B = redundant outputs of channel 2 (2B available only on Group 1 boards)

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3-16. QCA

atoront-ededr as

als,

nd

aged to

3-16.5. Operation

QCA Channel

Figure3-116 shows a block diagram of the stages in a QCA channel. The actuposition request (Vin) comes to the QCA from servo driver cards through the fredge connector. Once the signal is adjusted to the voltage and current levels neto drive the actuator, it is sent out to the field through the front-edge connectothe coil drive signal.

Input Stage

Figure3-117 shows the input stage in a QCA channel. For voltage level Vin signRin is 20kΩ, drawing minimal current from the input and keeping the input fromfloating if Vin is not connected to the channel.

Input inversion is used when the actuator position request range is unipolar aopposite in sign of the desired unipolar output drive range. For example, theactuator position request range may be 0 to -10V, and the desired output voltrange may be 0 to 12V. In this case, the input inverting jumper should be enableachieve an output of correct polarity (seeFigure 3-122).

Figure 3-116. QCA Channel

Figure 3-117. QCA Channel Input Stage

InputStage

V1 RangeAdjustment

Stage

V2V4

-10Vref

OutputGainV4Stage

Coil Drive A (voltage or current output)

Coil Drive B (voltage output only)

VinOffset

AdjustmentStage

-

+

Rin -

+

Unity Gain Inverter

Invert Input Jumper

Disable

EnableV1

10K10KVin

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3-16. QCA

djusttionecs)

nge., for

rding

Range Adjustment Stage

Figure3-118 shows the range adjustment stage in a QCA channel. The range astage sets the base range of the output drive signal and allows the input posisignal range to be converted to meet any current driving range (within card spfor a variety of actuators. An adjustable voltage divider determines the signal raThe final output signal range is a result of the range and gain stages combinedthe gain stage magnifies the base range by an adjustable gain multiplier.

RA1 is a potentiometer which enables precise adjustment of signal range accoto the following equation:

V2 = V1 * (RB/(RA1 + RA2 + RB))

Figure 3-118. QCA Channel Range Adjustment Stage

-

+

RB

V2V1

RA2RA1

1K

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3-16. QCA

juststablenalll

s(see

to be

:

Offset Adjustment Stage

Figure3-119 shows the offset adjustment stage in a QCA channel. The offset adstage handles bipolar and unipolar signal adjustments. This stage adds an adjuoffset which can translate a bipolar input signal into a unipolar servo drive sig(required by certain valves). This stage may also be configured to add in smaoffsets to unipolar signals to ensure the signal does not cross over 0V to anundesired signal polarity. If no offset is required, offset addition to the signal ibypassed by installing the channel's Offset jumper in the DIS (disable) positionFigure 3-122). Do NOT pull out RC1, RC2, or RD to disable offset.

Adjustment of the potentiometer RC1 enables precise adjustment of the offsetadded to the signal according to the following equation:

V3 = -10Vref * (RD/(RC1 + RC2 + RD))

The offset adjustment stage has unity gain resulting in the following equation

V4 = V3 - V2

Figure 3-119. QCA Channel Offset Adjustment Stage

Offset

Disable

Enable

-

+

-

+V3

V4V2

10K10K

10K10K

Jumper

Unity GainDifferentialAmplifierRD

-10VrefRC2RC1

50K

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3-16. QCA

1

Output Gain Stage - Voltage Output Configuration (Group 1 only)

The following closed loop gain equation applies to the output stage of Group boards illustrated inFigure 3-120:

Vout = -V4 * Rf/Riwhere Rf= Rf-A + Rf-B

Figure 3-120. QCA Output Gain Stage - Group 1

-

+

V4

Ri-

+V5

10K20K

ControlAmp

Rf-A Rf-B

2Ω VoutCoil Drive A

To Coil Drive B Circuitry (same as Coil Drive A above)

BoosterAmp

10K

Rout

10K

Rf

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3-16. QCA

2

nel

Output Gain Stage - Current Output Configuration (Group 2 only)

The following closed loop gain equation applies to the output stage of Group boards illustrated inFigure 3-121:

Iout = -(V4/Rout)*(Rf/Ri) = -V4/Rout

Ri = closely matched input resistors

Rf = closely matched feedback resistors

Rout = 8.25 ohms

Channel Configuration Examples

Unipolar Voltage In - Unipolar Voltage Out (Group 1)

This section contains calculations for selecting resistors for the following chanspecifications:

• Input Voltage: 0 to -10V

• Output Voltage: 0 to 12.5V

• Load Resistance: 50 ohms

1. Enable the invert jumper (shown inFigure3-122) since the input voltage sign isopposite from the output voltage sign.

Figure 3-121. QCA Output Gain Stage - Group 2

-

+

V4

Ri-

+V5

10K

ControlAmp

Rout

VoutCoil Drive A

BoosterAmp

Ri’ 10K

Rf’

10K

20K

Rf

10K

8.25Ω10K

Iout

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3-16. QCA

tagegain

.

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nel

2. Since the magnitude of the input must be gained up to get the full output volrange, the output gain stage will need a gain greater than 1. Set the outputstage to a gain of 2. This means Rf-B is 10KΩ (seeFigure 3-120).

3. Referring toFigure 3-120:

Vout MAX = 12.5VVout, booster amp MAX = 12.5V + (Rout)*(Iout) = 12.5V + (2Ω)*(250mA) = 13V

which is less than the maximum 15V allowed.

4. If the output stage has a gain of 2, V4 inFigure3-119 has the range: 0 to -6.25VAssume no offset is needed (Offset jumper in DIS position), so the offsetadjustment stage is a unity gain inverting stage which means V2 = 0 to 6.25

5. Since V2 = 0 to 6.25V and V1 = 0 to 10V (after the actuator position requestbeen inverted), V2 = 0.625*V1. This implies that:

RB/(RA1 + RA2 + RB) = 0.625

Let RA1 = 1k potentiometer, RA2 = 4.53K, and RB = 7.96k. By adjusting t1k potentiometer, the ratio of resistors falls between 0.590 and 0.637 whicincludes the desired 0.625 ratio.

6. The offset adjustment stage may be used to add a small offset to the valvposition request to make sure the output voltage is always positive. If a 1050 mV offset is desired:

RD/(RC1 + RC2 + RD) = 0.001 to 0.005

Let RC1 = 50k potentiometer, RC2 = 9.76k, and RD = 50 ohms. By adjustthe 50k potentiometer, the ratio of resistors falls between 0.0008 and 0.00When multiplied by 10Vref, the desired 10 to 50mV offset is added to the sig

Unipolar Voltage In - Unipolar Current Out (Group 2)

This section contains calculations for selecting resistors for the following chanspecifications:

• Input Voltage: 0 to -10V

• Output Current: 0 to 250mA

• Load Resistance: 50Ω

1. Enable the invert jumper (shown inFigure3-122) since the input voltage sign isopposite from the output current sign.

2. Referring toFigure 3-121:

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3-16. QCA

nd

06V.

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Kch

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geiching

Vout (booster amp MAX) = (Rload + Rout)*(Iout) = (50Ω + 8.25Ω) * 250mA = 14.56Vwhich is less than the maximum 15V allowed.

The output stage has unity gain where Rf = Ri. Since Rout is 8.25 ohms aIout = 0 to 250mA:

V4 = 0 to -2.06V

3. Assume no offset is needed (Offset jumper in DIS position), so the offsetadjustment stage is a unity gain inverting stage which implies V2 = 0 to 2.

4. Since V2 = 0 to 2.06V and V1 = 0 to 10V (after the valve position requestbeen inverted), V2 = 0.206*V1. This implies that:

RB/(RA1 + RA2 + RB) = 0.206

Let RA1 = 1K potentiometer, RA2 = 7.5K, and RB = 2K. By adjusting the 1potentiometer, the ratio of resistors ranges between 0.190 and 0.267, whiincludes the desired 0.625 ratio.

Calibration

To calibrate a QCA card, adjust the range and offset potentiometers on the frontedge while the output voltage or current is monitored. Since channel output drcannot be disconnected on power-up and potentiometer settings may be unkinitially, it is suggested that outputs be disconnected from the actuators initialInstead, a resistor (approximately equal to coil load resistance) of sufficient porating may be connected to the output at the halfshell on power-up, and thepotentiometers may be adjusted to safe operating values.

Note

Group 2 boards which have true current outputs,should have a load on the output when powered up. Ifno load is present and V4 (seeFigure 3-119) has aslight voltage present due to the input voltage or theoffset voltage, the output will saturate because thechannel is trying to drive a preset current into aninfinite load.

The following calibration steps apply to unipolar voltage input to unipolar voltaor current output QCA boards. Steps are included to add in a small offset whkeeps the output coil drive from crossing over the 0V or 0A boundary and switchpolarities, if this is a necessary constraint.

1. Disable the offset jumper (seeFigure 3-122).

M0-0053 3-246 5/99Westinghouse Proprietary Class 2C

Page 313: Ovation Q Line

3-16. QCA

eter) or

p 1)tory,

eter

2. Send the full scale actuator position request, and adjust the range potentiomon the front card edge for the channel being calibrated until Vout (Group 1Iout (Group 2) equals the desired full scale output for the channel.

3. Send the bottom of scale actuator position request and check if Vout (Grouor Iout (Group 2) is at the desired bottom of scale. If the output is satisfacthen calibration is done.

4. If offset is needed, enable the offset jumper and adjust the offset potentiomuntil Vout (Group 1) or Iout (Group 2) is acceptable and return to Step 2.

5/99 3-247 M0-0053Westinghouse Proprietary Class 2C

Page 314: Ovation Q Line

3-16. QCA

3-16.6. Controls and Indicators

Figure 3-122. QCA Card Outline and User Controls

RV

1O

S2

LEDS

+Vs

LE1

TP

4

R39

R50

-Vs

LE2

R16

2R

159

R16

3R

160

RV

2R

G2

RV

3O

S1

RV

4R

G1

JS9

OF

FS

ET

2

EN

JS10

OF

FS

ET

1

DIS

TP

11C

HA

N2

TP

12G

ND

TP

13C

HA

N1

JS5

PO

WE

R(-

)

-15V

JS8

-VS

GN

D TP

9

GN

D TP

10

JS3

PO

WE

R(+

)

+15

V

JS4

+V

S

JS1

INV

ER

T2

EN

JS2

INV

ER

T1

DIS

VC

OIL

2B

TP

7 VC

OIL

1B

TP

8

VB

OO

ST

2

TP

3R

AN

GE

2

TP

6V

BO

OS

T1

TP

5R

AN

GE

1

GN

D TP

1R

57

R54

GN

D TP

2R

60

R43 R47

R44

M0-0053 3-248 5/99Westinghouse Proprietary Class 2C

Page 315: Ovation Q Line

3-16. QCA

nnel

nnel

l 1),

LED Indicators

+VS: lit when +21V on-board supply is alive

-VS: lit when -21V on-board supply is alive

Plug-in Resistors

Potentiometers

Range Adjustment Potentiometer RA1: used to adjust the signal range of a chaduring calibration.

Channel 1 - Reference Designator RV4; Label RG1

Channel 2 - Reference Designator RV2; Label RG2

Offset Adjustment Potentiometer RC1: used to adjust the signal offset of a chaduring calibration.

Channel 1 - Reference Designator RV3; Label OS1

Channel 2 - Reference Designator RV1; Label OS2

Test Jacks

CHANx - test jack providing Vcoil Drive A output voltage of channel x to bemonitored during calibration. (x = 1,2) Reference Designators: TP13 (channeTP11 (channel 2)

GND - test jack providing signal ground. Reference Designator: TP12

Table 3-80. QCA Plug-in Scaling Resistor Reference Designators

Channel Range Adjust Resistors Offset Adjust Resistors *Gain Adjust Resistors (Rf-B)

#1 RA2: R54RB: R60

RC2: R160RD: R163

DriveA - R44DriveB - R47

#2 RA2: R50RB: R57

RC2: R159RD: R162

DriveA - R43DriveB - R39

* Group 1 Only

5/99 3-249 M0-0053Westinghouse Proprietary Class 2C

Page 316: Ovation Q Line

3-16. QCA

orLT

in

rivesnce

Jumpers

POWER(+): Always set jumpers to +15V position.DEFAULT Group 1 and 2: +15V position

POWER(-): Always set jumpers to -15V position.DEFAULT Group 1 and 2: -15V position

OFFSET: If jumper set to EN (enable), offset is added to the channel’s actuatposition request. When set to DIS (disable), no offset is added. DEFAUGroup 1 and 2: DIS position

INVERT: If jumper is set to EN, the channel actuator position request is invertedthe input stage. DEFAULT Group 1 and 2: EN position

Test Points

Test points appear at the output of those stages denoted by V2, V4, and Coil Din Figure 3-116. These test points plus the ground test points with their referedesignators are listed inTable 3-82 for each channel.

Table 3-81. Reference Designators for QCA Jumpers - Groups 1 and 2

Channel Offset Invert *Power(+) *Power(-)

#1 JS10 JS2 JS3JS4

JS5JS8

#2 JS9 JS1

* Note: Power (+) and (-) jumpers are not channel specific

Table 3-82. QCA Test Point Reference Designators

Channel Range AdjustStage Output

Offset AdjustStage Output

Gain AdjustStage Output Ground

#1 TP5 TP6 DriveA: TP13*DriveB: TP8

TP1, TP2, TP9,TP10, TP12

#2 TP3 TP4 DriveA: TP11*DriveB: TP7

* Group 1 Only

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Page 317: Ovation Q Line

3-16. QCA

3-16.7. Installation Data Sheets

1 of 3

Figure 3-123. QCA Wiring Diagram (Group 1)(Using AMP-18 conductor 18 AWG wiring) (3A99512)

+

- Channel 2 Primary VoltageOutput Coil Drive

Channel 2 Voltage Input

Channel 1 Voltage Input

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

QCA Card

TERMINAL BLOCK

EDGE-CONNECTOR

+

+

+

+

+

-

-

-

-

-

Channel 2 Redundant VoltageOutput Coil Drive

Channel 1 Redundant VoltageOutput Coil Drive

Channel 1 Primary VoltageOutput Coil Drive

Vcoil 2B

Vcoil 2A

Vin 2

Vin 1

Vcoil 1B

Vcoil 1A

5/99 3-251 M0-0053Westinghouse Proprietary Class 2C

Page 318: Ovation Q Line

3-16. QCA

Installation Data Sheet

2 of 3

Figure 3-124. QCA Wiring Diagram (Group 2)(Using AMP-18 conductor 18 AWG wiring) (3A99512)

+

- Channel 2 True CurrentCoil Drive

Channel 2 Voltage Input

Channel 1 Voltage Input

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

QCA Card

TERMINAL BLOCK

EDGE-CONNECTOR

+

+

+

-

-

-

Channel 1 True CurrentCoil Drive

Vcoil 2A

Vin 2

Vin 1

Vcoil 1A

M0-0053 3-252 5/99Westinghouse Proprietary Class 2C

Page 319: Ovation Q Line

3-16. QCA

For CE MARK Certified System

3 of 3

Figure 3-125. QCA CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

Vin1

Ground

Coil drive 1A

Ground

Ground

Ground

Ground

Ground

Coil drive 1B

Vin2

Coil drive 2A

Coil drive 2B

Notes

1. The A and B cabinetsMUST be bolted together touse the QCA in CE Mark Certified Systems.

2. As shown, the shields and grounds must beconnected together and to earth ground at the Bcabinet.

5/99 3-253 M0-0053Westinghouse Proprietary Class 2C

Page 320: Ovation Q Line

3-17. QCI

ntheof

3-17. QCI

Contact Input(Style 7379A06G02)

3-17.1. Description

Group 02 is applicable for use in the CE MARK Certified System

The QCI provides 16 digital contact inputs and a+48 V contact-wetting supplyvoltage (seeFigure3-126). This contact-wetting voltage provides supply isolatioand reduced current power consumption due to the current limiting capability ofsupply. The QCI digitally filters the contact-input signals and provides the optioninverting the polarity of any data bit.

Figure 3-126. QCI Block Diagram

M0-0053 3-254 5/99Westinghouse Proprietary Class 2C

Page 321: Ovation Q Line

3-17. QCI

onon

3-17.2. Features

The QCI card is available in two groups and provides the following features:

• Dual on-card contact-wetting power supply for low power consumption

• Separate status-indicating LEDs for each input

• Compatible with any DIOB controller

• IEEE surge-withstand protection

• Optical isolation for each input

• Optional digital switch selectable polarity of each bit

The Group 2 QCI provides 16 digitally-filtered contact inputs sharing a commreturn line with the ability to invert data-bit polarity (G01 does not have this optiand is no longer manufactured).

5/99 3-255 M0-0053Westinghouse Proprietary Class 2C

Page 322: Ovation Q Line

3-17. QCI

3-17.3. Specifications

A functional block diagram of the QCI is shown inFigure 3-127.

Input Requirements

Digital Filter Delay:2.6 msec to 6.0 msec

Input Signal Rejection

Input signal duration <2.6 msec is always rejected.Input signal duration >6.0 msec is always passed.

Figure 3-127. QCI Card Block Diagram

DA

TA

AD

DR

ES

S

AD

DR

ES

SC

OM

PA

RA

TO

R

PO

WE

R

DIOBGND

+12

+48+10

POWERSUPPLY

RET

PWRONLED

POINT 0

(16)

OPTICAL

ISOLATION

SIG

NA

LC

ON

DIT

ION

ING

DIG

ITA

LF

ILT

ER

ING

2:1

MU

LTIP

LEX

ER

BU

SD

RIV

ER

S

SELECT

HI-LO

ENABLE

DATA-DIR

1

LEDLOCAL

OSCILLATOR

16 8

•••••••••••••••••••POINT 15

RET

CA

RD

ED

GE

IND

ICA

TO

RS

16

UIOBGROUND JUMPER ADDRESS SELECTION

M0-0053 3-256 5/99Westinghouse Proprietary Class 2C

Page 323: Ovation Q Line

3-17. QCI

s

e

Note

The elapsed time between the contact’sopening and its subsequent closure must be>15 msec.

Contact leakage resistance:50 KΩ minimum.

Input Capabilities

The signal lines at the DIOB interface are specified by the DIOB specificationdescription.

Power Supply

Primary: +13 V +0.1 Vdc

Backup: +12.6 V+ 0.2 Vdc

Current: 500 mA (maximum) supplied by DIOB

Power Consumption: 6.3 W (maximum)

Electrical Environment

IEEE Surge withstand capability

Common Mode Voltage: 500 Vdc or peak ac (line frequency)

Card Addressing and Data Output

The QCI card address is established by eight jumpers on the front card-edgeconnector as shown inFigure3-128. The insertion of a jumper encodes a “1” on thaddress line.

Table 3-83. QCI Contact Wetting Voltage

Parameter Minimum Nominal Maximum

Open Circuit Voltage 42V 48V 56V

Closed Contact Current 6mA 14mA 22mA

5/99 3-257 M0-0053Westinghouse Proprietary Class 2C

Page 324: Ovation Q Line

3-17. QCI

data

ass

The binary data that is sent to the system controller over the DIOB are the 16bits from the 16 contact inputs divided into two eight-bit bytes.

Connections and Field Cabling

Refer toFigure 3-129 for details regarding the following discussion.

Up to 1.2 mA may flow through any contact shunt resistance from the+48V supply(with open contacts, no current can flow from the+10V supply due toreverse-biased diodes). A resistance of 50 KΩ (minimum) is required to maintainthe high-level contact-wetting voltage. However, the contacts are recognized open with a shunt resistance of 10 KΩ (minimum). To ensure that closed contactare always recognized as closed, the following equation must be applied:

RC + RLINE + 16RR ≤ 60Ω

Figure 3-128. QCI Card Address Jumper Assembly

A7 = 0

A6 = 0

A5 = 1

A4 = 0

A3 = 0

A2 = 0

A1 = 1

A0 = 1

BLANK:

BLANK:

JUMPER:

BLANK:

BLANK:

BLANK:

JUMPER:

JUMPER:

CARD-EDGE CONNECTOR(FRONT VIEW)

DIOB CARD ADDRESS = 00100011 = 2316

M0-0053 3-258 5/99Westinghouse Proprietary Class 2C

Page 325: Ovation Q Line

3-17. QCI

that

Contact Cycle Time

If the maximum QCI on card generated voltage is to be applied to plant contactsinterface to the QCI card, the elapsed time between a contact opening and itssubsequent closure must be greater than 15 msec.

Figure 3-129. Cable Length Limitations for QCI Card

FROMOTHER

CONTACTS

COMMONRETURN

PIN

ONE OF 16 INPUTS

RC RS

RRRLINE

RC + RLINE + 16RR < 60 Ω

RS = CONTACT SHUNT RESISTANCE

RC = RESISTANCE ASSOCIATED WITH A CLOSED CONTACT

RR = RESISTANCE OF A COMMON RETURN LINE (IF ANY)

RLINE = RESISTANCE OF NON-COMMON CABLE LENGTH TO AND FROM CONTACTS

5/99 3-259 M0-0053Westinghouse Proprietary Class 2C

Page 326: Ovation Q Line

3-17. QCI

he

Table 3-84 gives the cable length limits for various gauges of wire.

Table 3-84. Cable Length Limits for QCI Card

GaugeOhms/

thousand ft

16 Commons/Card(thousand ft)(maximum)1

1 Common/Card (ft)

(maximum)2

8 0.654 92 5,400

10 1.04 58 3,400

12 1.66 36 2,140

14 2.27 26 1,560

16 4.18 14 845

18 6.64 9.0 530

20 10.2 5.9 345

22 16.2 3.7 215

1The maximum cable length for a 16-common/card assumes that RR = 0 and RC = 0. Thelength given is the sum of the lengths to and from the contacts.

2The maximum cable length for a 1-common/card assumes that RC = 0. The length of thereturn is equal to the length of the cable to the contact. The length given is the length to tcontact only.

M0-0053 3-260 5/99Westinghouse Proprietary Class 2C

Page 327: Ovation Q Line

3-17. QCI

The QCI pin assignments are given inTable 3-85. These pins are located on thefront-edge connector.

Table 3-85. QCI Pin Assignments

Connection PinsB Side

(Component Side) A Side (Solder Side)

28 A7 GND

27 A6 GND

26 A5 GND

25 A4 GND

24 A3 GND

23 A2 GND

22 A1 GND

21 A0 GND

20

19

18

17 B15 B14

16

15 B13 B12

14

13 B11 B10

12

11 B9 B8

10

9 B7 B6

8

7 B5 B4

6

5 B3 B2

4

3 B1 B0

2

1 RET RET

5/99 3-261 M0-0053Westinghouse Proprietary Class 2C

Page 328: Ovation Q Line

3-17. QCI

f the

Controls and Indicators

QCI Group 2 (G02) provides the ability to reverse the polarity of the data bitsdepending on switch setting.Table 3-86 gives the data bit values for switchpositions.

Separate status-indicating LEDs for each contact input are located at the front ocard (seeFigure 3-130).

Figure 3-130. QCI Card Components

Table 3-86. QCI G02 DIP Switch Positions

Switch Position Contact State Digital Value

OPEN OpenClosed

01

CLOSED OpenClosed

10

15141312101198

76543290

PWR

DIP Switches(Only on G02)

LEDs

OSC

M0-0053 3-262 5/99Westinghouse Proprietary Class 2C

Page 329: Ovation Q Line

3-17. QCI

3-17.4. Installation Data Sheet

1 of 2

Figure 3-131. QCI Wiring Diagram

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTORCUSTOMER CONNECTIONS INTERNAL

BUS STRIP

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

+V

+48VDC

+10VDC

OPTO ISO

OPTO ISO

5/99 3-263 M0-0053Westinghouse Proprietary Class 2C

Page 330: Ovation Q Line

3-17. QCI

For CE MARK Certified System

2 of 2

Figure 3-132. QCI CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 15

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

CUSTOMER CONNECTIONS

COMPRESSION-STYLE TERMINAL BLOCK

M0-0053 3-264 5/99Westinghouse Proprietary Class 2C

Page 331: Ovation Q Line

3-18. QDC

al

ls on

3-18. QDC

Q-Line Digital Controller(Style 4256A15G01 through G11)

3-18.1. Description

G01 and G02 are applicable for use in the CE MARK Certified System

The Q-Line Digital Controller (QDC) printed circuit board provides an additionlevel of control capability, supplementing DPUs. The QDC has an on-boardprocessor which controls outputs based on user-defined algorithms. Full detaithe configuration and use of the QDC are contained in the “QDC User’s Guide”(U0-1105).

5/99 3-265 M0-0053Westinghouse Proprietary Class 2C

Page 332: Ovation Q Line

3-19. QDI

er to:

s,

t

3-19. QDI

Digital Input(Style 2840A13G01 through G11)

3-19.1. Description

The QDI card had been superseded by the QID card. For new applications, refthe following table to determine the equivalence between QID and QDI cards

The QDI card provides signal conditioning for 16 digital voltage process inputand it interfaces these signals to the DIOB (seeFigure 3-133). The QDI has twodifferent kinds of voltage-sensing input circuits available. Cards can have eightwo-wire (differential) inputs without electrical connections to other points, orsixteen single-ended inputs which share a common return line.

Table 3-87. QDI-QID Card Equivalents

QDIGroup

Equivalent QIDGroup Input Level Inputs*

G02 G02 24 VAC/DC 8

G04 G04 48 VAC/DC 8

G06 G06 120 VAC/DC 8

G10 G10 48 VDC 16

G11 G11 120 VAC 8

* 16 means single-ended inputs, 8 means differential inputs.

M0-0053 3-266 5/99Westinghouse Proprietary Class 2C

Page 333: Ovation Q Line

3-19. QDI

Block Diagram

3-19.2. Features

The QDI card is available in 11 groups and provides the following features:

• G01 provides 16 single-ended 5 VDC inputs

• G02 provides eight 24 VAC/VDC differential inputs

• G03 provides 16 single-ended 24 VAC/VDC inputs

• G04 provides eight 48 VAC/VDC differential inputs

• G05 provides 16 single-ended 48 VAC/VDC inputs

• G06 provides eight 120 VAC/VDC differential inputs

• G07 provides 16 single-ended 120 VAC/VDC inputs

Figure 3-133. QDI Block Diagram

5/99 3-267 M0-0053Westinghouse Proprietary Class 2C

Page 334: Ovation Q Line

3-19. QDI

• G08 provides 16 single-ended logic-oriented,+12 VDC inputs

• G09 provides 16 single-ended non-logic (filtered), 12 VDC inputs

• G10 provides 16 single-ended 48 VDC inputs with filter circuitry for pulseinput applications

• G11 provides eight 120 VAC/VDC differential inputs (high threshold)

3-19.3. Specifications

Input Requirements

Power Supply

Primary: +13.0 V+0.1 VDC/− 0.6 VDC

Backup: +13.0 V+ 0.1 VDC/− 0.6 VDC

Current: 200 mA (maximum for single-ended cards)100 mA (maximum for differential cards)

Table 3-88. QDI Input Requirements

Group

ONInput Voltage

(VDC or VAC rms)Min/Max

OFFInput Voltage

(VDC orVAC rms)

(max)

ONInput Current

(mA)Min/Max

PropagationTime

(msec)Min/Max

Power InFront End withAll Units On,

(Nominal Voltage)(Watts)

G01 4 6 0.9 10 15 – 0.2 1.0

G02 20 30 3 10 15 5 21 2.3

G03 20 30 3 10 15 5 21 4.6

G04 40 60 4 10 15 5 21 4.6

G05 40 60 4 10 15 5 21 9.2

G06 100 150 6 10 15 5 21 11.5

G07 100 150 6 10 15 5 21 23.0

G08 10 15 2 10 15 – 0.2 2.3

G09 10 15 2 10 15 5 21 2.3

G10 40 60 4 10 15 5 2.1 9.2

G11 100 150 VDC145 VAC

(rms)

31 VDC25 VAC

(rms)

10 15 5 43 10.1

M0-0053 3-268 5/99Westinghouse Proprietary Class 2C

Page 335: Ovation Q Line

3-19. QDI

or 16overover

Electrical Environment

IEEE Surge withstand capability

Common Mode Voltage: 500 VDC or peak AC (line frequency)

3-19.4. Card Addressing and Data Output

The QDI card address is established by eight jumpers on the front card-edgeconnector as shown inFigure 3-134 andFigure 3-135. The insertion of a jumperencodes a “1” on the address line.

The binary data that is sent to the system controller over the DIOB are the 8 data bits from the field inputs. For differential inputs, one byte of data is sent the DIOB (Figure 3-134). For single-ended inputs, two bytes of data are sent the DIOB (Figure 3-135).

This parameter defines the color for the value when the point is in alarm.

Figure 3-134. QDI Card Address Jumper Assembly (Differential Input)

A7 = 1

A6 = 1

A5 = 0

A4 = 0

A3 = 1

A2 = 0

A1 = 0

A0 = 0

JUMPER:

JUMPER:

BLANK:

BLANK:

JUMPER:

BLANK:

BLANK:

BLANK:

CARD-EDGE CONNECTOR(FRONT VIEW)

CARD ADDRESS = 1100 1000,

HI-LO = 1 (i.e. HIGH BYTEJUMPER:

(X ‘C8’ HIGH BYTE)

~ ~

5/99 3-269 M0-0053Westinghouse Proprietary Class 2C

Page 336: Ovation Q Line

3-19. QDI

Connections and Field Cabling

The digital inputs enter to the QDI Card on the front-edge connector. The pinassignments for this connector are listed inTable 3-89.

Figure 3-136 shows the wiring for point inputs to a G01.Figure 3-137 shows thetypical wiring for the single-ended input groups.

Figure 3-135. QDI Card Address Jumper Assembly, Single Ended Input

A7 = 0

A6 = 0

A5 = 1

A4 = 0

A3 = 0

A2 = 0

A1 = 1

A0 = 1

BLANK:

BLANK:

JUMPER:

BLANK:

BLANK:

BLANK:

JUMPER:

JUMPER:

CARD-EDGE CONNECTOR(FRONT VIEW)

CARD ADDRESS = 00100011(X ‘23’)

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3-19. QDI

sed

The cable length to field contacts is limited by cable capacitance when AC is uto wet contacts. SeeTable 3-90.

Figure 3-136. QDI G01 Point Wiring

Figure 3-137. QDI Typical Contact Input Point Wiring (G03, 05, 07, 08, 09, 10)

POINT 0

RETURN

POINT 15

QDI

G01

Up to 16 points

5 VOLTS

+−

FieldContact

Length

QDISingle-Ended

Point 15

Point 0

Return

16 points

FieldContact

Contact wettingvoltage supply

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3-19. QDI

Table 3-89. QDI Pin Allocations

(G01, G03, G05, G07, G08, G09, G10)

Input Digital Bit PC Card Edge Pin Field Terminal BlockTerminal Number

Return 1A and 1B 1

Bit 15 17B 17

14 15A 14

13 13B 13

12 11A 10

11 9B 9

10 7A 6

9 5B 5

8 3A 2

7 17A 16

6 15B 15

5 13A 12

4 11B 11

3 9A 8

2 7B 7

1 5A 4

0 3B 3

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3-19. QDI

(G02, G04, G06, G11)

Input Digital Bit PC Card Edge Pin Field Terminal BlockTerminal Number

Return 1A and 1B 1

Bit 0 3A 2

3B 3

1 5A 4

5B 5

2 7A 6

7B 7

3 9A 8

9B 9

4 11A 10

11B 11

5 13A 12

13B 13

6 15A 14

15B 15

7 17A 16

17B 17

Table 3-90. Cable Length for QDI

Group Maximum CapacitanceAt 50 pF/Ft

typical capacitanceMaximum Cable Length

G02 (24 VAC) 60,000 pF 1000 ft.

G04 (48 VAC) 30,000 pF 500 ft.

G06 (120 VAC) 15,000 pF 250 ft.

G11 (120 VAC) 15,000 pF 250 ft.

Table 3-89. QDI Pin Allocations (Cont’d)

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3-19. QDI

card

3-19.5. Controls and Indicators

Separate status-indicating LED’s for each input are located at the front of the(seeFigure 3-138).

Figure 3-138. QDI Card Components

LEDs

76543210

151413121110

98

LED Detail

PWR

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3-19. QDI

3-19.6. Installation Data Sheet

1 of 1

Figure 3-139. Wiring Diagram: QDI Groups 2, 4, 6, and 11

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Card

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Terminal block#8-32 Screw

Edge-connector Customer Connections

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3-20. QDT

hat

d

ignal

linetedic

3-20. QDT

Diagnostic Test(Style 7379A29G01)

3-20.1. Description

Applicable for use in the CE MARK Certified System

The Q-line Diagnostic Test (QDT) card is a DIOB testing device which verifies ta system’s DIOB functions properly (seeFigure3-140). To do this, this card verifiesthe integrity of the DIOB data, address and control lines. Additionally, this carverifies that the DIOB controller can drive the DIOB and related point cardsmounted on it. In a process control system, the Q-line point cards are used for sconditioning.

These point cards convert analog or digital field signals from a process intoequivalent digital signals that are compatible with the supervising controller. Q-point cards interface to a controller via the DIOB, which provides a byte oriendigital exchange of process information. The QDT card provides for diagnosttesting of this interface.

Figure 3-140. QDT Block Diagram

SimulationCircuit

Data DIOB Address

Card-edgeDisplays

DisplayControlCircuit

AddressDecoder &

Select

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3-20. QDT

ing

m

nel

any

3-20.2. Features

The QDT card is available in one group and provides the following features:

• Card-edge switches for mode selection and diagnostic testing.

• Simulates DC loading for 48 point cards.

• On-card 512 byte RAM to test the DIOB controller’s addressing and bus drivability.

• Card-edge LED’s for data display.

• Automatic Display mode selection on power-up to protect an active DIOB frooverloading.

Electrical connection to the QDT card is made through a 34-pin DIOB backpaconnector.

The QDT card may be housed as follows:

• In the standard Q-line card crate

• Mounted to crate with a M4X6MM screw (not provided with QDT card)

Operation

The QDT card provides two modes of operation:

• Simulator Mode – used to test DIOB and controller

Note

All point cards must be removed from theDIOB prior to Simulator mode operation.

• Display Mode – used to monitor a user selected DIOB address, displayingdata written to or read from the selected address.

Note

In the display mode, the user selects whetheroutput or input data is to be displayed, via thecard edge Data Direction switch.

3-20.3. Specifications

Power Requirements

• Voltage from DIOB:

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3-20. QDT

riveed

(50ise

els

r’s

theg of/

intonntos to

Primary: +12.4 VDC to+13.1 VDC

Secondary:+12.4 VDC to+13.1 VDC

• Current from DIOB:

750 mA maximum

• 5 VDC Power Supply:

Derived internally on QDT card from 12 VDC supplied from DIOB

Voltage: 4.8 VDC to 5.2 VDC

Current: 400 mA maximum

Simulator Mode

In the Simulator mode, the QDT card tests that the DIOB controller is able to da DIOB of maximum length and with the maximum number of point cards pluggin. Additionally, the QDT card checks that the controller is able to address allpossible DIOB locations and can generate the basic DIOB control signals.

The loading circuits, at the QDT card’s DIOB signal inputs, simulate the DCloading of the point cards and the capacitance of the longest permissible DIOBfeet). DIOB signals must drop below 3 VDC to be recognized as a logic 0 or rabove 9 VDC to be recognized as a logic 1. These QDT input circuits containvoltage comparators with hysteresis to reject input DIOB signals with voltage levbetween 3 and a 9 VDC.

In this mode, the QDT card (via the 512-bytes of RAM) tests the DIOB controlleDIOB addressing capability and the controller’s ability to drive the DIOB. TheQDT card’s 512-byte RAM simulates the entire DIOB address space. Due to fact that the QDT card simulates every DIOB point card address and the loadina DIOB full of point cards, no other point card should be present on the DIOBcontroller combination being tested.

Therefore, to prevent any mishaps, when a QDT card is powered up or insertedan active DIOB, it automatically powers up in the Display mode. The user theremoves all other point cards from the DIOB before switching the QDT card iits Simulator mode. Two edge mounted LED’s are provided to inform the user awhich mode the QDT card is in.

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3-20. QDT

eryser

yswith

OBDT

OBectedresstelyards

Caution

Failure to remove all point cards from the DIOB,prior to switching to the Simulator mode, cancause DIOB loading, generating a failedcondition.

Also, in this mode, the QDT card generates a DEVICE BUSY pulse during evDIOB cycle. This DEVICE BUSY pulses generation may be disabled by the uvia the card edge Device Busy enable switch. The DEVICE BUSY pulse isautomatically disabled and not generated in the Display mode.

Display Mode

In the Display mode, the QDT card simply monitors the DIOB lines and displadata on sixteen card edge LED’s. In this mode, the QDT logic does not interactthe DIOB address, data or control signal transfers.

Note

The QDT card displays DIOB data, while in theSimulator mode. However, no other point cards arepermitted on the DIOB.

When the QDT card operates in the Display mode, it does not occupy any DIaddresses and it appears to be transparent to the DIOB controller. All of the Qlogic, utilized for the Simulator mode, is isolated from the DIOB in the Displaymode.

Sixteen of the QDT card’s LED’s are used to display the contents of a 16-bit DIdata latch on the QDT card. This latch’s contents are updated every time the selDIOB address and direction of data (input or output) matches actual DIOB addand data direction. When this occurs, the appropriate LED’s flash for approxima0.1 seconds. In this way, the exchange of digital data between the Q-line point cand the DIOB is monitored.

3-20.4. Controls and Indicators

The QDT card’s controls and indicators are shown inFigure 3-141.Table 3-91 gives a description of these controls and indicators.

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3-20. QDT

owe

Figure 3-141. QDT Card Controls and Indicators

Table 3-91. QDT Card Controls and Indicators

Control/Indicator Description

Power-on LED Lights when QDT card is receiving power from DIOB.

Data Display LED’s These sixteen LED’s are arranged in two rows of eight each. The rclosest to the card edge displays the lower byte of DIOB data and thother row displays the higher byte of DIOB data.

Simulator LED Lights when QDT card is operating in the Simulator mode.

Display LED Lights when QDT card is operating in the Display mode.

15141312111098

76543210

DISEN

OUTIN

Power-OnLED

Data DisplayLEDs

Lamp TestSwitch

Mode SelectSwitch

Address SelectSwitch

Address SelectSwitch

Device BusyEnable Switch

Data DirectionSwitch

Simulator LED

Display LED

Address LEDADR

DISP

SIML

HighByte

LowByte

Dev.BusyDataDir.

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3-20. QDT

d

all

he

s

icto

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,to

Address LED Lights for approximately 0.1 seconds each time the DIOBaddress and data direction matches the address and datadirection selected on the QDT card.

Note

When the addresses and data directions of the DIOB and QDT carrepeatedly match, this LED appears to constantly light.

Lamp Test Pushbutton Simultaneously tests all twenty QDT card LED’s. When pressed, LED’s should light.

Mode Select ToggleSwitch (momentarycontact)

Selects the QDT card’s operating mode. Pressing this switctoward DISP displaces the QDT card into the Display modand lights the Display LED. Pressing this switch towardSIML places the QDT card into the Simulator mode and lightthe Simulator LED.

Caution

The Simulator mode should not be selected unlessall point cards areremoved from the DIOB and the appropriate DIOB controller diagnostprogramming exits. Failure to remove all point cards, prior to switchingthe Simulator mode, can cause DIOB loading, generating a failedcondition. Additionally, the QDT card’s Simulator mode is of no useunless the necessary controller diagnostic programs are present.

Address Select RotarySwitches (hex)

Selects the upper and lower bytes of the DIOB address that is to bemonitored by the QDT card’s display logic.

Device Busy ToggleSwitch

Enables or disables the generation of the DEVICE BUSY signal whithe QDT card is operating in the Simulator mode.

Data Direction ToggleSwitch

Selects the direction of DIOB data (input or output) that is to bedisplayed by the QDT card’s Display LED’s. Pressing this switch to INdisplays data that is input to the DIOB controller. Pressing this switchOUT, displays data that is written to a point card.

Table 3-91. QDT Card Controls and Indicators (Cont’d)

Control/Indicator Description

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3-21. QFR

ndthe

3-21. QFR

Remote I/O Fiber-Optic Interface(Style 4256A51G01)

3-21.1. Description

Applicable for use in the CE MARK Certified System

The QFR printed circuit board links master to remote nodes for long rangecommunication (up to 5,280 feet or 1,609 meters). The card provides signalconversion from electrical to optical and optical to electrical (one unit sends areceives). Full details on the configuration and use of the QFR are contained in“Remote Q-Line Installation Manual” (M0-0054).

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3-22. QIC

ionstionr aom

IOBrredents

of

3-22. QIC

Q-Line DIOB Monitor(Style 4256A83G01)

3-22.1. Description

The Q-Line DIOB Monitor (QIC) card adds the capability to monitor DIOBoperations. This function is often used in WDPF systems where DIOB operatdriven by one DIOB controller must be monitored by a second computer, in addito the normal DIOB controller. The second computer may be a WDPF DPU oW2500 I/O subsystem. Monitoring is typically a requirement when upgrading fra W2500 system to a WDPF system.

The card stores data transferred during read or write operations on the control Dand allows this data to be read by the second, monitor, DIOB. The data transfeover the bus is stored in shared memory on the card. Logic on the QIC card prevmemory contention from occurring.

The QIC card contains a second (monitor) DIOB port which allows read-onlyoperations of the shared memory. The monitor DIOB may originate from one three connectors on the QIC. There are two types of connectors:

• One WDPF DPU connector.

• Two connectors for a W2500 I/O subsystem.

Figure 3-142. QIC Block Diagram

ControlDIOB

Connector

Interface

MonitorDIOB

Connector1

InterfaceMonitor

DIOBConnector 2

DualPortRAM

StateMachine

StateMachine

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3-22. QIC

n into

or

entteortdwn

yte,

s theiven

ustata-

3-22.2. Features

DIOB 1 Operating Characteristics

• A DIOB 1 Read or Write operation to any location in the 512-byte DIOBaddress space causes the data present on the DIOB 1 data lines to be writtethe Dual Port RAM at the address specified by the DIOB 1 address lines.

• The QIC will not drive the DIOB 1 data lines, regardless of whether a ReadWrite operation is occurring.

• Device-Busy is checked on DIOB Read operation. If Device-Busy is not presat the proper time, no Data will be written into the shared RAM. On DIOB Wrioperation, Device-Busy is ignored. On Q-Line I/O cards which do not suppDevice-Busy, there is a jumper which to allow the Data be written to shareRam on DIOB Read operation without valid Device-Busy. The jumper is shoin Figure 3-142.

• For double-byte (word) operations, the second (High) byte of data will bewritten to the RAM before the other (Read-only) port of the RAM may beaccessed. This prevents data-tearing.

• DIOB specification, double-byte (word) operations must be accessed Low bthen High byte, in order to prevent data-tearing.

DIOB 2 Operating Characteristics

• DIOB 2 Reads of any location in the 512-byte DIOB address space causedata in the Dual Port RAM addressed by the DIOB 2 address lines to be dronto the DIOB 2 data lines.

• DIOB 2 Writes are ignored.

• Device-Busy is supported by the QIC. DIOB 2 cycles are NOT extended.

• In compliance with the DIOB specification, double-byte (word) operations mbe accessed Low byte, then High byte, in order to prevent the possibility of dtearing.

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3-22. QIC

500card

DIOB 2 Cable Restrictions

Connector P2: WDPF-style

Compatible with MBU, MSQ, MSX

Maximum Length: 50 ft

Connectors P3 or P4: W2500 -style

Compatible with WIO

Maximum Length: no longer than the present WIO-QPD or WIO-QPP cables

System Grounding Restriction

The 2 DIOB ports on the QIC are not isolated from each other. The DPU or W2computer power grounds (PG) of the cabinets that are connected to the QIC must be connected together by a minimum 4 AWG wire.

It is recommended that the cabinet containing the monitor DIOB controller beadjacent to the cabinet containing the QIC card.

Note

This current does not include the current drawn by anMBU, MSQ, or MSX card if it is connected to DIOB2. There is no current drawn by the WIO, if one isconnected to DIOB 2.

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3-22. QIC

r

be

d,

trolte,

at

B 2he

ns

Operating Restrictions

The following restrictions apply when using the QIC card:

• The power grounds (PG) of the cabinets containing the control and monitoDIOB controllers must be connected together by a minimum 4 AWG wire.

• It is recommended that the cabinet containing the monitor DIOB controlleradjacent to the cabinet containing the QIC card.

• The monitor DIOB cannot contain any other I/O cards that need to be reabecause the QIC responds to Read operations of all DIOB addresses.

• Double-byte (word) Read and Write operations of both the monitor and conDIOBs must be in Low byte, then High byte order to prevent data tearing. Nothe DPU DIOB controllers and the WIO both meet this requirement.

• Although three connectors exist (one for a DPU, two for a W2500) for themonitor DIOB, only one connector may be connected to a DIOB controllerany one time.

Card Usage

The QIC card contains four DIOB connectors P1, P2, P3, and P4 (seeFigure3-144). However, the signals coming from connectors P2, P3, P4 of DIOare tied together so that, essentially, there are two DIOB ports on the card. Tsignals from these ports are buffered and level-shifted to +5V levels.

The two state machines (Figure3-142) resolve any Shared RAM access contentiowhen two DIOB ports attempt to access the Shared Ram at the same time.

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3-22. QIC

B

f thethereon

O/,

hest

d to Then.

s are

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AM

The following occurs when a Read or Write operation occurs on DIOB 1:

1. The rising edge of DATA-GATE signals the Write State Machine that a DIOoperation is occurring.

2. The Write State Machine examines the output of the address comparator. Iaddress is the same as the previous (latched) address, HI,LO/ is high, andis data in the low byte latch that still must be written to RAM, a word operatiis occurring. Otherwise, a byte operation is occurring.

3. For a byte operation, the following occurs, depending on the state of HI,Land whether there is data in the low byte latch that still must be written. IfHI,LO/ is High, the Write State Machine immediately writes the data into tHigh Byte Dual Port RAM. If there is data in the low byte latch that still mube transferred to RAM, it will also be written at this time. If HI,LO/ is low andthere is data in the low byte latch, the data in the low byte latch is transferreRAM. Immediately afterward, the incoming data and address are latched.data is not written to RAM in case this new low byte is part of a word operatioIf there is no data in the latch to be written, the incoming data and addreslatched immediately. For a word operation, the Write State Machineimmediately writes both the low and high bytes to their respective

Dual Port RAMs

If there is data in the low byte latch that must be transferred to RAM and the 10µstimer has expired, the data is written to the RAM. The 10µs timer is used todetermine whether a low byte operation is part of a word operation. The timeturned on at the falling (inactive) edge of DATA-GATE. For a word operation, maximum time between pulses is 10µs. If the timer expires without anotheroccurrence of DATA-GATE, the low byte operation must have been a byteoperation. This ensures that a single low byte operation will be transferred to Ras soon as possible, in case another DIOB operation does not occur.

Note

If more than 10µs occurs between DATA-GATE pulses,the Write State Machine will write the low byte of datato the Dual Port RAM. Data tearing can occur for anassumed word operation if the DATA-GATE pulse of thehigh byte write follows the DATA-GATE pulse of thelow byte write by more than 10µs.

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3-22. QIC

OB

tion

sta

ressnd the.

ort

andauseword

t of a

The following occurs when a Read operation occurs on DIOB 2:

1. The rising edge of DATA-GATE signals the Read State Machine that a DIoperation is occurring.

2. If the operation is a write, no action takes place. Otherwise, the following acoccurs.

3. If HI,LO/ is low, the Read State Machine latches the address. It then readBOTH Dual port RAMs and latches the high byte of data. The low byte of dais transferred immediately to the DIOB drivers.

4. If HI,LO/ is high, the Read State Machine examines the output of the addcomparator. If the address is the same as the previous (latched) address a10 µs timer has not expired, the high byte read is part of a word operationOtherwise, the high byte read is a byte operation.

5. For a byte operation, the Read State Machine reads the High Byte Dual pRAM and transfers the data to the DIOB drivers.

For a word operation, the Read State Machine reads the High Byte Latchtransfers the data to the DIOB drivers. Note, the latch is read in this case becit contains the data that was read at the same time as the low byte of the was read. This prevents data tearing.

6. Similar to the 10µs timer used with the Write State Machine, the 10µs timer inthe Read State Machine determines whether a High Byte Read may be parword operation or not.

Note

For a high byte read operation, if the DATA-GATE pulseoccurs more than 10µs after the previous DATA-GATEpulse, a single high byte Read operation is assumed andthe data will be transferred from the RAM, regardless ofwhether the address matched the previous address.Therefore, to prevent data tearing from an assumed wordRead operation, the DATA-GATE pulse of the high bytewrite should follow the DATA-GATE pulse of the lowbyte write by less than 10µs.

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3-22. QIC

3-22.3. Specifications

Figure 3-143. QIC Detailed Block Diagram

Leve

lS

hift

12V

→5V

P1

HB

Dat

aLa

tch

LB Dat

aLa

tch

Add

.La

tch

Add

.C

omp.

Leve

lS

hift

5V→

12V

HB

Dat

aLa

tch

LB Dat

aLa

tch

Add

.La

tch

Add

.C

omp.

Leve

lS

hift

5V ←

12V

Leve

lS

hift

5V ←

12V

P2

P3

Sha

red

RA

MDD

A

DIO

B2

A

(Mon

itor)

Por

t

DIO

BC

ontr

ols

DIO

BC

ontr

ols

Add

.M

atch

Add

.M

atch

DIO

B1

(Con

trol

)P

ort

P4

Arb

itrat

ion

Sta

teM

achi

ne

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3-22. QIC

bus

Power Supply Voltage

Power Requirements

DIOB 1 supply voltage: +12.4 VDC to 13.1 VDC

Current: - supplied by DIOB 1

Typical 250 mA

Maximum 550 mA

3-22.4. Controls and Indicators

There are three jumpers on the card. Their approximate location is shown inFigure 3-144).

JS1 Control-DIOB Watch-dog Timer.

The settings are 1 or 20 Seconds. If activity ceases on the control DIOBlonger than the setting time, bits 0 and 8 of the status word are reset.

Minimum Nominal Maximum

Primary Voltage 12.4V 13.0V 13.1V

Backup Voltage 12.4V 13.1V

Figure 3-144. QIC Card Outline

JS1

JS3

JS2

Status LEDs

Power Connection

ActivityFlag SelectSwitch (SW1)

P1

P2

P3P4

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3-22. QIC

wordheIOB

the

ol

n

.

e a

in

The address of the status word is set by DIP switch SW1. The Status can be read in word or single byte operation from the Monitor DIOB 2. Taddress of the status word must be an unused Monitor (and control) Daddress.

JS2 Clock Enable. The JS2 jumper must be installed for normal operation ofQIC. This jumper is used for card production testing only.

JS3 Device-busy disabled. If installed, the QIC will write data from the ContrDIOB Read operation to shared RAM with or without valid Device-Busy.

If not installed, data from Control DIOB Read operation will not be writteto shared RAM without a valid Device-Busy.

Status LEDs

There are three status LEDs. Their location is shown inFigure 3-144. Theirmeanings are as follows:

LED1 OUTPUT PWR. If lit, there is +12VDC at TB1 connector of DIOB 2 portThis +12VDC is provided by DIOB 1 port.

LED2 QIC PWR. If lit, there is +12VDC and +5VDC power on QIC board. Th+12VDC is received from DIOB 1 port. The +5VDC is generated bylinear regulator on board.

LED3 ALIVE. If lit, bit 0 and bit 8 of the status word is set. It indicates the DIOBcontroller connected to DIOB 1 port access the DIOB 1 at least once1 second or 20 second depending on the setting of JS1.

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3-22. QIC

r oneis

3-22.5. Signal Interface

DIOB P1 Connector

The QIC interfaces to the control DIOB through a 34 pin card-edge connectothe DIOB backplane (P1 onFigure 3-144). The pinout and signal assignment arshown inTable 3-92 below. The QIC does not use the following signals from thconnector: UCAL/, UCLOCK, UFLAG/, USYNC, UNIT, DEV-BUSY.

Table 3-92. QIC DIOB1 Card Edge Connector

Signal Name(Component Side) Pin Number Pin Number

Signal Name(Solder Side)

PRIMARY +V 2 1 PRIMARY +V

BACKUP +V 4 3 BACKUP +V

GROUND 6 5 GROUND

UADD1 8 7 UADD0

UADD3 10 9 UADD2

Comp. UADD5 12 11 UADD4 Solder

Side UADD7 14 13 UADD6 Side

R,W/ 16 15 HI,LO/

DATA-GATE 18 17 UNIT

DEV-BUSY 20 19 GROUND

UDAT1 22 21 UDAT0

UDAT3 24 23 UDAT2

UDAT5 26 25 UDAT4

UDAT7 28 27 UDAT6

UFLAG/ 30 29 GROUND

USYNC 32 31 UCAL/

GROUND 34 33 UCLOCK

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3-22. QIC

t

DIOB 2 P2 Connector (WDPF style)

The QIC interfaces to the WDPF monitor DIOB through a 50 pin card-edgeconnector (see P2 onFigure 3-144). This cable connects to the WDPF DPU thadrives the DIOB signals. The pinout and signal assignment are shown inTable 3-93. The QIC does not use the following signals from this connector:UCAL/, UCLOCK, UFLAG/, USYNC, UNIT.

Table 3-93. QIC DIOB2 for WDPF

Signal Name(Component Side) Pin Number Pin Number

Signal Name(Solder Side)

GROUND 1 2 UADD0

GROUND 3 4 UADD1

GROUND 5 6 UADD2

GROUND 7 8 UADD3

GROUND 9 10 UADD4

GROUND 11 12 UADD5

GROUND 13 14 UADD6

GROUND 15 16 UADD7

GROUND 17 18 HI,LO/

GROUND 19 20 R,W/

GROUND 21 22 UNIT

GROUND 23 24 DATA-GATE

GROUND 25 26 DEV-BUSY

GROUND 27 28 UDAT0

GROUND 29 30 UDAT1

GROUND 31 32 UDAT2

GROUND 33 34 UDAT3

GROUND 35 36 UDAT4

GROUND 37 38 UDAT5

GROUND 39 40 UDAT6

GROUND 41 42 UDAT7

GROUND 43 44 UFLAG/

GROUND 45 46 UCAL/

GROUND 47 48 USYNC

GROUND 49 50 UCLOCK

5/99 3-293 M0-0053Westinghouse Proprietary Class 2C

Page 360: Ovation Q Line

3-22. QIC

le).OB

P

DIOB 2 P3 Connector

The QIC interfaces to the W2500 monitor DIOB through a 34 pin card-edgeconnector P3 (WIO QPD style) or a 34-pin header connector P4 (WIO QPP styA cable connects to the W2500 I/O subsystem’s WIO board, which drives the DIsignals. The pinout and signal assignment for both connectors are shown inTable 3-94.

Table 3-94. QIC DIOB2 (P4) for WIO

Signal Name(Component Side) Pin Number Pin Number

Signal Name(Solder Side)

NC 1 2 NC

NC 3 4 NC

GROUND 5 6 GROUND

UADD0 7 8 UADD1

UADD2 9 10 UADD3

UADD4 11 12 UADD5

UADD6 13 14 UADD7

HI,LO/ 15 16 R,W/

UNIT 17 18 DATA-GATE

GROUND 19 20 DEV-BUSY

UDAT0 21 22 UDAT1

UDAT2 23 24 UDAT3

UDAT4 25 26 UDAT5

UDAT6 27 28 UDAT7

GROUND 29 30 UFLAG/

UCAL/ 31 32 USYNC

UCLOCK 33 34 GROUND

Note: The QIC does not use the following signals from this connector: PRIMARY +V, BACKU+V, UCAL/, UCLOCK, UFLAG/, USYNC, UNIT

M0-0053 3-294 5/99Westinghouse Proprietary Class 2C

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3-22. QIC

at isX

teual

itche

DIOB 2 Power Connector

The QIC card contains the same 2 position terminal block +12V connector thon the QBE. This is used to power the DIOB interface circuitry on the MSQ or MScard.

DIOB 1 Addressing

The QIC responds to any DIOB 1 Read or Write to any location in the 512-byDIOB address space by writing the data present on the DIOB data lines into its DPort RAM at the address specified by the DIOB address lines.

DIOB 2 Addressing

The QIC responds to any DIOB 2 Read of any location in the 512-byte DIOBaddress space by driving the DIOB 2 data lines with the Dual Port RAM dataaddressed by the DIOB address lines.

There is board status word. The location of this word is selected with the DIP swSW1 (seeFigure3-144). Any Read by Monitor DIOB of this address will read thstatus word, not the shared RAM.

The QIC ignores DIOB 2 Writes.

5/99 3-295 M0-0053Westinghouse Proprietary Class 2C

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3-23. QID

C

ds for

3-23. QID

Style 4256A84G01 - G16 (through-hole PC boards)Style 3A99159G01 - G17 (surface mount PC boards)

3-23.1. Description

Groups 4256A84G01-G05;G08-G10 are applicable for use in the CE MARK CertifiedSystem

The Q-Line Digital Input Card (QID) provides an interface to 220 VAC and 220 VDdigital inputs. The QID can be used for up to 8 differential (Figure 3-145) or 16single-ended (Figure 3-146) inputs. For some applications, the QID allows fieldwiring cable length of up to 2,000 ft. (seeTable3-101 for a list of allowable lengths).Because of the increased cable length, new systems should employ the QID carall digital input applications where QDI or QBI cards were formerly used.Table 3-96 provides a list of equivalent cards for QDI and QBI.

Figure 3-145. QID Block Diagram, Double Input

Address

DIOBData

R/W HI-LO

AddressComparator

BusDriver

Opto-CouplersR-C Filters

SignalConditioning

LEDIndicators

JumperAddressSelection

Point 0 Point 7

1

88

8

(8) (A7) - (A8) - (A0) HI-LO

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Page 363: Ovation Q Line

3-23. QID

3-23.2. Features

• 8 differential (two-wire) inputs or 16 single-ended inputs.

• 500 VDC common mode rating.

• 600 VDC on-card isolation between each differential input channel. *

• Inputs include: 5, 12, 24, 48, 120, or 220 Volts

• IEEE Surge Withstand Capability (except Groups 01, 08, and 17).

• Field inputs and DIOB bus isolation using optical couplers.

• 500KΩminimum leakage resistance of field wiring cable allowed.

• May be read by any DIOB compatible controller card.

• Status LED for each input.

Figure 3-146. QID Block Diagram, Single Input

* The type of field wiring and style of terminations may restrict the design limit of the card.

DIOB

AddressComparator

JumperAddressSelection

LEDIndicators

Data R/W

BusDriver

2:1

Opto-CouplersR-C Filters

SignalConditioning

Point 0 Point 15

(16)

Common (A7) - (8) - (A0)

1

1

8

1616

16

AddressHi-Lo

Multiplex

5/99 3-297 M0-0053Westinghouse Proprietary Class 2C

Page 364: Ovation Q Line

3-23. QID

N

e

• QID Field input voltages equal to or less than the maximum OFF INPUTVOLTAGE, or currents equal to or less than the maximum OFF INPUTCURRENT, guarantee a logic zero to be read via the card.

• QID Field input voltages within the range of the ON INPUT VOLTAGE willguarantee a logic one to be read via the card.

• ON INPUT CURRENT gives the range of input current for the specified OINPUT VOLTAGE range.

• Minimum ON INPUT CURRENT does not guarantee that a logic one will btransfer via the card.

• 500 VDC or peak AC (line frequency) common mode voltage.

M0-0053 3-298 5/99Westinghouse Proprietary Class 2C

Page 365: Ovation Q Line

3-23. QID

Table 3-95. QID Card Summary

Group Input Level Inputs* Surge** Comments Replaces

G01 5 VDC 16 No No input filters -Common line

connected to 5VDC

QBI G01

G02 24 VAC/DC 8 Yes QDI G02

G03 24 VAC/DC 16 Yes QBI G04,10

G04 48 VAC/DC 8 Yes QDI G04

G05 48 VAC/DC 16 Yes QBI G05,06

G06 120 VAC/DC 8 Yes 500 ft cable QDI G06

G07 120 VAC/DC 16 Yes 500 ft cable QBI G07,08, 11

G08 12 VDC 16 No No input filters QBI G02

G09 12 VAC/DC 16 Yes QBI G03,09

G10 48 VDC 16 Yes Pulse Inputs QDI G10

G11 120 VAC 8 Yes 1,000 ft cable QDI G11

G12 120 VAC 16 Yes 1,000 ft cable QBI G08,11

G13 220 VAC 8 Yes 1,000 ft cable

G14 220 VAC 16 Yes 1,000 ft cable

G15 220 VDC 8 Yes

G16 220 VDC 16 Yes

G17*** 5VDC 16 No No input filters -Common line can beconnected to +5V or

5V RTN.

QBI G01

* 16 means single-ended inputs, 8 means differential inputs. ** ANSI Std. C37.90A 1974 (or IEEE 472-1974) for surge withstand*** Style 3A99159 only.

5/99 3-299 M0-0053Westinghouse Proprietary Class 2C

Page 366: Ovation Q Line

3-23. QID

d in

3-23.3. Specifications

Inputs/Outputs

Power Requirements

Control DIOB supply voltage: +12.4 VDC to 13.1 VDC

Current: - supplied by DIOB bus.

Typical: 100 mA

Table 3-96. QID Inputs

Group

ONInput Voltage(VDC or VAC

RMS)

OFFInput

Voltage(VDC or

VAC RMS)

ONInput Current

(mA)

OFFInput

CurrentPropagationTime (msec)

Power InFront End,

All Units On(Watts)Typical

MIN MAX MAX MIN MAX (mA) MIN MAX (TYP)

G01 2.4 7 0.9 2 10 0.5 --- 0.2 0.5

G02 20 30 7 5 10 3.0 1 14 1.5

G03 20 30 7 5 10 3.0 1 14 3.0

G04 40 60 17 7 12 5.0 1 14 3.8

G05 40 60 17 7 12 5.0 1 14 7.6

G06 100 150 40 6 10 3.8 1 14 7.1

G07 100 150 40 6 10 3.8 1 14 14.2

G08 10 15 3 5 10 2.0 --- 0.2 1.5

G09 10 15 3 5 10 2.0 1 14 1.5

G10 40 60 24 7 12 5.0 0.5 2.1 7.6

G11 95 150 60 16 27 8.4 1 14 10.0

G12 95 150 60 16 27 8.4 1 14 20.0

G13 190 264 120 30 43 11.4 1 14 23.2

G14 190 264 120 30 43 11.4 1 14 46.4*

G15 180 264 110 6 10 3.8 1 14 12.4

G16 180 264 110 6 10 3.8 1 14 24.8

G17 2.8 7 0.9 2 10 0.5 --- 0.2 0.5

* Note: Due to high power in front end, the maximum number of the QID G14 that can be usethe DPU cabinet is 24 cards.

M0-0053 3-300 5/99Westinghouse Proprietary Class 2C

Page 367: Ovation Q Line

3-23. QID

theldershown

Maximum: 200 mA

DIOB Connector

The QIC interfaces to the DIOB bus through a 34 pin card-edge connector onDIOB backplane. The QID contains 17 gold fingers on the component and sosides of the board, spaced 0.1” apart. The pinout and signal assignment are in Table 3-97.

Table 3-97. QID Pinout

Signal Name Pin # Pin # Signal Name

PRIMARY +V 2 1 PRIMARY +V

BACKUP +V 4 3 BACKUP +V

GROUND 6 5 GROUND

UADD1 8 7 UADD0

UADD3 10 9 UADD2

Comp. UADD5 12 11 UADD4 Solder

Side UADD7 14 13 UADD6 Side

R,W/ 16 15 HI,LO/

DATA-GATE 18 17

DEV-BUSY 20 19 GROUND

UDAT1 22 21 UDAT0

UDAT3 24 23 UDAT2

UDAT5 26 25 UDAT4

UDAT7 28 27 UDAT6

30 29 GROUND

32 31

GROUND 34 33

5/99 3-301 M0-0053Westinghouse Proprietary Class 2C

Page 368: Ovation Q Line

3-23. QID

DI

d in

ds.

There are three type of input signal interfaces selectable by groups:

• Differential Input Interface-- provided in QID 8 differential input groups(QID G02, 04, 06, 11, 13, and 15) and is the same as that provided in any Q8 differential input cards. SeeTable 3-98.

• Single Ended Input Interface --provided in QID 16 differential input groups(QID G01, 03, 05, 07-09, 12, 14, 16, and 17) and is the same as that provideany QBI 16 Single-ended input cards. SeeTable 3-99.

• Group 10 Input Interface -- equivalent to the QDI 16 single-ended input carSeeTable 3-100.

Table 3-98. QID Differential Input Interface

Input DigitalBit Number PC Card Edge Pin 1A and 1B

Field BlockTerminal Number

Chassis 1A and 1B 1

Bit 0 3A 2

3B 3

Bit 1 5A 4

5B 5

Bit 2 7A 6

7B 7

Bit 3 9A 8

9B 9

Bit 4 11A 10

11B 11

Bit 5 13A 12

13B 13

Bit 6 15A 14

15B 15

Bit 7 17A 16

17B 17

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Page 369: Ovation Q Line

3-23. QID

Table 3-99. QID Single-Ended Input Interface

Input DigitalBit Number PC Card Edge Pin

Field BlockTerminal Number

Common 1A and 1B 1

Bit 0 3A 2

Bit 1 3B 3

Bit 2 5A 4

Bit 3 5B 5

Bit 4 7A 6

Bit 5 7B 7

Bit 6 9A 8

Bit 7 9B 9

Bit 8 11A 10

Bit 9 11B 11

Bit 10 13A 12

Bit 11 13B 13

Bit 12 15A 14

Bit 13 15B 15

Bit 14 17A 16

Bit 15 17B 17

5/99 3-303 M0-0053Westinghouse Proprietary Class 2C

Page 370: Ovation Q Line

3-23. QID

eld.ctor.per

ssdge

DIOB Control

The QID Single-ended Input groups occupy a 16 bit word in the DIOB address fiThe address of the QID is selected by jumpers at the top of the front-edge conneInsertion of a jumper encodes a “one” on each address line. Absence of a jumencodes a “zero”.

The QID Differential Input groups occupy one byte (8 bits) in the DIOB addrefield. When selecting address of the QID, the HI-LOW address line at the front-econnector must also be used.

Table 3-100. QID G10 Input Interface

Input DigitalBit Number PC Card Edge Pin

Field BlockTerminal Number

Common 1A and 1B 1

Bit 8 3A 2

Bit 0 3B 3

Bit 1 5A 4

Bit 9 5B 5

Bit 10 7A 6

Bit 2 7B 7

Bit 3 9A 8

Bit 11 9B 9

Bit 12 11A 10

Bit 4 11B 11

Bit 5 13A 12

Bit 13 13B 13

Bit 14 15A 14

Bit 6 15B 15

Bit 7 17A 16

Bit 15 17B 17

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Page 371: Ovation Q Line

3-23. QID

etsrateer bit

pututsts of

Input Circuit

Each input circuit of the QID is inherently a voltage input device. A two-wiredifferential input will produce a logic “one” at the DIOB if the voltage between thtwo wires is greater than the minimum ON INPUT VOLTAGE specified for thaQID group. A Logic “zero” will be produced if the voltage between two wires iless than the maximum OFF INPUT VOLTAGE. Single-ended input cards opein a similar manner except that voltage is sensed between the one input wire pand the common terminal.

Contact inputs are provided by placing a field contact in series with the QID involtage supply. Contact closure produces a logic “one” at the DIOB. Contact inpmay also be used on differential cards where isolation between two or more sewetting voltage supplies is required.

Figure 3-147. QID Card Address Jumper Example

Jumper

Jumper

Blank

Blank

Jumper

Blank

Blank

Blank

Jumper

: A7 = 1

: A6 = 1

: A5 = 0

: A4 = 0

: A3 = 1

: A2 = 0

: A1 = 0

: A0 = 0

: HI-LO = 0

Card Address =11001000

(Hex “C8” Low Byte)

Blank

Blank

Jumper

Blank

Blank

Blank

Jumper

Jumper

: A7 = 0

: A6 = 0

: A5 = 1

: A4 = 0

: A3 = 0

: A2 = 0

: A1 = 1

: A0 = 1

Card Address =00100011(Hex “23”)

Differential Inputs Single-Ended Inputs

No Jumper requiredat HI-LO

5/99 3-305 M0-0053Westinghouse Proprietary Class 2C

Page 372: Ovation Q Line

3-23. QID

e”,

3-23.4. Controls and Indicators

Power LED

POWER LED indicates whether there is +12VDC on the QID board.

Input status LEDs

For each input to the QID card, an LED indicates input status (ON for logic “onOFF for logic “zero”).

Figure 3-148. QID Card Outline

LEDs

76543210

151413121110

98

LED Detail

PWR

M0-0053 3-306 5/99Westinghouse Proprietary Class 2C

Page 373: Ovation Q Line

3-23. QID

leh can

3-23.5. Wiring

Field Wiring Cable Length

When using AC supply voltage to wet contact inputs, some limits exist on cablengths due to stray capacitance in the cables. The maximum capacitance whicbe tolerated by the QID is listed below.

Note

For CE Mark certified systems, fieldwiring that carries the AC mains musthave double insulation.

Table 3-101. QID Allowable Cable Capacitance

Group Number Voltage Capacitance Maximum Length1

G02 (24VAC) 100,000 PF 2,000 FT

G03 (24VAC) 100,000 PF 2,000 FT

G04 (48VAC) 75,000 PF 1,500 FT

G05 (48VAC) 75,000 PF 1,500 FT

G06 (120VAC) 25,000 PF 500 FT

G07 (120VAC) 25,000 PF 500 FT

G11 (120VAC) 50,000 PF 1,000 FT

G12 (120VAC) 50,000 PF 1,000 FT

G13 (220VAC) 50,000 PF 1,000 FT

G14 (220VAC) 50,000 PF 1,000 FT1 Based on standard cable with stray capacitance of 50 PF/FT. A longer length cable can be used if a cable with lower capacitance is used.

5/99 3-307 M0-0053Westinghouse Proprietary Class 2C

Page 374: Ovation Q Line

3-23. QID

'

'

Figure 3-149. QID Group 1 Connections

Figure 3-150. QID Group 8 and Group 17 Connections

LogicVoltage

G01

Point 15

Point 0

Common

(16)

QID

+

-

LogicVoltage

G08 and G17

Point 15

Point 0

Common

(16)

-

+

QID

Common linecan be connectedto Logic Voltage (+)or Logic Voltage (-).

M0-0053 3-308 5/99Westinghouse Proprietary Class 2C

Page 375: Ovation Q Line

3-23. QID

Figure 3-151. QID Single Ended Inputs

Figure 3-152. QID Differential Inputs

FieldContact

Length

QIDSingle-Ended

Point 15

Point 0

Return

16 points

FieldContact

Contact wettingvoltage supply

(see Table 3-101)

Inputs

FieldContact

Length

QIDDifferential

Point 7

Point 0

Return

8 points

FieldContact

Contact wettingvoltage supply

(see Table 3-101)

Contact wettingvoltage supply

Chassis

(8)

Input

5/99 3-309 M0-0053Westinghouse Proprietary Class 2C

Page 376: Ovation Q Line

3-23. QID

3-23.6. Installation Data Sheet

1 of 7

Figure 3-153. QID Wiring for Groups 2, 4, 6, 11, 13, and 15

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

20

19

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19B

19A

17B

17A

15B

15A

13A

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Card

EdgeConnector

CustomerConnections

TerminalBlock

Note: For G13 (220 VAC) and G15 (220 VDC) used with #6 screw terminalblocks, all neutral returns of wetting voltages must be connected to eventerminals of terminal blocks (terminals 2, 4, 6, 8, 10, 12, 14, 16).

M0-0053 3-310 5/99Westinghouse Proprietary Class 2C

Page 377: Ovation Q Line

3-23. QID

Installation Data Sheet

2 of 7

Figure 3-154. QID Card Connections

5/99 3-311 M0-0053Westinghouse Proprietary Class 2C

Page 378: Ovation Q Line

3-23. QID

Installation Data Sheet

3 of 7

Figure 3-155. QID Card Connections

M0-0053 3-312 5/99Westinghouse Proprietary Class 2C

Page 379: Ovation Q Line

3-23. QID

Installation Data Sheet

4 of 7

Figure 3-156. QID Card Connections (G10)

5/99 3-313 M0-0053Westinghouse Proprietary Class 2C

Page 380: Ovation Q Line

3-23. QID

For CE MARK Certified System

5 of 7

Figure 3-157. QID CE MARK Wiring Diagram (Groups 2, 4, 6, 11, 13 and 15)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

A

BIT 2+

-

BIT 0+

-

BIT 1+

-

BIT 3+

-

BIT 4+

-

BIT 5+

-

BIT 6+

-

BIT 7+

-

20

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

PE

M0-0053 3-314 5/99Westinghouse Proprietary Class 2C

Page 381: Ovation Q Line

3-23. QID

For CE MARK Certified System

6 of 7

Figure 3-158. CE MARK Wiring Diagram (Groups 1, 3, 5, 7, 8, 9, 12, 14 and 16)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

20

PE

20

PE

19

20

19

20

CUSTOMER CONNECTIONS

18 1A *

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 15

* 2A in Groups 14 and 16

-

+AC or DC~

5/99 3-315 M0-0053Westinghouse Proprietary Class 2C

Page 382: Ovation Q Line

3-23. QID

For CE MARK Certified System

7 of 7

Figure 3-159. CE MARK Wiring Diagram (Group 10)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

20

PE

19

20

CUSTOMER CONNECTIONS

.75A

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 15

BIT 7

BIT 6

BIT 14

BIT 13

BIT 5

BIT 4

BIT 12

BIT 11

BIT 3

BIT 2

BIT 10

BIT 9

BIT 1

BIT 0

BIT 8

BIT 15

-

+AC or DC~

M0-0053 3-316 5/99Westinghouse Proprietary Class 2C

Page 383: Ovation Q Line

3-24. QLC

the

he

3-24. QLC

Q-Line Serial Link Controller(Style 4256A01G01)

3-24.1. Description

Groups 01and 02 are applicable for use in the CE MARK Certified System

The QLC printed circuit board is a single-board computer which interfaces to WDPF DPU (Distributed Processing Unit). The QLC, installed in a Q-Cratecommunicates with the DPU through the DIOB. For additional information on tQLC, see “QLC User’s Guide” (U0-1100).

5/99 3-317 M0-0053Westinghouse Proprietary Class 2C

Page 384: Ovation Q Line

3-25. QLI

ndutedoneand

3-25. QLI

Q-Line Loop Interface Card(Style 7381A10G01 through G03)

3-25.1. Description

Groups 01, 02, 03 are applicable for use in the CE MARK Certified System

The Q-Line Loop Interface Card (QLI) handles the analog and digital inputs aoutputs associated with a single or cascaded control loop executing in a DistribProcess Unit (DPU). The QLI’s I/O capability consists of three analog inputs, analog output, two digital inputs, and two digital outputs. Communications to from the card are through a Distributed Input/Output Bus (DIOB).

Figure 3-160. QLI Functional Block Diagram

DIOB

DIOB Interface

DIOB Bus Arbitration,

Serial

A/D A/D A/D D/A

RS 422Serial Port

ProcessorEPROM

RAM

Two OpticalIsolators

TwoDrivers

TWO OPTICALISOLATORS

Two SignalConditioners

Two OpticalIsolators

(+) (−) (+) (−) (+) (−) (+) (−) RTNTwo Digital InputsTwo Digital Outputs

AnalogOutput

Analog Inputs

MEMORY

E EPROM

Switches

PortCircuit

Isolation Barrier

G03

40V

- +

G01,02or

TimingControl

Switches,Jumpers Data Latches

M0-0053 3-318 5/99Westinghouse Proprietary Class 2C

Page 385: Ovation Q Line

3-25. QLI

ep

at athe

ts at

me

d

The QLI may be linked to a Loop Interface Module (LIM) or Small Loop InterfacModule (SLIM), used for monitoring and manual control of the QLI’s control loo(seeFigure 3-161).

Analog input voltages or currents are converted by the QLI to binary numbersrate of four times per second. They are stored by the QLI until they are read byDPU. Binary numbers from the DPU are converted to output voltages or currena rate greater than 10 times/second.

Digital inputs are read five times per second and digital outputs fixed at the sarate.

Three versions of the QLI are available, distinguished by their analog input anoutput value ranges:

Figure 3-161. QLI Card Usage

Version Analog Input Analog Output

Group 1 0 - 10 V 0 - 10 V

Group 2 0 - 5 V 0 - 10 V

Group 3 0 - 20 mA 4 - 20 mA

LIMor

SLIM

Flat Flex(Up to 12QLI’s onchain)

Twisted Pair

TransitionPanelMultiple QLIs(LIM or SLIM)

LIMor

SLIM

Twisted Pair(One QLI/LIMor SLIM)

DPU

Q-Crate

DataHighway

TCP

DPU

QBE

QTB

QLI

#1

QLI

#2

QLI

#3

QLI

#4

QLI

#28

QLI

#29

QLI

#30

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Group 3 QLIs may be modified to accept 10-50 mA input by changing a 250 oinput resistor on the card to a 100 ohm resistor. Changing the resistor to 100 ointroduces an error of 0.2%.

Each QLI card must have an external power supply which delivers 500 mA at24 VDC to the card edge connector. This power is for I/O functions. The Q crdelivers 13 VDC at the rear edge pin connectors. This is the power for all logiccommunications on the card.

The QLI automatically checks for 13-volt power supply malfunctions as well amany of its own malfunctions. Malfunctions are displayed by the program runnin the DPU.

Additional information related to the installation and operation of the QLI can befound in “Q-Line Loop Interface Module (QLI/LIM) User’s Guide” (NLAM-B200).

3-25.2. Features

• Three analog input circuits and one analog output circuit. Also two digital inpand two digital output circuits. Both analog and digital circuitry are isolatedfrom the logic circuitry.

• Choice of analog input and output ranges.

• Analog-to-digital conversion rate of four times per second with an accuracy0.1%

• Digital scan rate of five times per second.

• Automatic adjustment for gain and offset temperature coefficients of analoinputs.

• IEEE/SWC surge withstand protection for both digital and analog inputs aoutputs.

• Interfaces with the DPU through a Distributed Input/Output Bus (DIOB).

• Configuration switches to customize operation.

• Serial port connection to Loop Interface Module (LIM) or Small Loop InterfacModule (SLIM). RS-422 and up to 1000 feet long.

• Automatic diagnostic program detects 13V power supply and QLImalfunctions.

• Detects and flags over- and under-range conditions.

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3-25.3. Specifications

Analog Input:

Input ranges Group 1 0-10 VDC

Group 2 0-5 VDC

Group 3 0-20 mA*

A/D conversion type voltage-to-frequency

Conversion rate 4/sec

Accuracy 0.1%

Impedance 100 megohms/volt, 1000 ohms in overload

Resolution 12 bits

Analog Output:

Output ranges Group 1 0-10 VDC

Group 2 0-10 VDC

Group 3 4-20 mA*

Loading 0-1000 Ohms for current, 500 Ohms minimum for volta

Resolution 12 bits, unipolar

Digital Input Ranges

Min ON voltage – 18VDC

Max ON voltage – 60VDC

Max OFF voltage – 6VDC

Max OFF current – 0.5mA

Digital Output Ranges

Min ON voltage 2VDC at 150mA, 3VDC at 200mA

Max ON current 200mA

Max OFF current 0.5mA at 60VDC

Note

Only Group 3 can be used for pulse digital outputs.

*With Group 3 cards, the range can be changed to 10-50 mA by changing a resistor on the card. Accuracwill then be 0.2%.

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3-25.4. Interface Specifications

Field wiring to the QLI is through the card edge connector. Prefabricated cabconnections are made with the terminal blocks in the adjacent “B” cabinet.

The QLI itself is grounded by a grounding screw at the bottom front corner ofcard (seeFigure 3-163). This not only grounds the card through its rack but alsallows the IEEE Surge Protection circuitry to function and allows the LIM (LooInterface Module) to function properly.

The card edge connector contains the fuse for both the 24 VDC power supplythe digital inputs and outputs. Recommended ratings for replacement fuses ashown in the installation diagram. The terminal block itself is rated at 5Amaximum, but most applications require a fuse of less than 1A.

Analog inputs are protected up to 120 VDC continuous; digital, up to 150 VDCcontinuous. Both analog and digital input and output circuits meet IEEE/SWCSurge Withstand Standards.

3-25.5. Circuit Description

The QLI contains three analog input channels, each of which has its own circincluding an A/D converter. Analog inputs are converted to binary numbers.Negative inputs are flagged as an under-range condition. The QLI has one anoutput with a D/A converter which converts binary numbers to an analog voltagcurrent value. The QLI also has two digital inputs and two digital outputs.

Incoming analog and digital values to the DPU are stored in DIOB data latchethe QLI and accessed by the DPU for processing. Outgoing analog and digitavalues from the DPU are also stored in data latches on the QLI.

Components

Figure 3-160 shows a functional block diagram of the QLI.

1. Serial Port Control: An RS-422 serial port for communication with a LoopInterface Module (LIM). An on-board microprocessor sends and receives seI/O data for manual loop control through this port.

2. A/D Converters: (Three converters: One for each analog channel) Converincoming analog signals to a digital value. Incoming analog currents are ficonverted to a voltage signal and then to a frequency.

3. D/A Converter: Converts binary signals from the DPU to an analog voltagecurrent.

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4. Digital Input Circuits : Digital inputs pass through signal conditioners, filtersand optical isolators before being read by a microprocessor.

5. Digital Output Circuits : Digital outputs from the DPU go to themicroprocessor and then through optical isolators, signal conditioners, anfilters before leaving the circuit. These outputs are also powered through card edge connector.

6. Switches: Settings of the configuration and EEPROM switches and theconfiguration jumper clips allow the microprocessor to follow the correctcontrol procedures for the configuration chosen.

7. Microprocessor: Controls serial port communication, adjusts analog inputs fgain and offset error, stores configuration data, and performs control functidictated by the configuration data.

8. Memory Controller : Allows the microprocessor to read configuration datafrom the on-board memories and to write configuration data sent to it fromDPU to the On-board EEPROM. This data will then be available for themicroprocessor to read on the next power-up cycle.

9. Memories: Current configuration data is stored in the 1K EEPROM; defauconfiguration data and control programming is stored in the 32K EPROM; ainput, output, and calculation data is stored in the 2K Static RAM.

10.DIOB Bus Arbitration : Controls access to the DIOB data latches. Coordinareading of new data by both the microprocessor and the DPU.

11.DIOB Data Latches: Store input data written by the microprocessor for theDPU to read via the DIOB interface, and output and configuration data writby the DPU via the DIOB interface for the microprocessor to read.

12.DIOB Interface: Places data from the output data latches onto the DIOB dlines and takes data from the DIOB data lines and stores it in the input dalatches.

3-25.6. Card Addressing

Card addressing is in hexadecimal. Addresses begin at 08 and end at F0 and fthe standard Q-Line addressing scheme. The last three bits are always zero; onfirst five bits are set with jumpers.

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3-25. QLI

Note

Installing a jumper encodes a DIOB addressBIT = 1. Installing a jumper encodes a CardConfiguration BIT = 0.

3-25.7. Controls and Indicators

QLI card components are shown inFigure 3-163.

Figure 3-162. QLI Card Address Jumper Example

Figure 3-163. QLI Card Components

28

27

26

25

24

23

22

21

20

Jumper:

Jumper:

Blank

Blank

Jumper:

Jumper:

Jumper:

Jumper:

Jumper:

A7=1

A6=1

A5=0

A4=0

A3=1

0

0

0

Address Enabled

DIOBAddress

CardConfiguration

This jumper must be present forthe QLI to respond to the DPU.

Serial Port

Switches 1-3

EEPROM Switch

LEDs

Connector

POWER OK

CALIBRATION

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Configuration Switches

EEPROM Switch

Controls access to the on-board EEPROM (seeFigure3-163). If the switch is OFF,EEPROM is ignored on power-up and the configuration constants receive defvalues from EPROM. Also, any configuration data written to the QLI will not bstored in EEPROM. If the switch is ON, configuration constants previously writtto the QLI (while the switch was ON) are read from EEPROM on power-up and anew configuration data written to the QLI will be stored in EEPROM for the nepower-up.

Switch No. 1 For all cards configuration types except Digital Positioning tyDigital Output Default : Controls whether to hold digital outputsat their current values during DPU timeout or to go to zero valuOpen = Hold.

For Digital Positioning type configurations only:Initial State Selection: Controls whether the output pulses stawith the ON or OFF state. Open = ON state. This feature isavailable on QLI cards at sub X and later.

Switch No. 2 Power Line Frequency: Choose between 50 and 60 Hz powerline frequency. Open = 50 Hz.

Switch No. 3 Disable DPU Timeout: Controls whether or not QLI will enter atimeout mode if DPU has not written to QLI for more than3 seconds. Open = enable timeout.

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tions:

LED Indicators

Configuration Jumpers

Slots on the card edge connector allow insertion of jumpers for card configuraand addressing (seeFigure 3-162). Choices for card configuration are as follow

POWER OK - LED is lit if proper power to the card is provided.It is ON in normal operation.

CALIBRATION - LED is lit if the card is calibrating or is initializing.It is OFF in normal operation.

Table 3-102. Configuration Jumpers

State Jumper 23 Jumper 22 Jumper 21

NORMAL In In In

NORMAL WITH RAISE/LOWEROVERRIDE

In In Out

MASSFLOW In Out In

MASSFLOW WITH RAISE/LOWER OVERRIDE

In Out Out

DIGITAL POSITIONINGDigital positioning only available forgroup 3.

Out In In

DIGITAL POSITIONING WITHRAISE/LOWER OVERRIDEDigital positioning only available forgroup 3.

Out In Out

Not Used Out Out In

Not Used Out Out Out

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3-25.8. Installation Data Sheet

1 of 4

Figure 3-164. QLI Wiring Diagram: WDPF Powered, Local Grounding

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

(+)

(−)

(+)

SHIELD

(−)

(+)

SHIELD

(−)

(+)

SHIELD

(−)

ANALOG

DIGITAL INPUT 1

I/O DEVICES18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

REQUIRED ENABLE JUMPER

TERMINAL BLOCK HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTOR CUSTOMER CONNECTIONS

DIGITAL INPUT 2

OUTPUT

ANALOGINPUT 1

ANALOGINPUT 2

ANALOGINPUT 3

DIGITAL OUTPUT 1

DIGITAL OUTPUT 2

(+) ANALOG OUTPUT 1 (−)

(−)ANALOG INPUT 1(+)

(−)ANALOG INPUT 2(+)

(−)ANALOG INPUT 3(+)

DIGITAL INPUT 1

DIGITAL INPUT 2

FUSE 1/4A

FUSE 1/4A

FUSE 1/32A

FUSE 1/32A

FUSE 1/32A

FUSE 1/32A

FUSE 1/4A

FUSE 1/4A

+24 VDC24 VDCReturn(Customergrounding)

A

20

19

(AT HALF-SHELL)

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“L”

Installation Data Sheet

2 of 4

Installation Notes (Refer to Figure 3-165)

1. For QLI cards at level 3QLI22 and higher (drawing number 7381A10 sub or higher), the card is not connected to pin 15A and a jumper is present,connecting pin 1A to 3B.

For earlier versions of the QLI, perform the following steps:

a. Remove pin 15A from the card edge connector and tie back the wire.

Figure 3-165. QLI Wiring Diagram: Digital I/O-WDPF PoweredAnalog I/O-Self Powered with Remote Grounding

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

(+)

(−)

(+)

SHIELD

(−)

(+)

SHIELD

(−)

(+)

SHIELD

(−)

ANALOG

DIGITAL INPUT 1

I/O DEVICES18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

REQUIRED ENABLE JUMPER

TERMINAL BLOCK HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTOR CUSTOMER CONNECTIONS

DIGITAL INPUT 2

OUTPUT

ANALOGINPUT 1

ANALOGINPUT 2

ANALOGINPUT 3

DIGITAL OUTPUT 1

DIGITAL OUTPUT 2

(+)ANALOG OUTPUT 1(−)

DIGITAL INPUT 1

DIGITAL INPUT 2

FUSE 1/4A

FUSE 1/4A

FUSE 1/32A

FUSE 1/4A

FUSE 1/4A

+24 VDC24 VDCReturn(Customergrounding)

20

19

+

S

-

ANALOG INPUT 3

+

S

-

ANALOG INPUT 2

+

S

-

ANALOG INPUT 1

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b. Add a jumper between pin 1A and pin 3B on the card edge connector.

2. Analog input devices should be connected with shielded twisted pair cablShield drains and negatives from QLI must be connected to DC power ret

3. DC power return must be grounded

4. Jumpers between terminal block screws 3, 4, 5, 7, 8, 10 and 11 must be a

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For CE MARK Certified System

3 of 4

Installation Notes (Refer to Figure 3-166)

1. The digital outputs must use shielded cable, unless the cabinets are boltetogether and interposing relays are used (as shown above). The actual rewiring depends on the relay style used.

2. The analog output must NOT have the shield tied to the return. However, shield must be connected to earth ground at the B cabinet, as shown.

3. The analog inputs may be grounded at the B cabinet or in the field, as sh

Figure 3-166. QLI CE MARK Wiring Diagram (Analog Inputs Powered at Field Side)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

PE

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

PE

A

(+)

(-)

POINT 3

18

19

20

18

19

20

R1

R0

1

2

6

12

9

13

15

17

16

(−)

(+)24 VDC

(+)

(-)

POINT 2

(+)

(-)

POINT 1

(+)

(-)ANALOGOUTPUT

BIT 1

BIT 2

FUSE SIZE DEPENDENT ONRELAY AND APPLICATION

.25A

.25A

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4 of 4

Installation Notes (Refer to Figure 3-167)

1. The digital outputs must use shielded cable, unless the cabinets are boltetogether and interposing relays are used (as shown above). The actual rewiring depends on the relay style used.

2. The analog output must NOT have the shield tied to the return. However, shield must be connected to earth ground at the B cabinet, as shown.

3. When powering the analog inputs at the WDPF side, the analog inputs shbe grounded at the B cabinet or in the field, as shown.

Figure 3-167. QLI CE MARK Wiring Diagram (Analog Inputs Powered at WDPF System Side)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

PE

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

PE

A

(+)

(-)

POINT 3

18

19

20

18

19

20

R1

R0

1

2

6

12

9

13

15

17

16

(−)

(+)24 VDC

(+)

(-)

POINT 2

(+)

(-)

POINT 1

(+)

(-)ANALOGOUTPUT

BIT 1

BIT 2

FUSE SIZE DEPENDENT ONRELAY AND APPLICATION

.25A

.25A

1/32A

1/32A

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3-26. QLJ

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3-26. QLJ

Q-Line Loop Interface Card with Output Readback(Style 7381A76G01 through G03)

3-26.1. Description

The Q-Line Loop Interface Card (QLJ) handles the analog inputs and outputsassociated with a single or cascaded control loop executing in a Distributed ProUnit (DPU). The QLJ’s I/O capability consists of three analog inputs, and oneanalog output with readback. Communications to and from the card are throuDistributed Input/Output Bus (DIOB).

Figure 3-168. QLJ Functional Block Diagram

DIOB

DIOB Interface

DIOB Bus Arbitration,

A/D A/D A/D D/A

RS 422Serial Link

EE PROM Processor

EPROM

RAM

(+) (−) (+) (−) (+) (−) (+) (−)

AnalogOutput

Analog Inputs

Memory

A/D

(+) (−)

InternalReadback

Timing Control

Jumpers, Switches

Data Latches

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The QLJ may be linked to a Loop Interface Module (LIM) used for monitoring amanual control of the QLJ’s control loop (seeFigure 3-169).

Analog input voltages or currents are converted by the QLJ to binary numbersrate of four times per second. They are stored by the QLJ until they are read bDPU. Binary numbers from the DPU are converted to output voltages or currena rate greater than 10 times/second.

Figure 3-169. QLJ Card Overview

LIM

Flat Flex(Up to 12QLJ’s onchain)

Twisted Pair

TransitionPanelMultiple QLJs(LIM or SLIM)

LIM

Twisted Pair(One QLJ/LIMor SLIM)

DPU

Q-Crate

DataHighway

TCP

DPU

QBE

QTB

QLJ

#1

QLJ

#2

QLJ

#3

QLJ

#4

QLJ

#28

QLJ

#29

QLJ

#30

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ack

.1%

00

ions.

Three versions of the QLJ are available, distinguished by their analog input aoutput value ranges:

Group 3 QLJs may be modified to accept 10-50 mA input by changing a 250input resistor on the card to a 100 ohm resistor. Changing the resistor to 100 ointroduces an error of 0.2%.

The Q crate delivers 13 VDC at the rear edge pin connectors. This is the poweall logic and communications on the card.

The QLJ automatically checks for 13-volt power supply malfunctions as well amany of its own malfunctions. Malfunctions are displayed by the program runnin the DPU.

Additional information related to the installation and operation of the QLJ canfound in “Q-Line Loop Interface Card and Loop Interface Module (QLI/LIM)User’s Guide” (NLAM-B200).

3-26.2. Features

• Three analog input circuits and one analog output circuit with internal readband range checking. Analog circuitry is isolated from the logic circuitry.

• Choice of analog input and output ranges.

• Analog-to-digital conversion rate of 4 times per second with an accuracy of 0

• Automatic adjustment for gain and offset temperature coefficients of analoginputs.

• IEEE/SWC surge withstand protection for analog inputs and outputs.

• Interfaces with the DPU through a Distributed Input/Output Bus (DIOB).

• Configuration switches to customize operation.

• Serial port connection to Loop Interface Module (LIM). RS-422 and up to 10feet long.

• Automatic diagnostic program detects 13V power supply and QLJ malfunct

Version Analog Input Analog Output

Group 1 0 - 10 V 0 - 10 V

Group 2 0 - 5 V 0 - 10 V

Group 3 0 - 20 mA 4 - 20 mA

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able

f theop

d

ill

.

• Detects and flags over- and under-range conditions.

3-26.3. Specifications

Analog Input

Input ranges Group 1 0-10 VDCGroup 2 0-5 VDCGroup 3 0-20 mA *

A/D conversion type voltage-to-frequency

Conversion rate 4/sec

Accuracy 0.1%

Impedance 100 megohms/volt, 1000 ohms in overload

Resolution 12 bits

Analog Output

Output ranges Group 1 0-10 VDCGroup 2 0-10 VDCGroup 3 4-20 mA **

Loading 0-1000 Ohms for current500 Ohms minimum for voltage

Resolution 12 bits, unipolar

Accuracy 0.1%

AO Readback A/D resolution 8 bits

Accuracy of readback 3.125% (5 bits)

Circuit Specifications

Field wiring to the QLJ is through the front card edge connector. Prefabricated cconnections are made with the terminal blocks in the adjacent “B” cabinet.

The QLJ itself is grounded by a grounding screw at the bottom front corner ocard (seeFigure 3-171). This not only grounds the card through its rack but alsallows the IEEE Surge Protection circuitry to function and allows the LIM (LooInterface Module) to function properly.

Analog inputs are protected up to 120 VDC continuous; digital, up to 150 VDCcontinuous. Analog input and output circuits meet IEEE/SWC Surge WithstanStandards.With Group 3 cards

*With Group 3 cards, the range can be changed to 10-50mA by changing a resistor on the card. Accuracy wthen be 0.2%.** AO is totally isolated from the rest of the card. The shield can be connected to earth ground in the field

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3-26.4. Circuit Description

The QLJ contains three analog input channels, each of which has its own circincluding an A/D converter. Analog inputs are converted to binary numbers.Negative inputs are flagged as an under-range condition. The QLJ has one aoutput with a D/A converter which converts binary numbers to an analog voltagcurrent value. This analog output is read back and converted to linear numberscan be read by the DPU.

Incoming analog values to the DPU are stored in DIOB data latches on the QLJaccessed by the DPU for processing. Outgoing analog values from the DPU arestored in data latches on the QLJ.

Components

Figure 3-168 shows a functional block diagram of the QLJ.

1. Serial Port Control: An RS-422 serial port for communication with a LoopInterface Module (LIM). An on-board microprocessor sends and receives seI/O data for manual loop control through this port.

2. A/D Converters: (Three converters: One for each analog channel) Converincoming analog signals to a digital value. Incoming analog currents are ficonverted to a voltage signal and then to a frequency.

3. AO Readback: A/D converts analog output signal directly to a digital value

4. D/A Converter: Converts binary signals from the DPU to an analog voltagecurrent.

5. Switches: Settings of the configuration and EEPROM switches and theconfiguration jumper clips allow the microprocessor to follow the correctcontrol procedures for the configuration chosen.

6. Microprocessor:Controls serial port communication, adjusts analog inputs fgain and offset error, stores configuration data, and performs control functdictated by the configuration data.

7. Timing and Control Circuitry : Generates the signals needed for the input aoutput circuits and the microprocessor. Based on an 11.0592-MHz clock.

8. Memories: Current configuration data is stored in the 1K EEPROM; defauconfiguration data and control programming is stored in the 32K EPROM; ainput, output, and calculation data is stored in the 2K Static RAM.

9. DIOB Bus Arbitration : Controls access to the DIOB data latches. Coordinareading of new data by both the microprocessor and the DPU.

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10.DIOB Data Latches: Store input data written by the microprocessor for theDPU to read via the DIOB interface, and output and configuration data writby the DPU via the DIOB interface for the microprocessor to read.

11.DIOB Interface: Places data from the output data latches onto the DIOB dlines and takes data from the DIOB data lines and stores it in the input dalatches.

3-26.5. Card Addressing

Card addressing is in hexadecimal. Addresses begin at 08 and end at F0 and fthe standard Q-Line addressing scheme. The last three bits are always zero; onfirst five bits are set with jumpers.

Note

Installing a jumper encodes a DIOB addressBIT = 1. Installing a jumper encodes a CardConfiguration BIT = 0

Figure 3-170. QLJ Card Address Jumper Example

28

27

26

25

24

23

22

21

20

Jumper:

Jumper:

Blank

Blank

Jumper:

Jumper:

Jumper:

Jumper:

Jumper:

A7=1

A6=1

A5=0

A4=0

A3=1

0

0

0

Address Enabled

DIOBAddress

CardConfiguration

This jumper must be present forthe QLJ to respond to the DPU.

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re

3-26.6. Controls and Indicators

QLJ card components are shown inFigure 3-171.

Configuration Switches (Four Position DIP Switch)

EEPROM Toggle Switch

Controls access to the on-board EEPROM. If the switch is OFF, EEPROM isignored on power-up and the configuration constants receive default values fEPROM. Also, any configuration data written to the QLJ will not be stored inEEPROM. If the switch is ON, configuration constants previously written to thQLJ (while the switch was ON) are read from EEPROM on power-up and any nconfiguration data written to the QLJ will be stored in EEPROM for the nextpower-up.

Figure 3-171. QLJ Card Components

Switch Pos. No. 1 Not used.

Switch Pos. No. 2 Power Line Frequency: Choose between 50 and 60 Hzpower line frequency. Open = 50 Hz.

Switch Pos. No. 3 Disable DPU Timeout: Controls whether or not QLJ willenter a timeout mode if DPU has not written to QLJ for mothan 3 seconds. Open = enable timeout.

Switch Pos. No. 4 Not used.

Serial Port

Switches 1-3

EEPROMSwitch

Error Jumper

LEDs

POKCAL

M0-0053 3-338 5/99Westinghouse Proprietary Class 2C

Page 405: Ovation Q Line

3-26. QLJ

r to

Serial Port Error Jumper

Determines how the absence of a serial port is reported to the DPU.

Position 1-2 installed jumper – Report serial port errors

Position 2-3 installed jumper – Do not report serial port connector off as an errothe DPU.

Configuration Jumper Clips

Slots on the card edge connector allow insertion of jumper clips for cardconfiguration and addressing. Choices for card configuration are as follow:

LED Indicators

Table 3-103. Configuration Jumpers

State Jumper 23 Jumper 22 Jumper 21

NORMAL In In In

MASSFLOW In Out In

All other configurations are invalid.

POWER OK - LED is lit if proper power to the card is provided.It is ON in normal operation.

CALIBRATION - LED is lit if the card is calibrating or is initializing.It is OFF in normal operation.

5/99 3-339 M0-0053Westinghouse Proprietary Class 2C

Page 406: Ovation Q Line

3-26. QLJ

in the

, &

3-26.7. Installation Data Sheet

1of 2

Installation Notes (Refer to Figure 3-172)

A. If inputs are to be grounded at the system end, insert a #6 screw and nut hole located near the shield terminal on Terminal Block A. Then add twojumpers as shown below. Six holes, located next to terminals 2, 5, 8, 11, 1417, have been drilled for this purpose.

Figure 3-172. QLJ Wiring Diagram

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

EDGE CONNECTOR

ANALOG

(+)

(SHIELD)

(−)

ANALOG

(+)

(SHIELD)

(−)

ANALOG

(+)

(SHIELD)

(−)

ANALOG

(+)

(SHIELD)

(−)

(+)

(SHIELD)

(−)

ANALOG

(+)

(SHIELD)

(−)

(+)

(SHIELD)

(−)

(+)

(SHIELD)

(−)

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK

20B

20A

OUTPUT

INPUT 1

INPUT 2

INPUT 3

OUTPUT 1

ANALOGINPUT 1

ANALOGINPUT 2

ANALOGINPUT 3

REQUIRED ENABLE JUMPER

20

19

M0-0053 3-340 5/99Westinghouse Proprietary Class 2C

Page 407: Ovation Q Line

3-26. QLJ

B. If inputs are to be grounded at the signal source, ground both the (−) side of thesignal and the cable shield as shown below.

Figure 3-173. QLJ Ground Inputs at System End

Figure 3-174. QLJ Ground Inputs at Signal Source

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

#6 SCREW

TRANSDUCER

(+)

(−)

(+)

(−)

S

A

5/99 3-341 M0-0053Westinghouse Proprietary Class 2C

Page 408: Ovation Q Line

3-26. QLJ

es.turn.

dded.

Installation Data Sheet

2 of 2

Installation Notes (Refer to Figure 3-175)

1. Jumper 1A - 3B is connected only for QLJ’s sub D and later. For earlierversions, this jumper should be added.

2. Analog input devices should be connected with shielded twisted pair cablShield drains and negatives from QLJ must be connected to DC power re

3. DC power return must be grounded.

4. Jumpers between terminal block screws 3, 4, 5, 7, 8, 10, and 11 must be a

Figure 3-175. QLJ Fused Half-Shell Extension Wiring

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

(+)

(−)

(+)

SHIELD

(−)

(+)

SHIELD

(−)

(+)

SHIELD

(−)

ANALOG

I/O DEVICES18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

REQUIRED ENABLE JUMPER

TERMINAL BLOCK HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTOR CUSTOMER CONNECTIONS

OUTPUT

ANALOGINPUT 1

ANALOGINPUT 2

ANALOGINPUT 3

(−)ANALOG INPUT 1(+)

(−)ANALOG INPUT 2(+)

(−)ANALOG INPUT 3(+)

FUSE 1/4A

FUSE 1/4A

FUSE 1/32A

FUSE 1/32A

FUSE 1/32A

FUSE 1/32A

(+)ANALOG OUTPUT 1(−)

20

19

20

19

M0-0053 3-342 5/99Westinghouse Proprietary Class 2C

Page 409: Ovation Q Line

3-27. LIM

d

rdss

3-27. LIM

Loop Interface Module(Style 1D54561G01 through G02)

3-27.1. Description

The Loop Interface Module (LIM) provides the displays, keyboards inputs, anaccompanying logic needed for the operator to monitor and control the I/Ofunctions of a QLI (Q-Line Loop Interface).

Information is presented to the operator by various bargraphs, LEDs, numericdisplays and alphanumeric displays on the front panel of the LIM. The keyboaallows the operator to send control information to the QLI to control the proce(seeFigure 3-176).

Figure 3-176. Loop Interface Module

5/99 3-343 M0-0053Westinghouse Proprietary Class 2C

Page 410: Ovation Q Line

3-27. LIM

3-27.2. Features

Through keys on the front of the LIM panel, the operator has the followingcapabilities:

• Raise output

• Lower output

• Raise setpoint

• Lower setpoint

• Change LIM mode (Group 1 only)

• Change alphanumeric and numeric displays

• Change to different QLI (with different loop number) (Group 1 only)

• Change QLI mode to Cascade (Group 1 only)

• Change QLI mode to Auto

Figure 3-177. LIM Functional Block Diagram

10

9

8

7

BargraphDisplay

StatusLeds

NumericDisplay

NumericDisplay

Alpha

6

4

Micro-Processor

1

KeyboardInterface

2

SerialPort

Input/Output

3

5

InterfaceUser Power

SupplyFrom User Power Ok

To All Components

QliTo/from

DisplayController

AndControl

Timing

M0-0053 3-344 5/99Westinghouse Proprietary Class 2C

Page 411: Ovation Q Line

3-27. LIM

QLI

• Change QLI mode to Manual

• Change QLI mode to Local

• Change QLI tuning constants (Group 1 only)

Additional information on the installation and use of the LIM can be found in“Q-LineLoopInterfaceCardandLoopInterfaceModule(QLI/LIM) User’sGuide”(NLAM- B200).

Additional Features

• Runs bargraphs, LEDs, and alphanumeric and numeric displays to monitorI/O activities.

• Scans keypad to control QLIs

• Monitors and communicates with up to 12 QLIs

• Group 1 LIMs operate in four modes: CONTROL, MONITOR, TUNING,LOOP. Group 2 operates in CONTROL mode only.

• Sends and receives information to and from the QLI through a serial port.

• Flags a break in the communication link with the QLI

• Allows loop control even if DPU is down

• Displays:

two 40-segment bargraphs

one 30-segment bargraph

one 4-digit numeric

one 4-digit alphanumeric

thirteen status LEDs

• Control keys:

5/99 3-345 M0-0053Westinghouse Proprietary Class 2C

Page 412: Ovation Q Line

3-27. LIM

OP,

for

I

ndn

og

foror

to

four keys to raise and lower setpoint and outputs

seven function keys

Groups

The LIM card is packaged in one of two assemblies (seeFigure3-178). The card isthe same for both assemblies, although the PROMs will have been burneddifferently. They keyboards are the same except Group 2 does not have the LOCASC, and MODE buttons.

The four modes of operation for the LIM are as follows:

Group 1 Allows the operator to choose from among four modes of operationthe LIM and four for the QLI.

Group 2 Offers no choice of modes for the LIM; it always operates in theCONTROL mode. Offers three choices of operation of the QLI.

CONTROLMODE:

Allows the operator to send control information to the QLthrough a keyboard; displays the process variable, thesetpoint, and output value for the QLI on a bargraph, adisplays PV, SP, or OUT with proper engineering units oan alphanumeric display.

MONITOR MODE:(Group 1 only)

Displays the process variable, the setpoint, and outputvalues for the QLI on a bargraph and displays the analinput values on an alphanumeric display.

TUNING MODE:(Group 1 only)

Displays the gain, reset, rate, and derivative gain valuesthe QLI it is communicating with and enables the operatto change the values. Requires a password.

LOOP MODE:(Group 1 only)

Displays the Loop Number of the QLI the LIM is currentlycommunicating with and allows the operator to changeanother QLI.

M0-0053 3-346 5/99Westinghouse Proprietary Class 2C

Page 413: Ovation Q Line

3-27. LIM

Figure 3-178. Keyboards for Group 1 and Group 2 LIMs

AUTO

MAN

LOC

DISP

AUTO

MAN

LOC

DISP

MODE

LOOP

CASC

GROUP 1 GROUP 2

5/99 3-347 M0-0053Westinghouse Proprietary Class 2C

Page 414: Ovation Q Line

3-27. LIM

withis

IMs;

3-27.3. Specifications

Power cables to the LIM must be single stranded #16 AWG copper conductorsring lugs on both ends. Power required at the black terminal block of the LIM 1.5A at 12 VDC (seeTable 3-104). No shielding is required. A backup powersupply is optional.

In installations with more than one LIM, each LIM should have its own pair ofconductors directly from the power supply. If LIMs are connected in parallel,conductors must be able to accommodate the total current requirement for all Lvoltage must measure 12 VDC at the last LIM in the line.

Figure 3-179. LIM Wiring

Table 3-104. LIM Power Card-Edge Terminal Block Connector

Component Side Pin Description

1 Chassis (Earth) Ground

2 Chassis (Earth) Ground

3 Chassis (Earth) Ground

4 Chassis (Earth) Ground

5 Signal (“–”)

6 Signal (“–”)

7 +12V B

8 +12V A

+12V A (8)

+12V B

Signal “-”

SerialPort

Signal “-”

(1)

M0-0053 3-348 5/99Westinghouse Proprietary Class 2C

Page 415: Ovation Q Line

3-27. LIM

toancterdr

LI.teLI

ort,lock.

ng

3-27.4. Circuit Description

The LIM card contains the logic to send and receive information from the QLIallow the operator to monitor and control the QLI’s I/O activities. The operator cmonitor the activities on three bargraphs, a 4-digit numeric display, a 4-charaalphanumeric display, and 13 status LEDs. The I/O activities can be controllethrough an 11-key keyboard for Group 1 assemblies or an 11-key keyboard foGroup 2 assemblies.

3-27.5. Components

A functional block diagram of the LIM card is shown inFigure 3-177.

1. Keyboard Interface: Allows the operator to control the I/O activities of theQLI.

2. Serial Port (seeTable 3-105): Receives display and status data from the QAlso sends operator inputs from the keyboard to the QLI. Can communicawith only one QLI at a time. The LIM must enter Loop Mode to change the Qwith which it is communicating.

3. Timing and Control : Generates the signals needed to coordinate the serial pkeyboard scans, displays, and microprocessor. Based on a 11.0592-MHz-c

4. Microprocessor: Scans the keyboard and determines what action (if any)should be taken, formats outgoing serial port messages, interprets incomiserial port messages, and maintains the various displays.

5. User Power Interface: Provides the regulated voltages needed by the logiccircuitry and provides the POWER OK signal for the microprocessor. Alsoprovides the voltages needed by the various displays.

Table 3-105. LIM Serial Port Card-Edge Connector

Component Side Pin Description

1 Transmit+

2 Transmit−

3 Shield (Signal Ground)

4 Receive+

5 Receive−

6 through 10 Not Used

5/99 3-349 M0-0053Westinghouse Proprietary Class 2C

Page 416: Ovation Q Line

3-27. LIM

n

aphs,

it

s

6. Display Controller: Provides multiplexing control for the status LEDs,bargraphs, and the numeric display. The alphanumeric display has its owmultiplexing circuitry.

7. Bargraph Displays: Can display either the setpoint, process variable, andoutput values. The setpoint and process variable are on 40-segment bargrthe output is on a 30-segment bargraph.

8. Status LEDs: Thirteen status LEDs display the LIM mode, the QLI mode,which value is currently being displayed by the numeric display, and high-limand low-limit alarm conditions.

9. Numeric Displays: Shows a numeric value for the setpoint, output, procesvariable, or analog inputs. This value will be scaled to the appropriateengineering units for the value of the numeric display.

10.Alphanumeric Display: Can give the name of the engineering units for thevalue of the numeric display, or can give status or mode information.

M0-0053 3-350 5/99Westinghouse Proprietary Class 2C

Page 417: Ovation Q Line

3-28. SLIM

ts,O

oardss

3-28. SLIM

Small Lop Interface Module(Style 4D33741G01 through G02)

3-28.1. Description

Applicable for use in the CE MARK Certified System

The Small Loop Interface Module (SLIM) provides the displays, keyboards inpuand accompanying logic needed for the operator to monitor and control the I/functions of a QLI (Q-Line Loop Interface).

Information is presented to the operator by various bargraphs, LEDs, numericdisplays and alphanumeric displays on the front panel of the SLIM. The keyballows the operator to send control information to the QLI to control the proce(seeFigure 3-180).

Figure 3-180. SLIM Small Loop Interface Module

Disp

Auto

Man

Loc

SP/Bias

Out

0

20

40

60

80

100

0 20 40 60 80 100

RejecttoLocal

PV SP Out

WDPF II

SLIM Enclosure

SLIM

5/99 3-351 M0-0053Westinghouse Proprietary Class 2C

Page 418: Ovation Q Line

3-28. SLIM

Block Diagram

3-28.2. Features

Through keys on the front of the SLIM panel, the operator has the followingcapabilities:

• Raise output

• Lower output

• Raise setpoint

• Lower setpoint

• Change SLIM mode (Group 1 only)

• Change alphanumeric and numeric displays

• Change to different QLI (with different loop number) (Group 1 only)

• Change QLI mode to Cascade (Group 1 only)

Figure 3-181. SLIM Functional Block Diagram

10

9

8

7

BargraphDisplay

StatusLeds

NumericDisplay

NumericDisplay

Alpha

6

4

Micro-Processor

1

KeyboardInterface

2

SerialPort

Input/Output

3

5

InterfaceUser Power

SupplyFrom User Power Ok

To All Components

QLITo/from

DisplayController

AndControl

Timing

M0-0053 3-352 5/99Westinghouse Proprietary Class 2C

Page 419: Ovation Q Line

3-28. SLIM

QLI

• Change QLI mode to Auto

• Change QLI mode to Manual

• Change QLI mode to Local

• Change QLI turning constants (Group 1 only)

Additional information on the installation and use of the SLIM can be found in“Q-LineLoopInterfaceCardandLoopInterfaceModule(QLI/LIM) User’sGuide”(NLAM- B200).

• Runs bargraphs, LEDs, and alphanumeric and numeric displays to monitorI/O activities.

• Scans keypad to control QLIs

• Monitors and communicates with up to 12 QLIs

• Group 1 SLIMs operate in four modes: CONTROL, MONITOR, TUNING,LOOP. Group 2 operates in CONTROL mode only.

• Sends and receives information to and from the QLI through a serial port.

• Flags a break in the communication link with the QLI

• Allows loop control even if DPU is down

• Displays:

two 40-segment bargraphs

one 30-segment bargraph

one 4-digit numeric

one 4-digit alphanumeric

thirteen status LEDs

• Control keys:

four keys to raise and lower setpoint and outputs

seven function keys

5/99 3-353 M0-0053Westinghouse Proprietary Class 2C

Page 420: Ovation Q Line

3-28. SLIM

rnedOP,

for

ele,h,g

utog

es

.

r

Groups

The SLIM card is packaged in one of the two assemblies (seeFigure 3-178). Thecard is the same for both assemblies, although the PROMs will have been budifferently. They keyboards are the same except Group 2 does not have the LOCASC, and MODE buttons.

The four modes of operation for the SLIM are as follows:

Group 1 Allows the operator to choose from among four modes of operationthe SLIM and four for the QLI.

Group 2 Offers no choice of modes for the SLIM; it always operates in theCONTROL mode. Offers three choices of operation of the QLI.

CONTROL MODE: Allows the operator to send control information to thQLI through a keyboard; displays the process variabthe setpoint, and output value for the QLI on a bargrapand displays PV, SP, or OUT with proper engineerinunits on an alphanumeric display.

MONITOR MODE:(Group 1 only)

Displays the process variable, the setpoint, and outpvalues for the QLI on a bargraph and displays the analinput values on an alphanumeric display.

TUNING MODE:(Group 1 only)

Displays the gain, reset, rate, and derivative gain valufor the QLI it is communicating with and enables theoperator to change the values. Requires a password

LOOP MODE:(Group 1 only)

Displays the Loop Number of the QLI the SLIM iscurrently communicating with and allows the operatoto change to another QLI.

M0-0053 3-354 5/99Westinghouse Proprietary Class 2C

Page 421: Ovation Q Line

3-28. SLIM

Figure 3-182. Keyboards for Group 1 and Group 2 SLIMs

Disp

Auto

Man

Loc

SP/Bias

Out

0

20

40

60

80

100

0 20 40 60 80 100

RejecttoLocal

PV SP Out

WDPF II

Disp

Auto

Man

Loc

SP/Bias

Out

0

20

40

60

80

100

0 20 40 60 80 100

RejecttoLocal

AI1

SP Out

Casc

MCT

Loop

Mode

AI2 AI3

PV

WDPF II

5/99 3-355 M0-0053Westinghouse Proprietary Class 2C

Page 422: Ovation Q Line

3-28. SLIM

orsIMr

of,l

I toancterdr

3-28.3. Specifications

Power cables to the SLIM must be single stranded #16 AWG copper conductwith ring lugs on both ends. Power required at the black terminal block of the SLis 0.5A at 12 VDC (seeFigure 3-183). No shielding is required. A backup powesupply is optional.

In installations with more than one SLIM, each SLIM should have its own pairconductors directly from the power supply. If SLIMs are connected in parallelconductors must be able to accommodate the total current requirement for alSLIMs; voltage must measure 12 VDC at the last SLIM in the line.

3-28.4. Circuit Description

The SLIM card contains the logic to send and receive information from the QLallow the operator to monitor and control the QLI’s I/O activities. The operator cmonitor the activities on three bargraphs, a 4-digit numeric display, a 4-charaalphanumeric display, and 13 status LEDs. The I/O activities can be controllethrough an 11-key keyboard for Group 1 assemblies or an 11-key keyboard foGroup 2 assemblies.

3-28.5. Components

A functional block diagram of the SLIM card is shown inFigure 3-181.

1. Keyboard Interface: Allows the operator to control the I/O activities of theQLI.

Figure 3-183. SLIM Wiring

+12A

+12B

RTN

RTN

SerialPort

M0-0053 3-356 5/99Westinghouse Proprietary Class 2C

Page 423: Ovation Q Line

3-28. SLIM

LI.tee

ort,lock.

ng

n

the

,it

s

2. Serial Port (seeTable 3-106): Receives display and status data from the QAlso sends operator inputs from the keyboard to the QLI. Can communicawith only one QLI at a time. The SLIM must enter Loop Mode to change thQLI with which it is communicating.

3. Timing and Control : Generates the signals needed to coordinate the serial pkeyboard scans, displays, and microprocessor. Based on a 11.0592-MHz-c

4. Microprocessor: Scans the keyboard and determines what action (if any)should be taken, formats outgoing serial port messages, interprets incomiserial port messages, and maintains the various displays.

5. User Power Interface: Provides the regulated voltages needed by the logiccircuitry and provides the POWER OK signal for the microprocessor. Alsoprovides the voltages needed by the various displays.

6. Display Controller: Provides multiplexing control for the status LEDs,bargraphs, and the numeric display. The alphanumeric display has its owmultiplexing circuitry.

7. Bargraph Displays: Can display the setpoint, process variable, or outputvalues. The setpoint and process variable are on 30-segment bargraphs, output is on a 20-segment bargraph.

8. Status LEDs: Thirteen status LEDs display the SLIM mode, the QLI modewhich value is currently being displayed by the numeric display, and high-limand low-limit alarm conditions.

9. Numeric Displays: Shows a numeric value for the setpoint, output, procesvariable, or analog inputs. This value will be scaled to the appropriateengineering units for the value of the numeric display.

10.Alphanumeric Display: Can give the name of the engineering units for thevalue of the numeric display, or can give status or mode information.

Table 3-106. SLIM Serial Port Card-Edge Connector

Component Side Pin Description

1 Transmit+

2 Transmit−

3 Shield (Signal Ground)

4 Receive+

5 Receive−

6 through 10 Not Used

5/99 3-357 M0-0053Westinghouse Proprietary Class 2C

Page 424: Ovation Q Line

3-28. SLIM

g

ideMtion

the.

he

SLIM use in the CE MARK Certified System

The SLIM is applicable for use in the CE MARK certified system. The followinrules apply:

• A transition panel kit (Westinghouse drawing number 3A59353) is used insthe DPU to provide an earth grounding point for the shields of the QLI/SLIcable (Westinghouse drawing number 5A26130) and the internal QLI transipanel cable (Westinghouse drawing number 5A26127).

• Cable 5A26130 (SLIM to transition panel) provides the connection betweenSLIM and the transition panel. It is connected to (internal) cable 5A26127

• Cable 5A26127 (QLI/SLIM transition panel) provides the connection from ttransition panel to the QLI. It is connected to cable 5A26130.

M0-0053 3-358 5/99Westinghouse Proprietary Class 2C

Page 425: Ovation Q Line

3-29. QMT

us

3-29. QMT

M-Bus Terminator Card(Style 7379A79G01 through G03)

3-29.1. Description

The QMT card provides a variety of support functions for the Q-line Memory B(M-bus) and Distributed Input/Output Bus (DIOB) (seeFigure 3-184). The QMTcard is available in three design groups (G01, G02, and G03).

3-29.2. Features

All QMT cards (G03, G02, and G01) provide the following Q-line supportfunctions:

• Voltage threshold selection for the following power supplies:

— +V Primary (+13V)

Figure 3-184. QMT Block Diagram

UIOBor DIOBPowerStatus

Monitor

DIOB

Read,Write,

and DMAInterruptRecovery

DeadComputerRecovery

PowerSupplyMonitor

On-CardPower

Supplies

DIOB Bus Extension

Optional Q-line M-bus

120ΩTerminators

Dischargeand

Clamp

Bus

5/99 3-359 M0-0053Westinghouse Proprietary Class 2C

Page 426: Ovation Q Line

3-29. QMT

atus

ne

e

— +V Backup (+13V)

• All DIOB signals are diode clamped to+15 VDC and 0 VDC

• DIOB extension through two front-edge connector

• Two form-C, dry-circuit relays indicating primary and secondary DIOB power st

The G02 QMT cards add the following Q-line support functions:

• Voltage threshold detection for the following power supplies:

— +12 Auctioneered (+12 VDC)

— +5 Internal (+5 VDC)

— +15 (+15 VDC DIOB clamp supply)

• DIOB discharge

The G01 QMT cards include all of the G02 functions and add the following Q-lisupport functions:

• 120Ω termination to+5 VDC for 33 M-bus signals

• +5 VDC at 2A for microcomputer termination and bus transceiver power

• Voltage threshold detection for the following power supply:

— +5T (M-bus) (+5 VDC)

• Time-out detection and recovery for the following M-bus conditions:

— Missing READY on READ cycle

— Missing READY on WRITE cycle

— Incomplete Direct Memory Access (DMA) cycle

— Missing READY on INTERRUPT OPCODE cycle

— “Dead Computer” reset (optional)

— Sequence fault (READY•REL↑)

— All DIOB signals are diode clamped to+15 VDC and 0 VDC

The QMT card is designed to be installed in a standard Q-line card cage in thvertical position and it occupies card slot number 25 in all M-bus card cages.

M0-0053 3-360 5/99Westinghouse Proprietary Class 2C

Page 427: Ovation Q Line

3-29. QMT

Block Diagram

Figure 3-185. QMT Card Functional Block Diagram

J5CONNECTOR

J3 CONNECTOR

DIOB EXTENSION(WITHOUT POWER)

J4 CONNECTOR

J1 CONNECTOR(DIOB)

DIOBDISCHARGE

ANDCLAMP

MBUSTERMINATION

(120 Ω5 V)

READWRITEDMA

INTERRUPTRECOVERY

+5 VDCAT2 A

+5 VDCAT2 A

+15 VDCAT

10 MA

INTERNALLOGIC (VCC)POWER SUPPLY

M-BUS TERMINATIONPOWER SUPPLY

DIOB CLAMPPOWER SUPPLY

CHASSISPOWER MONITORRELAYS

DEADCOMPUTERRECOVERY

POWERSUPPLY

MONITOR

J2 CONNECTOR(M-BUS)

5/99 3-361 M0-0053Westinghouse Proprietary Class 2C

Page 428: Ovation Q Line

3-29. QMT

ors.

MTline

MTline

Power Requirements

Signal Interface

The QMT card interfaces with the Q-line system through five electrical connectThe connector names and locations are shown inFigure 3-186. Descriptions ofindividual connector functions are provided followingFigure 3-186:

• J1 Connector: The J1 connector is a 34-pin DIOB signal interface to the Qcard. The J1 connector plugs into the backplane of a standard 19 inch Q-card cage.

• J2 Connector: The J2 connector is a 50-pin M-bus signal interface to the Qcard. The J2 connector plugs into the backplane of a standard 19 inch, Q-card cage.

Minimum Nominal Maximum

Primary Voltage 12.4 VDC + 13.0 VDC 13.1 VDC

Backup 12.4 VDC -- 13.1 VDC

Current 2A 3A

Power Consumption 26 watts 39.3 watts

Figure 3-186. QMT Card Connectors

J1

J2

J5

J3

J4

M0-0053 3-362 5/99Westinghouse Proprietary Class 2C

Page 429: Ovation Q Line

3-29. QMT

nd the-flex

toredJ5

• J3 and J4 Connectors: The J3 and J4 34-pin connectors are used to exteDIOB signals to other card crates. Female front-edge connectors with flatribbon cable are used to transfer the DIOB signals.

• J5 Connector: The J5 connector is a 9-pin connector that is used as anapplication interface for the QMT card power monitor relays. The J5 connecis a board mounted connector that transfers the relay signals to any desirlocation.Table 3-107 shows the pin connections and signal names for the connector.

3-29.3. Input/Output Signal Requirements

M-bus signals: Complies with M-bus interface requirementsDIOB signals: Complies with DIOB interface requirements

Fuses

The QMT card uses six fuses for over current protection.Table 3-108 shows thename, rating and function of each fuse.

Table 3-107. QMT J5 (Power Monitor Relay) Pin Connections and Signal Names

Pin No. Signal Name

1 PCOM

2 BCOM

3 +12 AX

4 BNC

5 GROUND

6 PNO

7 BNO

8 PNC

9 (Not Connected)

Table 3-108. QMT Card Fuse Ratings and Locations

Fuse Name Rating (Amperes) Function

M192-1 1 +12V Auctioneered Out to J5-3

M196-1 2 +5T Power Supply Output

M196-2 2 +5 Power Supply Output

5/99 3-363 M0-0053Westinghouse Proprietary Class 2C

Page 430: Ovation Q Line

3-29. QMT

unted

hiler

.

Wiring

Electrical connection to the Q-line system is made by two backplane plug-inconnectors (J1 and J2), two front-edge connectors (J3 and J4) and a side mo(component side) connector (J5) (seeFigure 3-186).

The J1 and J2 connectors are, respectively, the DIOB and M-bus connectors wthe J3 and J4 connectors provide for DIOB cable extension. The J5 connectoprovides connection to the primary and backup power monitor relay contacts

M272-1 3 +12 Auctioneered Main Input

H60-1 .25 +V Primary Comparator Input

H60-2 .25 +V Backup Comparator Input

Table 3-108. QMT Card Fuse Ratings and Locations

Fuse Name Rating (Amperes) Function

M0-0053 3-364 5/99Westinghouse Proprietary Class 2C

Page 431: Ovation Q Line

3-30. QPA

temnd

ts mays. Theents,

3-30. QPA

Pulse Accumulator(Style 7379A13G01 through G04)

3-30.1. Description

Groups 01 through 04 are Applicable for use in the CE MARK Certified System

The QPA card accumulates the pulse inputs that are normally counted by the syscontroller. This configuration allows the system controller to perform other control adata acquisition tasks and permits higher rates of pulse inputs. These pulse inpuoriginate from devices such as position encoders, tachometers and flow-rate meterQPA performs average speed measurements, average inverse speed measuremelapsed time measurements and speed ratio measurements (seeFigure 3-187).

Figure 3-187. QPA Block Diagram

Control

Compare

FieldControlLogic

2:1 MUX

Latch

DataDIOB

Data

Field ControlField Clock

PHA PHB

Status

Up/DownCounter

StatusRead

DIOB Data

Field Clock Inputs

PHA PHB

G04 OnlyRegisterMSB

Up/DownCounter

2:1 MUXLatch

Inputs Inputs

5/99 3-365 M0-0053Westinghouse Proprietary Class 2C

Page 432: Ovation Q Line

3-30. QPA

edge theputcted.

ter

pare

teister.

zethe

bya

tedThevel

ntainbase)s of aThele tozero,

word.manyhe

The QPA interfaces with the Distributed Input Output Bus (DIOB) through arear-edge connector, J1. Ten field inputs are brought onto the card via a front-connector, J3. A 25-pin “D” type connector is located on the top front-edge ofcard (J2). The J2 connector is used to interface QPA comparator register outsignals to QPA counter control inputs. It also permits various options to be sele

3-30.2. Definitions

Frozen– This signal indicates that the counter is still counting, but the last counvalue before freezing is stored in the latch that is read by the DIOB.

FLAG – This signal is set by an exact comparison of the counter and the comregister. It is reset by a power-up or a status read command.

Compare– This signal is active only when a comparison is valid. It will deactivaon the next counter clock, counter reset or write command to the compare reg

Running – This signal indicates that the counter has been enabled to recogniclock inputs and may increment/decrement accordingly. Its state is affected bySTART and STOP inputs and theSTART/STOP bit in the command word.

Snap-Shot – This signal takes an instantaneous sample of the counter’s valueunfreezing the bus input latch, then immediately refreezing it. By insertion of jumper from a J2 connector pin,RESET OPTION, to one of its ground pins,counter reset will immediately follow the snap-shot of the counter value.

DIOB – (DISTRIBUTED INPUT/OUTPUT BUS) – This bus interfacesQ-Line I/O point cards to a multiplexing bus controller and permits a byte-oriendigital exchange of information between the bus controller and the point cards.data, address and control signals on the DIOB are twelve volt CMOS logic lesignals. The DIOB also supplies power to the Q-Line point cards.

3-30.3. Features

There are four QPA card groups available. The G01 through G04 QPA cards cotwo separate counter/comparators circuits. The pulse inputs (process or timeare fed into one of two counter/comparators. Each counter/comparator consist15-bit bidirectional counter, a start/stop bit, a snap-shot bit, and a comparator.counter’s value may be read at any time and the comparator’s output is availabthe bus as status. For the G01 through G03 cards, both counters may be reset tostarted or stopped, and snap-shot or released from snap-shot by a commandThe command may be sent to one specific card (jumper selected address) or tocards (jumper selected group address). Group addressing gives the system tability to perform a plant snap-shot. Groups are described below:

M0-0053 3-366 5/99Westinghouse Proprietary Class 2C

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3-30. QPA

ed,

itive

g

areon

puts

• G01 provides Phase A and Phase B inputs that are optically coupled,+48 VDCdifferential voltage inputs that employ on-card digital filtering(Figure3-188). The SNAP-SHOT, START, and STOP inputs are single-end48 VDC, optically coupled inputs with digital filters (identical to that ofPhase A and Phase B inputs). The common return line may be tied to a posor negative polarity (+48 VDC). SeeFigure 3-189.

• G02 provides Phase A and Phase B inputs that are optically coupled,+5 VDCdifferential inputs (with no filtering). The clock plus input should be tied to a+5VDC +5% voltage source and the clock minus input to the output of a+5 VDCline driver. The line driver must be capable of sinking 40 mA while maintaininan output voltage (VOL) of +0.5 VDC or less. SeeFigure 3-190 andFigure 3-191. The SNAP-SHOT, START and STOP inputs are+48 VDC, single-endedinputs as stated in G01. SeeFigure 3-189.

• G03 provides Phase A and Phase B inputs that are+5 VDC differential inputsas described in G02. The control inputs of SNAP-SHOT, START and STOP+5 VDC, single-ended, optically-coupled inputs without filtering. The commreturn line must be tied to+5 VDC +5% voltage source. SeeFigure 3-192.

• G04 provides Phase A and Phase B inputs that are identical to Group one in(Figure 3-188). The control signals and the J2 connector are absent.

5/99 3-367 M0-0053Westinghouse Proprietary Class 2C

Page 434: Ovation Q Line

3-30. QPA

Figure 3-188. QPA +48 VDC Clock Input Signal Wiring (G01, G04)

Eac

h cl

ock

sign

al s

houl

d be

tran

smitt

ed o

ver

a tw

iste

dco

nduc

tor

pair

as s

how

n. T

he c

able

con

tain

ing

the

twis

ted

pair

shou

ld o

nly

carr

y Q

PA fi

eld

sign

als.

An

oute

r sh

ield

sho

uld

surr

ound

all

the

cabl

e’s

twis

ted

pair

cond

ucto

rs.

PH

(-)

PH

(-) P

H(+

)

PH

(+)

Fie

ldC

onta

cts

Fie

ldC

onta

cts

Con

tact

Wet

ting

Volta

ge S

uppl

y

Clo

ck In

puts

PH

.A1(

+),P

H.A

1(-)

PH

.A0(

+),P

H.A

0(-)

PH

.B0(

+),P

H.B

0(-)

PH

.B1(

+),P

H.B

1(-)

Con

tact

Wet

ting

Volta

ge S

uppl

y

QPA

Gro

up O

neor

Fou

r

48V

DC

48V

DC

+

+-

-

Two

met

hods

of w

iring

the

cont

act w

ettin

g vo

ltage

sup

ply

to th

e fie

ld c

onta

cts

and

the

QPA

clo

ck in

puts

are

sho

wn.

M0-0053 3-368 5/99Westinghouse Proprietary Class 2C

Page 435: Ovation Q Line

3-30. QPA

Figure 3-189. QPA Control Signal ( +48 VDC) Input Wiring (G01, G02)

5/99 3-369 M0-0053Westinghouse Proprietary Class 2C

Page 436: Ovation Q Line

3-30. QPA

Figure 3-190. QPA +5 VDC Clock Input Signal Wiring (G02, G03)

+5V

DC

±5%

M0-0053 3-370 5/99Westinghouse Proprietary Class 2C

Page 437: Ovation Q Line

3-30. QPA

Figure 3-191. QPA Clock Signal Wiring (Differential Line Driver) G02 and G03

+5V

DC

±5%

QPA

-4

QPA

-4

5/99 3-371 M0-0053Westinghouse Proprietary Class 2C

Page 438: Ovation Q Line

3-30. QPA

Figure 3-192. QPA +5 VDC Control Input Wiring (G03)

QPA

GR

OU

PT

HR

EE J3 C

ON

NE

CTO

R

CO

NT

RO

L IN

PU

T

CO

MM

ON

SIN

GLE

EN

DE

D IN

PU

TS

WIR

ING

IS R

ES

TR

ICT

ED

TO

WIT

HIN

TH

E C

AB

INE

T IN

WH

ICH

TH

EQ

PA IS

LO

CAT

ED

.

TH

E O

PE

N C

OLL

EC

TOR

TR

AN

SIS

TOR

MAY

BE

RE

PLA

CE

D B

Y T

TL

OP

EN

CO

LLE

CTO

R G

ATE

S O

R S

TAN

DA

RD

TT

L G

ATE

S C

APA

BLE

OF

SIN

KIN

G 1

6 M

A O

R C

UR

RE

NT

QPA

CO

NT

RO

L IN

PU

TS

STA

RT

0, 1

STO

P 0

,1S

NA

PS

HO

T 0

,1

-+

5 V

OLT

S D

.C.

+5%

M0-0053 3-372 5/99Westinghouse Proprietary Class 2C

Page 439: Ovation Q Line

3-30. QPA

3-30.4. Specifications

A functional block diagram of the QPA card is shown inFigure3-193. The counter/comparator is shown inFigure 3-194 andFigure 3-195..

Figure 3-193. QPA Functional Block Diagram

J1Bus

Interface

Counter/Comparator#1

(CC1)

Counter/Comparator#0

(CC0)

Time Base

J2(G01,2,3)

25 pin“D” Connector

Field Signalsfrom TerminalBlock

1 MHz Osc.

Power On

5/99 3-373 M0-0053Westinghouse Proprietary Class 2C

Page 440: Ovation Q Line

3-30. QPA

Figure 3-194. QPA Card Counter/Comparator (1 of 2) (G01, 2, 3)

DIOB

DATA

1 UFLAG

8

RESET ON P.U.

DIRECTIONBIT (1=DOWN)

DATA

COMPARE

REGISTER

STATUS

READ

ANDMSB

P.U.

Q R

S

MSB

15

15

15

15 8MUX2:1

LATCH

UP/DOWNCOUNTER

BUSCOMMAND

P.U.

AND

BUS COMMANDOR P.U.

CO

UN

T

RE

SE

T

EN

AB

LE

“RUNNING”

BU

SC

OM

MA

ND

FR

EE

ZE

“FROZEN”

Q

R

(=)

OR

OR

X44:1

MUX

S

CLOCK SELECT

100 KHZ10 KHZ

+−+−

BUSCOMMAND

OR LOGICS

R

BUS COMMANDOR P.U.

Q

“FLAG”

UFLAG

FLAG

COMPARE

HIGH SPEED

TIME BASE

PHB

PHA

START

START

STOP

STOP

RESETOPTION

LEGEND

J3 CONNECTION

J2 CONNECTION

POWER UP

STATUS BIT

OPTICAL ISOLATION

P.U. =

=

=

SNAP-SHOT

SNAP-SHOT

SNAP-SHOT

OR

UNFREEZE LATCH, THEN FREEZE LATCH.RESET COUNTER IF RESET OPTION INPUTIS GROUNDED.

Internal Timebase

ExternalClocks

M0-0053 3-374 5/99Westinghouse Proprietary Class 2C

Page 441: Ovation Q Line

3-30. QPA

Figure 3-195. QPA Card Counter/Comparator (2 of 2) (G04)

DIOB

DATA8MUX

2:1

LATCH

DIRECTION BIT

MSB

15

UP/DOWNCOUNTER

“FROZEN”

S

R

Q

(DIRECTION)PHB +

PHA +CLOCK

(X1)

CE

BUS COMMAND

OR P.U.

BUS COMMAND

S

R

Q

BUS COMMAND

OR P.U.

BUS COMMAND

BUS COMMAND

OR P.U.

R

“RUNNING”

LEGEND

J3 CONNECTION

POWER UP

STATUS BIT

OPTICAL ISOLATION

P.U. =

=

=

EXTERNALCLOCKS

5/99 3-375 M0-0053Westinghouse Proprietary Class 2C

Page 442: Ovation Q Line

3-30. QPA

eethet

calge

cal

Internal Timebase Clocks and External Inputs’ Digital Filter Clock

Vin is measured directly across the QPA input pins for external clock inputs (sTable3-109). Vin is measured directly between the specified QPA input pin andcommon return pin for control inputs. Iin is the current measured at the QPA inpupin that flows into the input circuit.

QPA field input voltages equal to or less than the maximum OFF voltage willguarantee a logic zero to be transferred to the QPA logic circuitry via the optiisolator. QPA field input voltages equal to or greater than the minimum ON voltawill guarantee a logic one to be transferred to the QPA logic circuitry via the optiisolator.

Frequency

Internal Low Speed Time Base Clock 10 kHz+ 1%

Internal High Speed Time Base Clock 100 kHz+ 1%

Digital Filter Clock 1.953 kHz+ 2%

Table 3-109. QPA Field Signal (J3) Specifications

VDC mA(DC)

External Phase A& Phase B Vin OFF Vin ON Iin OFF Iin ON

Clock Inputs Max. Min. Nom. Max. Max. Min. Nom. Max

G01, 4 2.0 40 48 60 0.35 8.0 11.9 15.25

G02, 3 0.8 3.9 – 5.0 3.0 25.0 – 42.0

Control Inputs

G01, 2 2.0 40 48 60 0.35 8.5 11.7 16.6

G03 0.7 4.1 – 5.3 0.2 8.3 – 15.45

M0-0053 3-376 5/99Westinghouse Proprietary Class 2C

Page 443: Ovation Q Line

3-30. QPA

ldic

200

Iin OFF (MAX) is the maximum leakage current allowed to flow into a QPA fieinput (J3) that still ensures that a logic zero will be transferred to the QPA logcircuitry via the optical isolator (seeTable3-110). When Vin OFF(MAX) is appliedto a QPA field input, the resulting input current may exceed Iin OFF (MAX) but theinput current will still transfer a logic zero to the logic circuitry. IinOFF may be dueto driver/cable leakage or coupling capacitance between cables.

Power Supply Voltage (VDC)

3-30.5. Addressing and Field Pins

J2 Connector signals ( Figure 3-196)

• INPUTS: theTIME BASE,HIGH SPEED andRESETOPTION are select lineswhich may be tied to ground at the connector or left open (inactive). TheSTART, STOP andSNAP-SHOT inputs may be tied to a QPA output(COMPARE) or left open (inactive).SNAP-SHOT is available on two separatepins to aid in daisy chaining. SeeFigure 3-196 for pin locations of J2. TheUFLAG (pin #1) of the J2 connector is tied directly to the QPA card-DIOBpin 30 (UFLAG).

Table 3-110. Field Signal Times (J3)

External ClockInputs

msecMax. Count Rate

msec

OnTime(Min.)

OffTime(Min)

Digital Filter Delay

CLKX1 CLKX4 1 Min. Nom. Max.

G01, 4 2.5 2.5 200 kHz 800 kHz 1.7 2.0 2.36

G02, 3 0.005 0.005 100 kHz 400 kHz – None –

Control Inputs

G01, 2 2.5 2.5 – – 1.7 2.0 2.36

G03 0.1 0.1 – – – None –1 Assumes a two-phase (quadrature) input clock. The maximum clock frequencies are stillKHz for G01 and G04 or 100 KHz for G02 and G03.

Minimum Nominal Maximum

Primary Voltage: +12.4 +13.0 +13.1

Current: 100 mA (max), limited with a 0.5 Amp fuse

5/99 3-377 M0-0053Westinghouse Proprietary Class 2C

Page 444: Ovation Q Line

3-30. QPA

• OUTPUTS: TheCOMPARE output may be used to drive the QPA inputsdescribed in the above section.FLAG is an open collector output which may bewired into an interrupt subsystem or similar receiver. To clear theFLAG, astatus read should be part of an interrupt service routine. TheFLAG output mayalso be used to drive theUFLAG input if the DIOB Controller usesUFLAG.

Figure 3-196. QPA J2 Pin Connector (G01, 2 and 3) (Front View)

13

12

11

10

9

8

7

6

5

4

3

2

1

25

24

23

22

21

20

19

18

17

16

15

14

FLAG0

TIME-BASE0

HIGH-SPEED0

RESET-OPTION0

START0

STOP0

FLAG1

TIME-BASE1

HIGH-SPEED1

RESET-OPTION1

START1

STOP1

DIOB UFLAG

COMPARE0

GND

GND

GND

SNAP-SHOT0

SNAP-SHOT0

COMPARE1

GND

GND

GND

SNAP-SHOT1

SNAP-SHOT1

4260A10G02

Counter/Comparator 0

Counter/Comparator 1

M0-0053 3-378 5/99Westinghouse Proprietary Class 2C

Page 445: Ovation Q Line

3-30. QPA

als

er

J3 Connector Signals ( Figure 3-197)

• CONTROL INPUTS: THE SNAP-SHOT, STOP and START inputs may beeither the+48 volt wetted contacts (external supply required) type or the+5 voltTTL current sinking type. The selection is to be by group. Each of the six signwill be single wire sharing a common with the other five inputs (seeFigure 3-197).

• CLOCK INPUTS: Phase A and Phase B are both two wire inputs with eith+48 volt wetted contacts (external supply required) or+5 VDC line drivercompatible.

Figure 3-197. QPA J3 Pin Connector (G01, 2, 3, and 4) (Front View)

POINT 1

POINT 0

(GROUPS 1, 2, 3, ONLY)

(SLOT)

17B

15B

13B

11B

9B

7B

5B

3B

1B

17A

15A

11A

9A

7A

3A

1A

PHB1 (−)

PHA1 (−)

(OPEN)

STOP1

PHB0 (−)

PHA0 (−)

(OPEN)

STOP 0

CONTROL RETURN

PHB1 (+)

PHA1 (+)

SNAP-SHOT 1

START1

PHB0 (+)

PHA0 (+)

SNAP-SHOT 0

START 0

CONTROL RETURN

0

404A037H01 (CARD EDGE)A = CIRCUIT SIDEB = COMP. SIDE

5/99 3-379 M0-0053Westinghouse Proprietary Class 2C

Page 446: Ovation Q Line

3-30. QPA

B

QPA card connectors are shown inFigure3-198.Table3-111 shows the clock selectjumper connections (seeFigure 3-196).

Figure 3-198. QPA Card Connectors

Table 3-111. QPA Clock Select Jumper Connections

JumperCounter Clock

TIMEBASE HIGH SPEED

N N 1 count per external clock cycle*

N J 4 counts per external clock cycle**

J N 1 count per 100µs (internal 10kHz timebase)

J J 1 count per 10µs (internal 100kHz timebase)

J = Jumper Inserted; N = No Jumper*When the X1 external clock is selected, a one or two phase clock may be used. If Phaseis left open, the counter will only up-count.**If the X4 clock is selected, a two-phase clock must be used.

J1

J3

J2Power On

LED

M0-0053 3-380 5/99Westinghouse Proprietary Class 2C

Page 447: Ovation Q Line

3-30. QPA

ordr

BStatus

upper be

data

DIOB Addressing and Field Pins

A QPA card occupies four successive DIOB addresses (Figure 3-199). The lowestof the four DIOB addresses (XX) is occupied by the Counter/Comparator 0 wwhile the next higher DIOB address (XX+ 1) is occupied by Counter Comparato1 word. A DIOB write operation is performed to one of the two comparatorregisters, where a double type operation is required. The two upper QPA DIOaddresses (which address four data bytes) are used to address the QPA cardor Command byte (Figure 3-199).

Either of the upper or lower bytes of the QPA addresses (XX+ 2, XX + 3) may beread to obtain the QPA status byte. If double byte DIOB Read operations arerequired, the Status byte appears in the lower data byte and is repeated in thedata byte. If single byte data transfers are used, the card command byte maywritten into the upper or lower byte of the QPA addresses (XX+ 2, XX + 3). Whendouble byte data transfers are used, the Command byte must be in the lowerbyte and be repeated in the upper data byte. Refer toFigure 3-200 for QPA DataFormats,Figure 3-201 for Card Address Bit Positions andFigure 3-202 for CardAddress Selection.

Figure 3-199. QPA Card Address Format

COUNTER 0 WORD OR COMPARATOR 0 WORD

COUNTER1 WORD OR COMPARATOR1 WORD

COMMAND BYTE OR STATUS BYTECOMMAND BYTE OR STATUS BYTE

COMMAND BYTE OR STATUS BYTECOMMAND BYTE OR STATUS BYTE

LOW BYTEHIGH BYTEDIOB ADDRESS

XX16

(XX + 1)16

(XX + 2)16

(XX + 3)16

5/99 3-381 M0-0053Westinghouse Proprietary Class 2C

Page 448: Ovation Q Line

3-30. QPA

Figure 3-200. QPA Card Data Format

Input Datafrom QPA(Read

High Byte Low Byte

0 = Comparator DisarmedE= Enable Bit:1 = Comparator Armed

- B -

Output Datato QPA (SetComparator)

MSB LSB

15 Bit Comparator

X XX X

High Byte Low ByteMSB LSB Input Datafrom QPA(Read StatusByte(S))

- C -

E

High Byte Low Byte

D

Counter)

X XX X

High Byte Low ByteMSB LSB OutputData toQPA (WriteCommand

Counter Reset 1

Start/Stop 1

Freeze/Unfreeze 1

1

- D -

Counter Reset 0

Start/Stop 0

Freeze/Unfreeze 0

0

Byte(S))

X = Don’t Care

Counter Flag 1

Running 1

Frozen 1

1

Counter Flag 0

Running 0

Frozen 0

0

0 = Last Count Was UpD= Direction Bit:1 = Last Count Was Down

- A -

MSB LSB

15 Bit Counter Value

M0-0053 3-382 5/99Westinghouse Proprietary Class 2C

Page 449: Ovation Q Line

3-30. QPA

Figure 3-201. QPA Card Address Selection (Example)

UADD2-7 UADD1 UADD0 HI-LO

0 0 0

0 0 1

0 1 0

0 1 1

Read counter 0 low byte:Write comparator 0 low byte.OR

Read counter 0 high byte:Write comparator 0 high byte.OR

Read counter 1 low byte:Write comparator 1 low byte.OR

Read counter 1 high byte:Write comparator 1 high byte.OR

Read card status byte(s)Write command byte(s)OR

Write command byte

Read flags on bits determinedby CA2, CA3.

1 X X

S2 S1 S0

CA6 CA5 CA4

Card DIOBAddress*

(CA2-CA7)

SameData

Format**111111

***111111

(X) = Don’t care

* The card address bits are jumper selectable on the front connector, J3. See Figure 3-202. The PulseAccumulator Card Occupies Four Addresses In The DIOB.

**Address bits S0, S1, S2 are jumper selectable (see Figure 3-202). These bits determine the QPA’S group writebyte address.

*** Bits CA2 through CA6 are the card address bits described above (*). Bits CA5 and CA6 determine the QPA’sparticular DIOB group read address. The DIOB group read address contains two bytes of data which containthe status of eight QPA’s flags. CA4 determines which byte (upper or lower) a QPA’s flags are located in. BitsCA2 and CA3 determine the flag bit positions within that byte. (Individual QPA cards cannot be assignedDIOB addresses FC16 to FF16).

Group reads and writes are not available with Group 4 QPA’s.

5/99 3-383 M0-0053Westinghouse Proprietary Class 2C

Page 450: Ovation Q Line

3-30. QPA

eade

ssesQPAe

Bte).

QPA DIOB Group Read Bit Format

The upper half of the DIOB address range (80-FF) is mapped into 64 Group Rbits that occupy four DIOB addresses (FC-FF; no point card may occupy thesaddresses) (Figure 3-203). Each Group Read bit has two successive DIOBaddresses mapped into it. A QPA card occupies four successive DIOB addrewhich means that two successive DIOB Group Read bits are available to eachcard. The QPA card DIOB address determines which two Group Read bits arassigned to it.Figure 3-203 may be used to determine the bit positions of aparticular QPA card’s FLAGS within the eight bytes of Group Read data (DIOGroup Read Address, high or low byte and bit positions within the particular byExample: Bits 0 and 1 of the low bytes of DIOB address FF16 contain the status ofFLAGS 0 and 1 of QPA card that is occupying DIOB addresses E016 to E316.

Figure 3-202. QPA Card Address Selection (Example)

Select Card DIOB Address

FIxed

Jumper Inserted = Logic One

CA7 = 1

CA6 = 0

CA5 = 1

CA4 = 1

CA3 = 0

CA2 = 1

S2 = 1

S1 = 0

28B, A

27B, A

26B, A

25B, A

24B, A

23B, A

22B, A

21B, A

S0 = 120B, A

for example. 101101XX (B416-B716)

Select Group Write Byte Address111111 10 High Byte

Selected by S2, S1, S0

J3 Card Edge Connector

[FE16(High Byte)]

M0-0053 3-384 5/99Westinghouse Proprietary Class 2C

Page 451: Ovation Q Line

3-30. QPA

Figure 3-203. QPA Card Group Read Bit Format

OP

EN

OP

EN

FLA

G1

QPA

FLA

G0 #31

FLA

G1

QPA

FLA

G0 #3

0

FLA

G1

QPA

FLA

G0 #2

9

FLA

G1

QPA

FLA

G0 #2

8

FLA

G1

QPA

FLA

G0 #2

7

FLA

G1

QPA

FLA

G0 #2

6

FLA

G1

QPA

FLA

G0 #2

5

7(F

)6(

F)

5(D

)4(

C)

3(B

)2(

A)

1(9)

0(8)

76

54

32

10

DIO

BA

DD

RE

SS

FF

F8-

FB

F4-

F7

F0-

F3

EC

-EF

E8-

EB

E4-

E7

E0-

E3

LOW

BY

TE

HIG

H B

YT

E

FLA

G1

QPA

FLA

G0 #23

FLA

G1

QPA

FLA

G0 #2

2

FLA

G1

QPA

FLA

G0 #2

1

FLA

G1

QPA

FLA

G0 #2

0

FLA

G1

QPA

FLA

G0 #1

9

FLA

G1

QPA

FLA

G0 #1

8

FLA

G1

QPA

FLA

G0 #1

7

FE

D8-

DB

D4-

D7

D0-

D3

CC

-CF

C8-

CB

C4-

C7

C0-

C3

FLA

G1

QPA

FLA

G0 #2

4

DC

-DF

FLA

G1

QPA

FLA

G0 #15

FLA

G1

QPA

FLA

G0 #1

4

FLA

G1

QPA

FLA

G0 #1

3

FLA

G1

QPA

FLA

G0 #1

2

FLA

G1

QPA

FLA

G0 #1

1

FLA

G1

QPA

FLA

G0 #1

0

FLA

G1

QPA

FLA

G0 #9

FD

B8-

BB

B4-

B7

B0-

B3

AC

-AF

A8-

AB

A4-

A7

A0-

A3

FLA

G1

QPA

FLA

G0 #1

6

BC

-BF

FLA

G1

QPA

FLA

G0 #7

FLA

G1

QPA

FLA

G0 #6

FLA

G1

QPA

FLA

G0 #5

FLA

G1

QPA

FLA

G0 #4

FLA

G1

QPA

FLA

G0 #3

FLA

G1

QPA

FLA

G0 #2

FLA

G1

QPA

FLA

G0 #1

FC

98-9

B94

-97

90-9

38C

-8F

88-8

B84

-87

80-8

3

FLA

G1

QPA

FLA

G0 #8

9C-9

F

5/99 3-385 M0-0053Westinghouse Proprietary Class 2C

Page 452: Ovation Q Line

3-30. QPA

A

eld

ead

n then a

QPA Applications

By using the control signals on the J2 and J3 connectors, several derived QPfunctions are possible.

The most straight forward use of the QPA card is pulse accumulation. With the fiinput wired to PHASE A (PHA+) and PHASE A (PHA−) (and PHASE B andPHASE B if necessary) and the control pins left open, the bus controller may rthe counter value at any time. Devices included in this category are positionencoders (where rotation in one direction increments the counter and rotation iopposite direction decrements the counter). This allows the counter to contaivalue that is proportional to rotary position.

Shown in the following figures (Figure3-204 throughFigure3-207) are four circuitconfigurations utilizing the QPA card.

M0-0053 3-386 5/99Westinghouse Proprietary Class 2C

Page 453: Ovation Q Line

3-30. QPA

Figure 3-204. QPA Card Used for Speed Measurement

J2 C

onne

ctio

n

J3 C

onne

ctio

n

5/99 3-387 M0-0053Westinghouse Proprietary Class 2C

Page 454: Ovation Q Line

3-30. QPA

Figure 3-205. QPA Card Used for Elapsed Time Measurement

STA

RT

STO

P

RT

N

HIG

H S

PE

ED

TIM

E B

AS

E

CO

UN

TE

R/C

OM

PAR

ATO

R 0

LIM

IT S

WIT

CH

ES A B 48

V+

E.G

.S

ELE

CT

100

KH

ZC

LOC

K

RE

AD

VA

LUE

(WH

EN

STO

PP

ED

)

SN

AP

-SH

OT

RT

N

RE

SE

T O

PT

ION

HIG

H S

PE

ED

CO

UN

TE

R/C

OM

PAR

ATO

R 1

48V

+

E.G

.S

ELE

CT

10 K

HZ

CLO

CK

RE

AD

VA

LUE

(AT

AN

Y T

IME

)

TIM

E B

AS

E

OR

J2 C

onne

ctio

n

J3 C

onne

ctio

n

M0-0053 3-388 5/99Westinghouse Proprietary Class 2C

Page 455: Ovation Q Line

3-30. QPA

Figure 3-206. QPA Used for Speed Ratio Measurement (For example, estimatestretch of materials between two rollers

J2 C

onne

ctio

n

J3 C

onne

ctio

n

5/99 3-389 M0-0053Westinghouse Proprietary Class 2C

Page 456: Ovation Q Line

3-30. QPA

put.ct

3-30.6. Implementation Example

In the following example, a QPA card is set up as a counter for one pulsed inThe parameter being counted in this case is a POWER VALUE (MWH): contaclosures from a megawatt meter. The number of megawatts per pulse will beaccounted for in the coefficients that have to be calculated.

Figure 3-207. QPA Used for Average Inverse Speed Measurement

J2 C

onne

ctio

n

J3 C

onne

ctio

n

M0-0053 3-390 5/99Westinghouse Proprietary Class 2C

Page 457: Ovation Q Line

3-30. QPA

1)ses forre aretatusoint

ple

AR

beint

e a

untget

,

,

The QPA card is located in the first slot of crate 1 in a DPU (zone/halfshell = Aand its address is 80H. Care should be taken when selecting hardware addresQPA cards, since they require 4 consecutive addresses each, even though theonly 2 inputs per card. (The remaining two addresses are used for control and sword transfer). In this example, EW1 is point 1 on the card. This is the second pon the card. The first point is point 0.

The QPA point must be initialized as an analog input point in the DPU. An examfollows:

INIT/EW1, AI, 1.0, IV = 0, FM = 0, DG = 2500, TB = 0, BB = 0, ED = ‘MWH TO PHOS1E − ACB NO1 ‘, EU = ‘MWH ‘, EV = 0.0, CD = 36, HW = 258, AP = 0, LC = 0,HL = 0.0, LL = 0.0, IL = 0.0, DB = 0.0, HS = 0.0, LS = 0.0, CV = 1, CJ = 0, CI = 2

CHARST/EW1 , ‘A ‘ (OPTIONAL)

INIT/HOURS, DM, 1.0INIT/PMIN, DM, 1.0INIT/SECND, DM, 1.0INIT, EWIR, AM, 1.0INIT/EW1TOT, AM, 1.0

This point may have non-zero values for parameters such as TOPBAR, BOTBand LIMITS as desired, just as any other analog process input point.

As an example, if 1 pulse from a KWH meter is equal to 10 KW, and EW1 is toequivalent to MEGAWATTS PER HOUR; the conversion coefficients for this powould be:

COEF/LT. 2 = (0.600, 0.00)

This means, if 3 pulses came in a one minute period, the coefficient would givvalue of 3 * 10 KW * 0.60+ 0.00 = 1.80 MWH.

If the CI and CV fields are left blank, the value of EW1 will be the actual pulse cofrom the QPA card. A gain can then be used in the RESETSUM algorithm to MW per hour.

The algorithms required to control the QPA card are as follows:

TIMECHG/110, HCHG = HOURS, MCHG = PMIN, SCHG = SECND

QPACMD/111, CNTR = EW1, GADR = 0, FRZ0 = 0, STRO = 0, RST0 = 0, FRZ1 = 0STR1 = 1, RST1 = 0, RUN = DX1PASS

QPACMD/112, CNTR = EW1, GADR = 0, FRZ0 = 0, STRO = 0, RST0 = 0, FRZ1 = 2STR1 = 0, RST1 = 0, RUN = PMIN

5/99 3-391 M0-0053Westinghouse Proprietary Class 2C

Page 458: Ovation Q Line

3-30. QPA

,

,

iny the

enardPUt is,

PAalueOnly

ationOB.eagn

ding

Theted by.

d in

the

QPACMD/113, CNTR = EW1, GADR = 0, FRZ0 = 0, STRO = 0, RST0 = 0, FRZ1 = 1STR1 = 0, RST1 = 1, RUN = PMIN

AIN/114, AREC = EW1

RESETSUM/115, IN1 = EW1, FFLG = HOURS(F), RSET = HOURS(F), RUN = PMINRCNT = 0.0, GAIN = 1.0, OUT = EW1R, FOUT = EW1TOT

Algorithm 110 (TIMECHG) generates PMIN, which is a flag denoting a changeminutes, and HOURS, which is a flag denoting a change in hours, to be used bQPACMD and RESETSUM algorithms. HOURS, PMIN and SECND must beinitialized as digital points (for example, DM record type).

Algorithm 111 sends a control command of START to channel 1 of the QPA whthe digital input DX1PASS is set. DX1PASS is a point generated by the standsystem in every DPU which is set to 1 only during the first pass through the Dcontrol program. These algorithms, therefore, start the QPA data collection (thacount upon DPU startup).

The two algorithm pairs (112 and 113) provide for the reading of data from the Qchannel 1. This is accomplished by first freezing the counter to get the new vfrom the QPA, and resetting the counter once that reading has been obtained.the reset operation will affect the actual QPA count; the freeze/unfreeze operonly causes the current value to be placed on the DIOB or removed from the DIThese 4 algorithms will only run when the digital flag PMIN is true. PMIN may bgenerated any number of ways, but in this system, PMIN is set as an output flfrom the algorithm TIMECHG every minute. By unfreezing the QPA value only othe next 1-minute pass after freezing, rather than immediately, a valid QPA reais present on the DIOB during the entire 1-minute period.

AIN (algorithm 114) is used to convert the value EW1 to engineering units asrequired by RESETSUM.

RESETSUM (algorithm 115) is used to totalize the value read from the QPA. values are summed based on the state the out flags PMIN and HOURS generaTIMECHG. In this example the output EW1R is an hours accumulation of MWOutput EW1TOT which is triggered by HOURS will be an hourly total.

A description of each individual algorithm and required parameters can be foun“Control Algorithms” (U0-0106).

The command words as described here may be field-wired if the availability ofQPA count is to be controlled by hardware rather than software.

M0-0053 3-392 5/99Westinghouse Proprietary Class 2C

Page 459: Ovation Q Line

3-30. QPA

s all

3-30.7. Installation Data Sheet

1 of 5

Installation Note:

Group 4 consists of counters only and no control signals. Group 1 containsignals and circuits shown.

Figure 3-208. QPA Wiring Diagram, Groups 1 and 4

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

3/4 A18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

TERMINAL BLOCK HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTOR CUSTOMER CONNECTIONS INTERNALBUS STRIP

BLACK RED

(+)RETURN

TP BUS

PHB

PHA

SNAP-SHOT

START

STOP

PHB

PHA

SNAP-SHOT

START

STOP

48 VOLT POWER

SNAP-SHOT

START

STOP

PHB

START

STOP

PHA

(+)

(−)

(+)

(−)

SNAP-SHOT

PHB

PHA

(+)

(−)

(+)

(−)

CLOCK1

CLOCK0

CO

UN

TE

R 1

CO

UN

TE

R 2

*

*

*

*

*

*

5/99 3-393 M0-0053Westinghouse Proprietary Class 2C

Page 460: Ovation Q Line

3-30. QPA

hen

Installation Data Sheet

2 of 5

Installation Notes:

Group 3 uses customer supplied 5V power. This cards TP Bus will be live wcustomer 5V is on.

* Group 2 utilizes standard 48V supply.

Figure 3-209. QPA Wiring Diagram, Groups 2 and 3

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

Card

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

Terminal Block Half Shell Extension(B-Block)

Edge-connector Customer Connections

InternalBus Strip

BLack Red

(+)Return

* TP BUS

48 Volt Power

Snap-shot

Start

Stop

PHB

Start

Stop

PHA

(+)

(−)

(+)

(−)

SNAP-SHOT

PHB

PHA

(+)

(−)

(+)

(−)

Clock1

Clock0

Cou

nter

1C

ount

er 2

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

*

PHB

PHA

(+)

(−)

(+)

(−)

PHB

PHA

(+)

(−)

(+)

(−)

(+) (−)

Customer5V POWER

*

(Group 2) (Group 3)

M0-0053 3-394 5/99Westinghouse Proprietary Class 2C

Page 461: Ovation Q Line

3-30. QPA

ory.the B at

For CE MARK Certified System

3 of 5

Installation Notes:

1. All field wiring must use shielded cables. Individually-shielded cables are not mandatA single overall shield is acceptable. The shield may be connected to earth ground atcabinet or in the field.Figure 3-210 shows two shielded cables with shields connectedthe B cabinet.

2. The control signals are absent from the Group 4 QPA.

Figure 3-210. QPA CE MARK Wiring Diagram (Groups 1 and 4)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

20

PE

20

PE

19

20

19

20

-

+48 VDC

PHB 1

PHA 1

SNAP

START 1

STOP 1

PHB 0

PHA 0

SNAP

START 0

STOP 0

CUSTOMER CONNECTIONS

SHOT 1

SHOT 0

18 .75A

5/99 3-395 M0-0053Westinghouse Proprietary Class 2C

Page 462: Ovation Q Line

3-30. QPA

ory.the Beld.

high

For CE MARK Certified System

4 of 5

Installation Notes:

1. All field wiring must use shielded cables. Individually-shielded cables are not mandatA single overall shield is acceptable. The shield may be connected to earth ground atcabinet or in the field.Figure3-211 shows the shields connected to earth ground in the fi

2. Twisted-pair wiring is recommended for the clock inputs (PHA and PHB) due to the frequencies.

Figure 3-211. QPA CE MARK Wiring Diagram (Group 2)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

20

PE

20

PE

19

20

19

20

-

+48 VDC

SNAP

START 1

STOP 1

SNAP

START 0

STOP 0

CUSTOMER CONNECTIONS

SHOT 1

SHOT 0

18 .75A

-

+PHB 1

-

+PHA 1

-

+PHB 0

PLANT EARTHGROUND

PLANT EARTHGROUND

-

+PHA 0

M0-0053 3-396 5/99Westinghouse Proprietary Class 2C

Page 463: Ovation Q Line

3-30. QPA

earthh

the

For CE MARK Certified System

5 of 5

Installation Notes:

1. All field wiring must use shielded cables. Individually-shielded cables are notmandatory. A single overall shield is acceptable. The shield may be connected toground at the B cabinet or in the field.Figure3-212 shows all shields connected to eartground at the B cabinet.

2. Twisted-pair wiring is recommended for the clock inputs (PHA and PHB) due to high frequencies.

Figure 3-212. QPA CE MARK Wiring Diagram (Group 3)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

19

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

19

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

A

20

PE

20

PE

19

20

19

20

-

+5 VDC

SNAP

START 1

STOP 1

SNAP

START 0

STOP 0

CUSTOMER CONNECTIONS

SHOT 1

SHOT 0

18 .75A

-

+PHB 1

-

+PHA 1

-

+PHB 0

-

+PHA 0

5/99 3-397 M0-0053Westinghouse Proprietary Class 2C

Page 464: Ovation Q Line

3-31. QRC

d the

3-31. QRC

Remote Q-Line Controller(Style 4256A26G01)

3-31.1. Description

Applicable for use in the CE MARK Certified System

The QRC (Remote Q-Line Controller) printed circuit board serves as a DIOBcontroller in the WDPF Remote Q-Line I/O subsystem. Located in the remotestations, the QRC handles the communications between the remote station anMRC (which is housed in the master station (DPU)). Full details on theconfiguration and use of the QRC are contained in the“RemoteQ-LineInstallationManual” (M0-0054).

M0-0053 3-398 5/99Westinghouse Proprietary Class 2C

Page 465: Ovation Q Line

3-32. QRF

an

nce

el),nel,er

te forhed to

in

3-32. QRF

Four-Wire RTD Input Amplifier(Style 3A99109G01)

3-32.1. Description

Applicable for use in the CE MARK Certified System

The QRF card provides an addition to the family of Q-line I/O cards. It providesintegrated solution to measure temperature, using four-wire ResistanceTemperature Detectors (RTD's) (seeFigure 3-213).

Six isolated analog input channels are provided along with six isolated referecurrent sources to accommodate six four-wire RTD's. To provide electrical(transformer) isolation for the analog input channels, individual (one per channon-card power supplies are used. In addition to providing power to each chanprecise timing is also transmitted by using a stable frequency to drive the powsupplies.

The input analog signals on each channel are converted to digital data andtransferred to the on-board microcontroller. The data is processed to compensaoffset and gain errors, to provide filtering for 50/60 Hz. noise, and to convert tresult to a percent of the full scale input voltage. The resulting data is formatteconform to the data package used on the QAV, QAW, QAX, and QRT cards.

The formatted data is read via the Distributed Input/ Output Bus (DIOB).

Periodic calibration is performed by the microcontroller to obtain offset and gaerrors from each input channel.

As part of the calibration, reasonability checks are performed on the errors tomonitor the integrity of the hardware.

5/99 3-399 M0-0053Westinghouse Proprietary Class 2C

Page 466: Ovation Q Line

3-32. QRF

Figure 3-213. QRF Block Diagram

AddressDecoder

µController,Counter and

Control Circuits

TransformerIsolation

TransformerIsolation

(+) (-) S

...

...

Six Sets of 4-wire RTD Analog Field Inputs

OURCE

RETURN

SHIELD

Channel 1Voltage toFrequencyConverter

(+) (-) SOURCE

RETURN

SHIELD

Channel 6Voltage toFrequencyConverter

DIOBData Address Control

DataBufferRAM

M0-0053 3-400 5/99Westinghouse Proprietary Class 2C

Page 467: Ovation Q Line

3-32. QRF

TB.

try

3-32.2. Features

The QRF card provides the following features:

• IEEE Surge Withstand Capability

• Auto Offset Auto Gain corrections

• Electrical Isolation (all channels)

• On-Card Digital Memory (buffer)

• 50 or 60 Hz time-base using a QTB card or internal time-base without a Q

• Auto Conversion Check

• Both Normal and Common-Mode Rejection are provided

• Low power consumption is achieved by the extensive use of CMOS circuiand the use of a switching regulator to generate the +5V (Vcc).

• Reasonability test.

• RTD operational range monitoring.

• Open Input and Current Loop Detection

Four groups provided as follows:

Note

The groups are determined by the group ofthe Plug-on QRD Module (3A99114).

Group Temperature RangePlug-on QRD

Module

G01 0oC to 370oC using a 200 ohm Platinum RTD at 0oC 3A99114G01

G02 180oC to 230oC using a 100 ohm Platinum RTD at 0oC 3A99114G02

G03 268oC to 342oC using a 200 ohm Platinum RTD at 0oC 3A99114G03

G04 0oC to 290oC using a 100 ohm Platinum RTD at 0oC 3A99114G04

5/99 3-401 M0-0053Westinghouse Proprietary Class 2C

Page 468: Ovation Q Line

3-32. QRF

.up to

3-32.3. Specifications

Ratings

• Number of Analog Inputs: 6

• Point Sampling Rate (Rate/Second): 10, 5 during auto calibration

• Resolution: 12 bits

• Input Impedance: 107 Ohm6000 Ohms in Overload or power-down

• Input Channel Sample Period (four cycles of the power line frequency):0.066 sec. for 60 Hz.0.080 sec. for50 Hz.

• Current: 0.8 A typical, 1.0 A maximum

Power Supply

Input Signal Temperature Ranges

Normal Mode Voltage

The IEEE surge may be applied without permanent damage to the QRF cardReduced accuracy is to be expected if reading are taken during the surge and10 seconds following the surge, or until the next calibration.

Minimum Nominal Maximum

Primary Voltage 12.4 VDC + 13.0 VDC 13.1 VDC

Optional Backup 12.4 VDC -- 13.1 VDC

Group Temperature Range Platinum RTD’s Value Excitation Current Vspan*

G01 0oC to 370oC 200 ohm at 0oC 1mA+5% 273.3mV

G02 180oC to 230oC 100 ohm at 0oC 2mA+5% 36.72mV

G03 268oC to 342oC 200 ohm at 0oC 1mA+5% 54.04mV

G04 0oC to 290oC 100 ohm at 0oC 2mA+5% 216.92mV

* The actual Vspan values are the function of the excitation current.

M0-0053 3-402 5/99Westinghouse Proprietary Class 2C

Page 469: Ovation Q Line

3-32. QRF

outnge

.up to

dlue01;

outnge

g

s notmV

A continuous over-range input up to 10 VAC or 10 VDC can be sustained withdamaging the QRF card. However, readings taken following sustained over-racan be affected for several seconds.

Common Mode Voltage

The IEEE surge may be applied without permanent damage to the QRF cardReduced accuracy is to be expected if readings are taken during the surge and10 seconds following the surge, or until the next calibration.

A continuous maximum of+ 500 VDC or peak AC with respect to system grounis allowable. The common mode reject ratio is not applicable if the AC peak vaexceeds 200,000 percent of the full-scale input scan (20 VAC maximum for G67 VAC maximum for G02).

A continuous over-range input up to 10 VAC or 10 VDC can be sustained withdamaging the QRF card. However, readings taken following sustained over-racan be affected for several seconds.

Normal Mode Rejection

• 60 dB at exactly 50 and 60 Hz (and harmonics) with line frequency trackin

• 30 dB at 50 and 60 Hz+ 5% without line frequency tracking

For specified accuracy and normal mode rejection, the input peak-to-peak AC ito exceed 50% of the input span (136.65 mV for G01, 18.36 mV for G02, 27.02for G03 and 108.46mV for G04).

Common Mode Rejection

• 120 dB at DC and the power line frequency and its harmonics with linefrequency tracking

• 100 dB (typical) for nominal line frequency+5% and harmonics without linefrequency tracking

Note

Common mode rejection is not applicable ifpeak value of AC exceeds 200,000% of theinput span

5/99 3-403 M0-0053Westinghouse Proprietary Class 2C

Page 470: Ovation Q Line

3-32. QRF

ge

ion isata is

of

Temperatures Stability

For accuracy specifications to apply, the QRT card’s temperature rate of chanmust not exceed+ 10°C per hour.

Other Applicable Specifications

Once every 80 conversions (8 seconds apart) auto gain and auto offset calibratperformed. Calibration and input conversion cycles are alternated, thus the dnever more than 0.2 second old.

Reference Accuracy - Analog Inputs:

+0.20% of span+10 uV+1/2 LSB @ 99.7 confidence.

Reference Conditions:

25oC +1oC Ambient Temperature50%+1% RH.0 V Common Mode0 V Normal Mode (ac)

Temperature Coefficient:

Maximum variation of reading is + 0.25% of span, over the temperature range0oC to 60oC.

Note

The temperature characteristics of theinstrument are determined mainly by thecharacteristics of the reference resistors.

Long Term Stability:

0.02%

M0-0053 3-404 5/99Westinghouse Proprietary Class 2C

Page 471: Ovation Q Line

3-32. QRF

yonnly

edge).-7),

) aresses

n)uit to).

The

nge,

with

Operating and storage temperature:

Operating: From 0oC through +60oC as measured approximately 1/2 inch from anpoint on the printed circuit card while it is mounted in its normal vertical positiand while subject to the air movements which result from natural convection o(that is, no forced air movement).

Storage: From 0oC through +70oC.

Humidity:

From 10 to 90% relative humidity through an ambient temperature range of 0oCthrough 60oC, but with maximum wet bulb temperature not over 35oC (95oF).

3-32.4. Card Addressing

The card address is programmed by five jumpers on the top of the front card-connector. Insertion of a jumper encodes a “1” on each address line (Add 3-7When the pattern of the jumpers matches the bit pattern of the DIOB (UADD 3the card is selected.

Since there are only six analog channels on the card, two addresses (4 bytesused to obtain diagnostic data from the QRF card. As an option, the two addreare disabled on the QRF and can be used by other cards.

Bit patterns on UADD 0-2 determine which of the eight (or six using the optiochannels on the card is selected. In order to keep the address recognition circa minimum size, card addresses will be programmed in groups of 8 (16 bytes

Since the all-zero card address is excluded, 8 addresses (16 bytes) are lost. “DIOB” can address 31 cards (186 channels).

To provide address protection during card-pull and still retain the full address raan unused “finger” (20B) is shortened on the card. An “address” jumpermust be inthis position on the I/O connector.

Half of the address range is usable when the QRF is mixed on the same DIOBother cards that use the short “MSB” finger.

5/99 3-405 M0-0053Westinghouse Proprietary Class 2C

Page 472: Ovation Q Line

3-32. QRF

card

The QRF will use the feature where the DEV-BUSY line is pulsed (-whenaddressed-) to detect card presence. The DIOB cycle is extended during a validaddress.

A - Solder SideB - Component Side

A - Solder SideB - Component Side

Table 3-112. QRF DIOB Address Selection

ADDRESS LINE ADDRESS PIN GROUND PIN

A7A6A5A4A3

28B27B26B25B24B

28A27A26A25A24A

Address Protect 20A 20B

Table 3-113. Field Signal Pins

Input Excitation Current

(+) (-) Shield Source Return Shield

Point 1 1A 2A 3A 1B 2B 3B

Point 2 5A 6A 7A 5B 6B 7B

Point 3 9A 10A 11A 9B 10B 11B

Point 4 13A 14A 15A 13B 14B 15B

Point 5 17A 18A 19A 17B 18B 19B

Point 6 21A 22A 23A 21B 22B 23B

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3-32. QRF

ing

ard as

nectg of

lt)

3-32.5. Controls and Indicators

User configurable QRF card jumpers are shown inFigure 3-214.

Jumpers

JS1 (Three Pos.) - used for other RAM sizes - not installed.

JS2 (Three Pos.) - used to set the 50/60 hz operation according to the followtable:

JS3 (Three Pos.) - used to select the number of addresses used by the QRF cfollows:

JS4 - JS9 (Three Pos.) - only the first position (on each channel) is used to conthe shields for all six channels. This is an option used to facilitate the groundinthe shields on some Jobs.

Figure 3-214. QRF Card Jumpers

JS2 (1-2) JS2 (3-4) Function

OFF OFF 60 HZ operation, No QTB (internal time-base)

OFF ON 50 HZ operation, No QTB (internal time-base) (Defau

ON OFF 60 HZ operation, With QTB

ON ON 60 HZ operation, With QTB

JS3 (1-2) JS3 (3-4) Function

ON OFF All eight addresses are used by the QRF. (Default)

OFF ON The first six addresses are used by the QRF.

Jumper JS3

Jumper JS2

5/99 3-407 M0-0053Westinghouse Proprietary Class 2C

Page 474: Ovation Q Line

3-32. QRF

LEDs

LE1: POK - module receiving power from backplane

3-32.6. Installation Data Sheet

1 of 2

Figure 3-215. QRF Wiring Diagram

2BReturn

171618141315111012879546213

171618141315111012879546213

23B22B

23A22A21A19B18B17B19A18A17A15B14B13B15A14A13A

24A24B

21B

11B10B

11A10A

9A7B6B5B7A6A5A3B

1B3A2A1A

9B

shReturnSource

sh-+

shReturnSource

sh-+

shReturnSource

sh-+

shReturnSource

sh-+

shReturnSource

sh-+

sh

Sourcesh

-+

Point 3

Point 2

Point 1

Point 6

Point 5

Point 4

“B”Block

Halfshell

“A”Block

Halfshell

M0-0053 3-408 5/99Westinghouse Proprietary Class 2C

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3-32. QRF

For CE MARK Certified System

2 of 2

Figure 3-216. QRF CE MARK Wiring Diagram

POINT 1

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(Source)

(Return)

(+)

(-)

1

3A

1A

2B

3B

1B

6A

7A

5A

6B

7B

5B

10A

11A

9A

10B

11B

9B

2A

15A

13A

14B

15B

13B

18A

19A

17A

18B

19B

17B

22A

23A

21A

22B

23B

21B

14A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

2

POINT 2

(Source)

(Return)

(+)

(-)

POINT 3

(Source)

(Return)

(+)

(-)

POINT 4

(Source)

(Return)

(+)

(-)

POINT 5

(Source)

(Return)

(+)

(-)

POINT 6

(Source)

(Return)

(+)

(-)

NOTE: MOVs (Westinghouse Part # 4258A79H06) must beconnected from the cable shields to earth ground at the B cabinet.

5/99 3-409 M0-0053Westinghouse Proprietary Class 2C

Page 476: Ovation Q Line

3-33. QRO

der

oryrcuit

3-33. QRO

Relay Output(Style 2840A18G01 through G04)

3-33.1. Description

The QRO Card provides a method of interfacing DIOB controllers with fieldprocess points that require relay switching within the plant environment (seeFigure 3-217). This card consists of eight mercury-wetted relays energized unDIOB control, providing normally-open or normally-closed relay contactoperations to field processes. An on-card read/write latch provides an 8-bit memfunction. This card also contains a switch-selectable dead-computer time-out cito reset the card when not periodically updated by the controller.

Figure 3-217. QRO Block Diagram

DIOBData Address

DataLatch

BusDrivers

AddressDecoder

On-CardRelays

Card-EdgeLED

Indicators

Field ProcessRelay Contact

Outputs

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3-33. QRO

s

s

or

IOBgizesions. read/

etste

3-33.2. Features

The QRO card groups provides the following features:

• G01 provides eight contacts (SPST) which may drive resistive or inductiveloads. All G01 contacts are factory shipped as Form A (normally open).

• G02 provides eight contacts (SPST) which may drive resistive or inductiveloads. All G02 contacts are factory shipped as Form B (normally closed).

• G03 provides eight contacts (SPST) which are limited to resistive loads.(Inductive loads cannot be driven). All G03 contacts are factory shipped aForm A (normally open).

• G04 provides eight contacts (SPST) which are limited to resistive loads.(Inductive loads cannot be driven). All G04 contacts are factory shipped aForm B (normally closed).

Features common to all cards include:

• Contacts may be individually jumper selected to be Form A (normally open)Form B (normally closed).

• IEEE surge-withstand protection

• 330 VDC common mode rating

• On-card power-up, bus, and dead-computer time-out resets

• Switch-selectable time-out periods

• Read/write output data operation

• Card-edge LED indicator for each relay‘s state

• Compatible with any DIOB controller

During a write operation, the QRO card receives and latches data from the Dinto an on-card read/write register. This latched write data energizes or de-enerthe appropriate relays via transistor relay drivers, depending on user applicatDuring a read operation, the state of each of the eight relays is read from thewrite register and driven to the DIOB, for use by the system controller.

The read/write register may be reset by the DIOB controller, or by on-card resfrom the power-up and time-out circuits. Additionally, card-edge LED’s indicathe state of each relay, where “ON” is energized and “OFF” is de-energized.

The card should not be mounted more than 30 degrees from vertical.

5/99 3-411 M0-0053Westinghouse Proprietary Class 2C

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3-33. QRO

3-33.3. Specifications

A functional block diagram of the QRO is shown inFigure 3-218.

Output Capabilities

Figure 3-218. QRO Functional Block Diagram

Voltage: 330 VDC (maximum) 250 VAC (maximum) RMS at linefrequency

Current: 0.5 Adc at peak AC (maximum)

Power: 100 VA (maximum) DC at peak AC

Address Data

PowerUp

CardTime Out

Compare

FrontLatchReset

Or

9

Unit

8-bit

RelayCoils

DRIVERS

LED’s

~

DIOB

Latch

~

8 Identical Relays

ConnectorJumpers

9

On-Card Jumper

*0.1µF AT 60 Hz = 26 KΩ Impedance0.1µF AT 50 Hz = 31 KΩ Impedance

.1µF68Ω.5wN.O.

N.C.

8

8

MOV

MOV

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3-33. QRO

ated

Power Supply

Electrical Environment

IEEE Surge withstand capability (G01 and G02 only)

Common Mode Voltage: 330 VDC

250 VAC (rms)

Speed: 2ms typical (operate)10ms typical (release)

Contact Closed – 6Ω (maximum)

Impedance: Open (G01, G02) – 25 kΩ (minimum)Open (G03, G04) – 300 kΩ (minimum)

Duty Cycle: The contact should not open more than once every 10 ms (at rvoltage)

Primary: +13V + 0.1 VDC

Backup: +12.6V+ 0.2 VDC

Current: 400 mA (maximum) supplied by DIOB

5/99 3-413 M0-0053Westinghouse Proprietary Class 2C

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3-33. QRO

y be

Safe Operating Area

Figure 3-219 shows graphs for both DC and AC operation. These graphs mareferenced for safe operation specifications.

Figure 3-219. QRO Safe Operating Area Diagrams

.1

.2

.3

.4

.5

ClosedCircuitCurrent(Amps)

100 VA

DCSafe

OperatingArea

100 200 300

.1

.2

.3ClosedCircuitCurrent

(Amps RMS)

100 VA

ACSafe

OperatingArea

100 200 300250

Open Circuit Voltage (VAC RMS)

Open Circuit Voltage (VDC)

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3-33. QRO

edge

3-33.4. Card Addressing

The QRO card address is established by eight jumpers on the top, front, card-connector. The insertion of a jumper encodes a “1” on the address line(Figure 3-220).

Figure 3-220. QRO Card Address Jumper Assembly

A7 = 1

A6 = 1

A5 = 0

A4 = 0

A3 = 1

A2 = 0

A1 = 0

A0 = 0

Jumper:

Jumper:

Blank:

Blank:

Jumper:

Blank:

Blank:

Blank:

Card-edge Connector(Front View)

Address Selection Example

HI-LO = 1 (i.e., High byte)Jumper:

Card Address = 1100 1000(C8 High Byte)

5/99 3-415 M0-0053Westinghouse Proprietary Class 2C

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3-33. QRO

is set

the

orallylly

3-33.5. Controls and Indicators

The location of the QRO LEDs and DIP switches are shown inFigure 3-221.

If the QRO card is not periodically updated, the card resets. The update periodby four DIP switches as given inTable 3-114.

Separate LED’s for each output are located at the front of the card to indicatestatus of each output.

Eight jumpers are provided to select the form of each contact (normally opennormally closed). G01 and G03 are factory shipped with all jumpers in the normopen position. G02 and G04 are factory shipped with all jumpers in the normaclosed position.

Figure 3-221. QRO Card Components

DIP

LEDs

Switches

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3-33. QRO

3-33.6. Installation

The relay outputs are brought out on the front edge of the card. The contactallocations are listed inTable 3-115.

Table 3-114. QRO Card Reset Switch Position

Dip SwitchReset Time

A B C D

0 0 0 0 62 ms+ 20%

0 0 1 0 125 ms+ 20%

0 1 0 0 250 ms+ 20%

0 1 1 0 500 ms+ 20%

1 0 0 0 1 sec+ 20%

1 0 1 0 2 sec+ 20%

1 1 0 0 4 sec+ 20%

1 1 1 0 8 sec+ 20%

X X X 1 No time out, data latched (X = 0 or 1)

Table 3-115. QRO Digital Output Contact Allocations

Output Digital Bit No. PC Card Edge Pin No.Field Terminal Block Terminal

No.

B7 17B 17

17A 16

B6 15B 15

15A 14

B5 13B 13

13A 12

B4 11B 11

11A 10

B3 9B 9

9A 8

B2 7B 7

7A 6

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Page 484: Ovation Q Line

3-33. QRO

B1 5B 5

5A 4

B0 3B 3

3A 2

Table 3-115. QRO Digital Output Contact Allocations (Cont’d)

Output Digital Bit No. PC Card Edge Pin No.Field Terminal Block Terminal

No.

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Page 485: Ovation Q Line

3-33. QRO

3-33.7. Installation Data Sheet

1 of 1

Figure 3-222. QRO Wiring Diagram

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CARD

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TERMINAL BLOCKSCREW

EDGE-CONNECTOR CUSTOMER CONNECTIONS

20B

20A

TYPICAL

G01 G02

250 V

250 V

COMMON

HI/LO JUMPER

5A

20

19

5/99 3-419 M0-0053Westinghouse Proprietary Class 2C

Page 486: Ovation Q Line

3-34. QRS

f 6alog

tedred

standtheonllynds.

3-34. QRS

Redundant Station Interface(Style 3A99108G01 through G06)

3-34.1. Description

Groups G01 through G06 (Must be revision F or later) are applicable for use in theCE MARK Certified System

The QRS is designed to provide a redundant interface to the DPU, a Manual/Automatic (M/A) station and a field device. The M/A station interface consist odigital outputs, 8 digital inputs, 3 analog outputs, 1 fixed analog output and 1 aninput. The M/A station interface is referenced to the DIOB ground.

The field interface consists of a single analog output which is electrically isolafrom DIOB ground. All analog outputs have readback circuits which are monitoby the on-board microcontroller. In addition to the readback circuits, themicrocontroller monitors several other functions to determine if the card isoperating properly.

The QRS card can be configured to operate as part of a redundant pair or as aalone card. When two QRS cards are configured as a redundant pair, one of cards will be the controller and the other will be the backup. If a problem occursthe controller and the quality of the backup is good, then control is automaticapassed to the backup QRS. The transfer of control could take up to 30 milliseco

Contact your Westinghouse representative for additional information.

M0-0053 3-420 5/99Westinghouse Proprietary Class 2C

Page 487: Ovation Q Line

3-35. QRT

theple

rtern

3-35. QRT

Q-Line RTD Input Amplifier(Style 7379A62 G01 and G02)

3-35.1. Description

Applicable for use in the CE MARK Certified System

The QRT card converts an analog field signal to digital data. The digital data issummation of a frequency counted for a time period; this time period is a multiof the power line frequency (50 or 60 Hz).

Each QRT card contains four individually isolated voltage-to-frequency convecircuits (channels). The output of each input circuit is processed by a commomicrocomputer, and the resulting digital data is multiplexed to the DistributedInput/Output bus (DIOB) as a 13-bit word (seeFigure 3-223).

Figure 3-223. QRT Block Diagram

DIOBData Address Control

mP andControlCircuits

Channel 4Voltage toFrequencyConverter

RTD

(+) (-) COM (+) (-) COM

...

...

Four Sets of 3-wire RTD Field Pick-ups

Channel 1Voltage toFrequencyConverter

RTD

DataBufferRAM

AddressComparator andData Selection

5/99 3-421 M0-0053Westinghouse Proprietary Class 2C

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3-35. QRT

erbles.

rter.

ined

3-35.2. Definition of Terms

• RCOLD = Resistance at bottom of span

• RHOT = Resistance at top of span

• RSUPP = Equivalent resistance to RCOLD on card

• IPROBE = Current through RTD

• VFS = Full scale input voltage

• RSPAN = RHOT minus RCOLD

• R = Current limiting resistors on the bridge

• Calculated Output = Output stripped of indicator bits (bits 15, 14)

• Output = Output including indicator bits (bits 15, 14)

3-35.3. Features

The QRT card uses an electrical isolation circuit (transformer) to separate theanalog input from the digital counting circuits. The isolation circuit provides powfor each analog input channel in addition to providing precise timing from a stafrequency. This timing is generated on the digital side of the QRT card circuit

Each analog input circuit contains circuitry for signal conditioning, biasing,auto-zero and auto-gain correction, and a clocked voltage-to-frequency conve

Offset and gain correction factors are calculated periodically by the QRT cardmicrocomputer. The frequency of the offset and gain calibration cycle is determby a constant which has been programmed into the memory of the systemcontroller.

M0-0053 3-422 5/99Westinghouse Proprietary Class 2C

Page 489: Ovation Q Line

3-35. QRT

RTD)

four.

odingRT

ut

Figure 3-224 shows a typical control system configuration using QRT cards.

In process control and monitoring applications where temperature must bemeasured in various locations, a three-wire Resistance Temperature Detector (input signal is connected to bridge the amplifier circuits.

The QRT card provides the bridges, converters, and multiplexers to interface isolated RTD inputs asynchronously to a process control or monitoring systemCopper, platinum, or nickel RTDs can be interfaced to the QRT card.

The QRT card includes an on-board 8039 microcomputer which, in addition tsupervising voltage-to-frequency conversion, converts the digitized voltage reato a percent span of the full scale input voltage, and also performs periodic Qcard calibration.

The QRT card is a voltage input card with four individually-isolated analog inpchannels. The front end is designed to convert field signals to a proportionalfrequency. There are two QRT card groups:

• G01–Full Scale 10 mV Nominal

Figure 3-224. Typical Control System Using QRT Cards

FIELD INPUTS

FIELD INPUTS

POWER LINE INPUTSQTB CARD

QRT CARD

QRT CARD

DIOB

DIOB

NOTE

THE QTB CARD OBTAINS A HIGH NORMAL MODE REJECTIONIN APPLICATIONS WHERE LARGE POWER LINE FREQUENCYVARIATIONS OCCUR.

CONTROLLER

NUMBER 1

NUMBER 35

10 VDC ref1000

---------------------------- Actual

5/99 3-423 M0-0053Westinghouse Proprietary Class 2C

Page 490: Ovation Q Line

3-35. QRT

nciesg to

ornels

• G02–Full Scale 33-1/3 mV Nominal

where:

10 VDC ref = 10 VDC+ 1 Percent

The on-card controller is common to all four input channels and converts the variable frequeto a parallel, 12-bit word. It also provides offset and gain correction and controls the interfacinthe DIOB.

Both QRT card groups include the following features:

• IEEE surge withstand capability

• Auto-zero, auto-gain corrections

• Each channel is electrically isolated from the other channels and the UIOBDIOB ground. If a twisted pair cable must be used, every two analog chanwill have a common ground.

• On-card memory (buffer) for storing conversion results

• Normal and common-mode rejection

10 VDC ref300

---------------------------- Actual

M0-0053 3-424 5/99Westinghouse Proprietary Class 2C

Page 491: Ovation Q Line

3-35. QRT

0%

H.

Figure 3-225 shows QRT card percentage accuracy versus RCOLD/RSPAN.

The range of the valid input voltages to the QRT card extends from -10% to +11of the defined full scale voltage (that is,−0.1 VFS≤ Vin ≤ VFS). The dynamic linearrange of the output is shown inFigure 3-226.

If the output exceeds 11FFH, such as an open RTD, the output is set to 1200Below 3E00H, such as a shorted RTD, the output is set to 3DFFH.

Figure 3-225. QRT Card Accuracy

4

2

3

5

4321RSPANRCOLD

0.1%

0.16%

0.2%

0.225%

0.3%

0.4%

0.425%

0.5%

WHERE: RSPAN = RHOT − RCOLD (STANDARD CALIBRATION)

1 GROUP 1 ACCURACY INCLUDING BRIDGE(4 Ω SPAN)

2 GROUP 2 ACCURACY INCLUDING BRIDGEWITH LOW RTD SPAN (10 Ω SPAN)

5 GROUP 2 ACCURACY INCLUDING BRIDGE(CUSTOM CALIBRATION)

3 GROUP 2 ACCURACY INCLUDING BRIDGE

4 GROUP 2 ACCURACY EXCLUDING BRIDGE

1

NORMAL RANGE

5/99 3-425 M0-0053Westinghouse Proprietary Class 2C

Page 492: Ovation Q Line

3-35. QRT

ridgeation

nges.RT thesets

RTontrolic 1ined

oller.

andted.

Four different measurements are taken for each channel. One reading is the binput; the other three readings are the calibration readings, taken when a calibrcycle occurs (period of approximately 8 sec). During a calibration cycle, thecalibration readings are monitored to ensure that they are within acceptable raIf they are not, bit 14 is set to Logic 0. At the end of the calibration cycle, the Qcard checks for the presence of the USYNC jumper. If the jumper is installed,controller tests for the USYNC signal’s presence and its limits. A failure here bit 15 to Logic 0.

Bit 15 is also set to Logic 0 during the power up routine of the QRT card. The Qmicrocomputer is then reset, and conversion of data begins when the reset cis removed and the QRT card buffer memory is updated. Bit 15 is reset to Logafter a warm-up pause is complete. The length of the warm-up pause is determby another constant which is programmed into the memory of the system contr

The calibration readings plus bits 14 and 15 are stored in QRT card memory remain unchanged until the next calibration cycle, at which time they are updaThe result of the conversion is a 12-bit binary word.

Table 3-116 lists the interpretations of QRT card hexadecimal output data.

Figure 3-226. QRT Card Output Dynamic Linear Range

Table 3-116. QRT Card Conversion Results

Hexadecimal OutputData Interpretation

C000 Zero Input

VIN

1.125 VFSVFS(−)0.125VFS

OUTPUTD200HD000H

OUTPUT1200H1000H

CALCULATED

OUTPUTFDFFH

CALCULATED OUTPUT3DFFH

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3-35. QRT

ot

C001 Zero+ 1

D000 + FS

D001-D1FF + Over range

D1FF Maximum operational range

D200 Above the operational range (or RTD open)

FFFF Zero− 1

FFFF-FE00 − Over Range

FE00 Minimum operational range

FDFF Below the operational range (or RTD shorted)

8000-BFFF Calibration readings not within acceptable range

0000-7FFF Warm-up or USYNC failure (USYNC not present or present but nwithin specifications)

Table 3-116. QRT Card Conversion Results (Cont’d)

Hexadecimal OutputData Interpretation

5/99 3-427 M0-0053Westinghouse Proprietary Class 2C

Page 494: Ovation Q Line

3-35. QRT

.

Block Diagram

Figure 3-227 andFigure 3-228 show functional block diagrams of the QRT card

Figure 3-227. QRT Card Bridge and I to F Circuits Block Diagram

+

+

(−)

+ 12 VDC

PSD (250 KHZ)FREQUENCY

INPUT F11T1

R5C2

D1

CLOCKSYNCHRONOUSCOMPARATOR

CURRENTSOURCE

INTEGRATOR

IREF

CAPACITORDISCHARGE

LOGIC

MUXCONTROLLER

I TO F INPUT SIGNAL

+12 VDC

POWERSUPPLY

SWITCHINGLOGIC

−12 VDC

10 VDCREF 100 KΩ GO(1)

50 KΩ GO(2)100 Ω GO(1)167 Ω GO(2)

INPUT (2)

INPUT (3)

INPUT (1)

INPUT (4)

FULLSCALE REF

GROUNDREF

VBRIDGE

COMMONMODE

GROUND

MULTIPLEXER

+

−+

+

+

RGAIN

500 Ω

500 Ω

200 KΩ I OFFSET

0-4 VDCRANGE

75 KΩFRONTEDGE

CONNECTOR

R R

RSUPPRTD

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3-35.4. Specifications

Ratings

• Number of Analog Inputs: 4

• Point Sampling Rate: 500 msec

• Auto Calibration Rate: 9 sec

Figure 3-228. QRT Card Digital Circuits Block Diagram

DIO

BUADD (0-7)DATA DIR

USYNCHI-LO

DATA GATE

ADDRESSJUMPERS

AOK

DOUT

MWR, WHI-LO

TUSYNC

WR

SS

CL

I/O

CL P15 TADD (0-2)THI-LO

UDAT (0-7)DEV BUSY)

ADDRESSDECODER

RAM LOADENABLE

ANALOGPOWER

CONTROL(250 KHZ) PSD

6 MHZ

P17

P16

BUFFER RAM LOADCONTROLLER

LEVEL SHIFTAND

BUFFER

BUFFERRAM

BUFFERLATCH

PROGRAMMEMORY

ADDRESSLATCH

8039MICRO-

COMPUTER

COUNTER(5)

COUNTERS(1 TO 4)

POWER UPAND

RESET

5 VOLTREGULATOR

BUS (DB0-7) LEN

CONTROL

ADDRESS

I/O

P10-12 P14

RESET

WD(0-7)

+5V

F1 (0 THROUGH 3)

+12V

ALE/4

60HZ 50

HZ

JU 3-1

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• Sampling Rate During Calibration: 1 sec

Power Supply

Normal Mode Voltage Input

Table3-117 lists the input signal ranges and input spans for both QRT card groThe QRT card signal input can be open or short circuited without damaging the

Normal Mode Rejection

• 60 dB at exactly 50 and 60 Hz (and harmonics) without line frequency track

• 25 dB at 50 and 60 Hz+ 5% without tracking

• Optional 60 dB at power line frequency (and harmonics)+ 5% with linefrequency tracing

Temperatures Stability

For accuracy specifications to apply, the QRT card’s temperature rate of chanmust not exceed+ 10°C per hour.

Minimum Nominal Maximum

Primary Voltage 12.4 VDC + 13.0 VDC 13.1 VDC

Optional Backup 12.4 VDC -- 13.1 VDC

Current – 1.0 A 1.2 A

Table 3-117. Normal Mode Voltage Input

G01 G02

Nominal Actual Nominal Actual

Input SignalRange

0 through 10 mV 0 through 33-1/3mV

Input Span 10 mV 33-1/3 mV

Vref ≈ 10 VDC

0 through Vref1000

------------------------------------ 0 through Vref1000

------------------------------------

Vref1000------------ Vref

300------------

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Amplifier Offset Temperature Drift Compensation

The QRT card features automatic compensation for amplifier offset temperatudrift.

Bridge Supply

• Accuracy: 10.0+ 0.1 VDC

• Bridge Current: 10 mA Maximum

• Temperature Coefficient: 40 ppm/degree C

AC normal mode rejection does not apply if peak AC exceeds 50 percent of tinput span (5 mV maximum for G01; 17 mV maximum for G02).

QTB Tracking Ranges (Optional)

58 Hz to 62 Hz or 45 Hz to 55 Hz

Input Channel Sampling Period

0.4 seconds

Common Mode Input

The IEEE surge may be applied without permanent damage to the QRT cardReduced accuracy is to be expected if reading are taken during the surge and10 seconds following the surge, or until the next calibration.

A continuous maximum of+ 500 VDC or peak AC with respect to system grounis allowable. The common mode reject ratio is not applicable if the AC peak vaexceeds 200,000 percent of the full-scale input scan (20 VAC maximum for G67 VAC maximum for G02).

A continuous over-range input up to 10 VAC or 10 VDC can be sustained withdamaging the QRT card. However, readings taken following sustained over-racan be affected for several seconds.

Common Mode Rejection

• 120 dB at DC

• 100 dB at exactly 50 and 60 Hz (and harmonics) without tracking

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• 80 dB at 50 and 60 Hz+ 5% without tracking

• Optional 100 dB at power line frequency (and harmonics)+ 5% with linefrequency tracking

DIOB Interface

The QRT card plugs into a standard DIOB backplane connector.

3-35.5. Field Input Connection

Figure 3-229 shows the QRT card-edge connectors.

A standard Q-Line series front-edge connector is used on the QRT card. Each ofour analog channels has four contacts:

• (+) input

• (−) input

• common

• shield

Figure 3-229. QRT Card Connectors

BackplaneConnector

Front Edge Connector(RTD Input)

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Table 3-118 lists QRT card front-edge connector pin numbers and signals.

Table 3-118. QRT Front Edge Connector Pin Assignments

Pin Number(Solder Side) Signal

Pin Number(Component Side) Signal

1A (−) INPUT (POINT 0) 1B (−) INPUT (POINT 0)

2A UNUSED 2B UNUSED

3A SHIELD (POINT 0) 3B (+) INPUT (POINT 0)

4A UNUSED 4B UNUSED

5A COMMON (POINT 0) 5B SHIELD (POINT 0)

6A UNUSED 6B (−) INPUT (POINT 1)

7A COMMON (POINT 1) 7B (−) INPUT (POINT 1)

8A UNUSED 8B UNUSED

9A SHIELD (POINT 1) 9B (+) INPUT (POINT 1)

10A UNUSED 10B UNUSED

11A (−) INPUT (POINT 2) 11B SHIELD (POINT 2)

12A UNUSED 12B UNUSED

13A (+) INPUT (POINT 2) 13B COMMON (POINT 3)

14A UNUSED 14B UNUSED

15A SHIELD (POINT 2) 15B SHIELD (POINT 3)

16A UNUSED 16B UNUSED

17A (−) INPUT (POINT 3) 17B SHIELD (POINT 3)

18A UNUSED 18B UNUSED

19A (+) INPUT (POINT 3) 19B (+) INPUT (POINT 3)

20A GROUND 20B ENABLE

21A UNUSED 21B UNUSED

22A UNUSED 22B UNUSED

23A GROUND 23B UADD 2

24A GROUND 24B UADD 3

25A GROUND 25B UADD 4

26A GROUND 26B UADD 5

27A GROUND 27B UADD 6

28A GROUND 28B UADD 7

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3-35.6. Card Addressing

As shown inTable 3-119, the QRT card uses DIOB address bits UADD 7 throuUADD 2 for address selection of the card, and uses UADD 1 and UADD 0 to sechannels 1 through 4 on the card.

To set a DIOB address, a jumper is inserted at the terminal pair(s) correspondithe UADD bit(s) which is (are) Logic 1. A jumper to tie 20A to 20B on the fronedge must always be inserted. This feature removes the card from its DIOB addwhen the front-edge connector is removed.Table3-119 lists the DIOB address bits’corresponding front-edge connector pairs.

Selection of RTD Bridges

Table3-120 lists the six standard groups of bridge modules which are availablethe QRT card.

Custom RTD bridges are available to the user. For ordering details, contact yWestinghouse representative.

Table 3-119. Front Edge Pairs for QRT Card Address Bits

UIOB or DIOB Address Bit Corresponding Front Edge Pairs

UADD 7 28A, B

UADD 6 27A, B

UADD 5 26A, B

UADD 4 25A, B

UADD 3 24A, B

UADD 2 23A, B

Table 3-120. QRT Card RTD Bridge Modules (7380A92)

Module Group Full Scale Voltage R Rsup Rspan

1 10 mV or 33-1/3mV

-- -- --

2 33-1/3 mV 60 KΩ 100Ω 200 Ω

A7 A6 A5 A4 A3 A2 A1 A0

Possible CardAddress

Channels1 through 4

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3-35.7. Controls and Indicators

User configurable QRT card components are shown inFigure 3-230.

Jumper JU3-1 is installed in order to perform line frequency tracking. At the endeach calibration cycle, the controller checks whether this jumper is installed. Ifnot installed, then the controller will use its own internal clock as a time base voltage-to-frequency conversion. If jumper JU3 is installed, the controller will uthe QTB board’s USYNC signal for that time base (50 or 60 Hz according to jumlocation).

Four stranded jumpers may be installed to tie together the ground and shieldchannels 1 and 2 to the ground and shield of channels 3 and 4.

3-35.8. Application Information

As noted previously, the QRT card provides an interface to four individualresistance temperature detector (RTD) sensors. These RTDs can provide coljunction compensation for thermocouple (QAV) inputs. The following sectionsprovide information intended to clarify the application of QRT cards.

3 33-1/3 mV 15 KΩ 120Ω 50 Ω

4 33-1/3 mV 30 KΩ 100Ω 100Ω

5 33-1/3 mV 30 KΩ 400Ω 100Ω

6 10 mV 8 KΩ 8.5Ω 8 Ω

Figure 3-230. QRT Card Components

Table 3-120. QRT Card RTD Bridge Modules (7380A92) (Cont’d)

Module Group Full Scale Voltage R Rsup Rspan

Jumper JU3-1 StrandedJumpers (4)

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estance.

a netp 1bele,

Ds.

Bridge Resistor Calculation

Each of the four channels on the QRT card contains a resistance bridge, locata small daughter card. These four daughter cards, called the bridge moduleseach connected to the QRT by a row of nine 25-mil square posts. Each voltagechannel provides its bridge with a precision 10 V source voltage.

Three of four resistance arms that form each bridge (R, R, and RSUPP) are locatedon the daughter card (seeFigure3-231). The fourth resistance arm is the RTD. Thbridge is said to be balanced when the resistance of the RTD equals the resiof the bridge resistor arm that contains RSUPP. The resulting bridge voltage is zero

If the resistance of the RTD increases, the bridge is no longer balanced, and positive bridge voltage exists. This bridge voltage is input to the QRT card. GrouQRT cards accept a full scale bridge voltage input of 10 mV, and would typicallyspecified to interface copper RTDs with very low resistance values (for examp10 Ohm). Group 2 QRT cards accept a full scale bridge voltage input of33.3333 mV, and would typically be specified to interface platinum or nickel RT

Figure 3-231. Bridge Resistance

+

(−)

COM

RTD

(RA-2) R

+ (−)

R (RA-1)

(RB-1)

(RC-1)

+10 V

VBRIDGE

RSUPP

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ified

able

twoD

t.

The formulas used to specify the bridge resistors are shown below:

RSUPP – This bridge arm resistance is normally set equal to RCOLD. The twobridge arm resistors (RB-1) and RC-1) must be precision resistors (as specon the applicable system drawing). Typically, only resistor RB-1 is used.Resistor RC-1 may also be used if it is necessary to parallel two of the availresistors to obtain the desired RSUPP.

Formula 1a. RSUPP = RCOLD

OR

Formula 1b. RSUPP = RB-1

OR

Formula 1c. RSUPP =

R – Two bridge resistance arms contain resistor R (RA-1 and RA-2). Theseresistors are used to limit the RTD probe current (which minimizes the RTself-heating error). In conjunction with RSUPP, R is used to select the RTDresistance (that is, RHOT) that corresponds to a full scale bridge voltage outpuIf RHOT and RSUPP are known, then R is selected.

To simplify the task of selecting a value for R, once RHOT and RSUPPhave beendetermined, a first order approximation of the bridge voltage is used:

Formula 2a.

RB-1 ∗ RC-1RB-1 RC-1+--------------------------------

VBridge10V

R---------- RRTD RSupp–( )×=

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putnputluesbitsel’s

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ts:

A full scale bridge output voltage is desired when RRTD = RHOT:

Formula 2b.

If the value of R that is calculated from Formula 2 cannot be obtained byselecting a resistor from the standard drawing, the user may select a resisfrom the drawing with a slightly higher resistance. Using such a resistor foRA-1 and RA-2 causes the span of resistance that can be measured by thecard to be slightly wider that RSPAN:

Formula 3.

Card Output Calculation Formulas

The QRT card provides a sixteen bit digital output for each of its four voltage inchannels. The analog voltage to digital code conversion circuit in each QRT ichannel produces a signed 14-bit output (sign bit plus 13 data bits), of which vaof 0 to 4096 represent the normal full-scale operating range. These fourteen (bits 13 through 0) are the fourteen least significant bits of the QRT card channdigital output. Bits 15 and 14 are status bits and will be set to 1 if the QRT cafunctioning properly.

The sixteen bit QRT digital output is typically expressed in hexadecimal form. TQRT card is calibrated so that when a full scale bridge voltage is applied to an inchannel, the channel’s digital output code is D000H. A digital output of C000Hindicates that the QRT card input channel is measuring a bridge voltage whiczero (that is, RRTD = RSUPP). Bridge voltages that lie between zero and full scalresult in digital output codes that range from C000H (0 counts) to D000H (40counts).

The following two formulas will be required to convert a bridge voltage into coun

R10 V

FULL SCALE BRIDGE VOLTAGE----------------------------------------------------------------------------------------- ∗ RHOT RSUPP–( )=

QRT Resistance Measurement SpanFull Scale Bridge Voltage

10V-------------------------------------------------------------- R×=

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Formula 4. VLSB =

Formula 5. COUNTS =

As described previously, when the bridge module resistors are chosen, a first oapproximation for the bridge voltage (Formula 2a) is used to derive the equationcalculating the value of R (Formula 2b). However, since Formula 2 is only anapproximation of the actual bridge voltage equation (Formula 6, shown belowusing Formula 2b to calculate R results in a resistance value that is not preciscorrect. If bridge resistors RA-1 and RA-2 are selected to equal the calculated vof R, the actual bridge voltage will not equal the bridge voltage expected (fromFormula 2). In addition, there is a non-linear relationship between RRTD andVBRIDGE (see Formula 6). As a result, for a given value of RRTD, there is adifference between the expected output (calculated from Formula 2) and the aoutput (calculated from Formula 6):

Formula 6. VBRIDGE =

Bridge Resistor Selection and Output Examples

The following examples illustrate how using a first order approximation of thebridge voltage to calculate R affects the expected (ideal) hexadecimal output cas does the inherent non-linearity of the bridge. For each example, the valuesbridge resistors R and RSUPPare calculated. Then, five values for RRTD, ranging inequal increments from RCOLD to RHOT will be used to calculate bridge voltages,first using Formula 2, and then using Formula 6. The two resulting bridge voltvalues will be used to calculate counts and hexadecimal output codes.

Example A.

Given the following values:

RCOLD =120ΩRHOT =170ΩRSUPP is set equal to RCOLD (120Ω)

From the values given for RCOLD and RHOT, the RTD is obviously not a copperRTD, so a Group 2 QRT card is selected. This provides a full scale bridge volof 33.3333 mV.

FULL SCALE BRIDGE VOLTAGE4096

-----------------------------------------------------------------------------------------

VBRIDGE

VLSB----------------------

10 V * RRTD

R RRTD+-------------------------------

10 V * RSUPP

R RSUPP+----------------------------------–

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nt

Since a 120Ω resistor is available on the standard drawing (651A129), bridgeresistor RB-1 will be 120Ω (RC-1 is not required).

Formula 2b is used to calculate the value of R (bridge resistors RA-1 and RA

A 15 KΩ resistor is available from the standard drawing, so bridge resistors Rand RA-2 will have this value. With all three bridge resistors selected, the bridvoltages, counts, and hexadecimal output codes can be calculated.

For the following RTD resistance values:

Formulas 2 and 6 can be used to calculate bridge voltages (first order approximand actual):

Formula 2a.

OR

Formula 6.

The voltage weight of one count (or LSB) is calculated using Formula 4.

Formula 4. VLSB =

Using the bridge voltage figures calculated for each RTD resistance value,Formula 5 can be used to calculate the corresponding ideal number of counts

Formula 5. COUNTS =

The hexadecimal output codes are determined by converting the decimal counumber into hexadecimal and adding C000H. The results are shown inTable 3-121.

120Ω 132.5 Ω 145 Ω 157.5 Ω 170 Ω

R10 V

33.3mV------------------- ∗ 170Ω 120Ω–( ) 15 KΩ= =

VBRIDGE Expected( )10 V

15000Ω--------------------- * RRTD 120 Ω–( )=

VBRIDGE Actual( )10 V * RRTD

15KΩ RRTD+---------------------------------- 10 V * 120Ω

15.120KΩ--------------------------------–=

33.333 mV4096

--------------------------- 8.138µV=

VBRIDGE

8.138µV-----------------------

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Example B.

Given the following values:

RCOLD = 8.5ΩRHOT = 14.5ΩRSUPP is set equal to RCOLD (8.5Ω)

From the values given for RCOLD and RHOT, the RTD must be a copper RTD, so Group 1 QRT card is selected. This provides a full scale bridge voltage of10.000 mV.

Since an 8.5Ω resistor is not available on the standard drawing, bridge resistoRC-1 and RB-1 will both be required. If two 17Ω resistors are placed in parallel (aswill be the case with RC-1 and RB-1), the resulting resistance is 8.5Ω. The standarddrawing does include a 17Ω resistor, so both RC-1 and RB-1 will be set equal to17 Ω.

Formula 2b is used to calculate the value of R (bridge resistors RA-1 and RA

A 6000Ω resistor is available from the standard drawing, so bridge resistors Rand RA-2 will have this value. With all three bridge resistors selected, the bridvoltages, counts, and hexadecimal output codes can be calculated.

For the following RTD resistance values:

Formulas 2 and 6 can be used to calculate bridge voltages (first order approximand actual):

Table 3-121. Bridge, Count, and Output Values (Example A)

RTD ExpectedBridge V

ExpectedCounts

ExpectedOutput

ActualBridge V

ActualCounts

ActualOutput

170Ω 33.333 mV 4096 D000H 32.698 mV 4018 CFB2H

157.5Ω 25.000 mV 3072 CC00H 24.544 mV 3016 CBC8H

145Ω 16.666 mV 2048 C800H 16.376 mV 2012 C7DCH

132.5Ω 8.333 mV 1024 C400H 8.195 mV 1007 C3EFH

120Ω 0.000 mV 0 C000H 0.000 mV 0 C000H

8.5Ω 10 Ω 11.5 Ω 13.0 Ω 14.5 Ω

R10 V

10.000 mV--------------------------- ∗ 14.5Ω 8.5Ω–( ) 6000Ω= =

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Formula 2a.

OR

Formula 6.

The voltage weight of one count (or LSB) is calculated using Formula 4.

Formula 4. VLSB =

Using the bridge voltage figures calculated for each RTD resistance value,Formula 5 can be used to calculate the corresponding ideal number of counts

Formula 5. COUNTS =

The hexadecimal output codes are determined by converting the decimal counumber into hexadecimal and adding C000H. The results are shown inTable 3-122.

Table 3-122. Bridge, Count, and Output Values (Example B)

RTD ExpectedBridge V

ExpectedCounts

ExpectedOutput

ActualBridge V

ActualCounts

ActualOutput

14.5Ω 10.000 mV 4096 D000H 9.962 mV 4080 CFF0H

13.0Ω 7.500 mV 3072 CC00H 7.473 mV 3061 CBF5H

11.5Ω 5.000 mV 2048 C800H 4.983 mV 2041 C7F9H

10.0Ω 2.500 mV 1024 C400H 2.492 mV 1021 C3FDH

8.5Ω 0.000 mV 0 C000H 0.000 mV 0 C000H

VBRIDGE Expected( )10 V

6000 Ω------------------ * RRTD 8.5 Ω–( )=

VBRIDGE Actual( )10 V * RRTD

6000Ω RRTD+------------------------------------ 10 V ∗ 8.5Ω

6008.5Ω-------------------------------–=

10.000 mV4096

---------------------------- 2.44 µV=

VBRIDGE

2.44 µV----------------------

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Use of RTDs and Segments

The DPU’s cold junction compensation approach allows two separate temperazones, called segments, to be defined in each cabinet. For each segment, twtemperature readings can be averaged. Any thermocouple points terminated given segment will use the segment’s (averaged) temperature reading. This pevery accurate compensation when required.

Segments are defined by the addresses assigned to the RTDs. The QRT card auses the block of four hardware addresses beginning at F8. The first two addr(F8 and F9) are dedicated to the first segment, and the second two addresseand FB) are dedicated to the second segment. If only addresses F8 and F9 aassigned, only one segment will be defined. If temperature averaging is not toused, only one address in each segment can be assigned (for example, F8 insegment 1 and FA in segment 2).Figure 3-232 illustrates two of the possiblecombinations of RTD(s) and segment(s).

Each segment uses two QRT inputs, whether or not two RTDs are used. The seQRT input cannot be used for customer RTD inputs, since it would be averagedthe cold junction temperature. Also, two bridges must be installed for each segmeven if the second input is not used.

Note

If RTDs are mounted in a separatetermination (B) cabinet, a half-shellextension and baffle kit are required toprevent fan cooling from affecting thetemperature reading.

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are

TD:

For additional information on cold junction compensation (CJ record field, softwaddressing, etc.), refer to“Record Types User’s Guide” (U0-0131) and “MA CUtilities User’s Guide” (U0-0136).

Values for Sample RTDs

The following sample provides specific values for the Westinghouse standard R

Figure 3-232. RTDs and Segments

RTD 1(Address F8)

RTD 2(Address F9)

One SegmentRTD 1 and RTD 2 ValuesAre Averaged

RTD 1(Address F8)

RTD 4(Address FB)

Segment 1RTD 1 and RTD 2 ValuesAre Averaged

RTD 2(Address F9)

RTD 3(Address FA)

Segment 2RTD 3 and RTD 4 ValuesAre Averaged

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120Ω - Nickel RTD

Westinghouse Part No.: 774A759H01

Manufacturer: Minco Products (No. S4-60)

Alpha =.0081

For linear conversion:

Gain = 3780.378

Bias = 32.0

For 5th order polynomial conversion:C0 = 32.000C3 = 0.0000

C1 = 3835.6311C4 = 0.0000

C2 = −8044.8691C5 = 0.0000

If used with a G02 QRT card and a G03 bridge module, the following is true:

Span = 0 to 3.33 mVDC for a range of 0 to 70°C (32 to 158°F), 120 to 170Ω

Temperature Range Information

mV in VDC Temperature in °F Temperature in °C Ohms

0.0000000 32.0 0.0 120.00

0.0060386 57.0 13.89 130.01

0.0118357 81.0 27.22 139.95

0.0173913 104.0 40.00 149.79

0.0176328 105.0 52.78 159.99

0.0229468 127.0 52.78 159.99

0.0333333 158.0 70.00 170.17

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The following sample provides specific values for another common RTD:

100Ω - Platinum RTD

Manufacturer: Tempro

Alpha =0.00385

For linear conversion:

Gain = 30120.00

Bias = 32.0

For 5th order polynomial conversion:C0 = 32.0000 C3 = 80864.00

C1 = 27634.00 C4 = 20502.0E + 003

C2 = 61050.00 C5 = −31987.0E + 004

If used with a G02 QRT card and a G03 bridge module, the following is true:

Span = 0 to 3.33 mVDC for a range of 0 to 558°C (32 to 1036°F), 100 to 300Ω

Temperature Range Information

mV in VDC Temperature in °F Temperature in °C Ohms

0.0000000 32.00 0.0 100.00

0.0062151 219.20 104.0 140.01

0.0094422 316.40 158.0 160.30

0.0126693 413.60 212.0 180.24

0.0159562 512.60 267.0 200.22

0.0196614 624.20 329.0 222.31

0.0227092 716.00 380.0 240.15

0.0261753 820.40 438.0 260.07

0.0297610 928.40 498.0 280.26

0.0333333 1036.00 558.0 300.00

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3-35.9. Installation Data Sheet

1 of 4

Installation Notes (Refer to Figure 3-233):

1. Use three-conductor shielded cable to interface the RTDs to the terminal b

2. Group 1 QRT – 10 mV full scale (low-range bridge and 10Ω RTD)Group 2 QRT – 33.3 mV full scale (high-range bridge and 100Ω RTD)

Figure 3-233. QRT Wiring Diagram: Plant Grounding

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

10 V

CARD

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

EDGE-CONNECTOR FOR PLANT GROUNDED RTDS

20B

20APLUG-IN BRIDGE

1

(+)

SHIELD

(−)

RETURN

+

SHIELD

(−)

RETURN

RETURN

RETURN

(+)

SHIELD

(−)

(+)

SHIELD

(−)

5

PLANTGROUND

PLANTGROUND

RTD2

RTD1

RTD3

RTD4

2

POWER(+)(−)

CHANNEL 4

10 VPOWER

(+)(−)

CHANNEL 2

10 VPOWER

(+)(−)

CHANNEL 1

10 VPOWER

(+)(−)

CHANNEL 3

4

REQUIRED ENABLE JUMPER

Channel Shield(1 of 4)

Power Supply Return

Power Supply Return

Power Supply Return

Power Supply Return

5/99 3-447 M0-0053Westinghouse Proprietary Class 2C

Page 514: Ovation Q Line

3-35. QRT

r ofion

and

nnel

nnelfore,hield.

her at

er at

, the

is,the

is,the

3. Move the QRT line frequency jumper (located at the lower left hand cornethe QRT printed circuit card assembly) to the 50 Hz position if 50 Hz operatis desired.

4. One pair of QRT printed circuit card jumpers is used to connect Channel 1Channel 2’s power supply return and channel shield together. Therefore,Channel 1 and Channel 2 share a common power supply return and a chashield.

A second pair of QRT printed circuit card jumpers is used to connect Cha3 and Channel 4’s power supply return and channel shield together. ThereChannel 3 and Channel 4 share a common power supply and a channel s

5. Since Channel 1 and Channel 2’s power supply return are connected togetthe QRT, RTD1 and RTD2 must have their power supply return and shieldconnections tied together and grounded to a single point.

Since Channel 3 and Channel 4’s power supply return are connected togeththe QRT, RTD3 and RTD4 must have their power supply return and shieldconnections tied together and grounded to a single point.

6. If a QRT is to interface to both plant grounded and cabinet grounded RTDsfollowing rules apply:

Channel 1 and Channel 2 must interface to similarly grounded RTDs (thatboth RTDs must be cabinet grounded or both RTDs must be grounded to same plant ground).

Channel 3 and Channel 4 must interface to similarly grounded RTDs (thatboth RTDs must be cabinet grounded or both RTDs must be grounded to same plant ground).

M0-0053 3-448 5/99Westinghouse Proprietary Class 2C

Page 515: Ovation Q Line

3-35. QRT

IInstallation Data Sheet

2 of 4

Figure 3-234. QRT Wiring Diagram: Cabinet Grounding

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

10 V

CARD

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

EDGE-CONNECTOR FOR CABINET GROUNDED RTDS

20B

20APLUG-IN BRIDGE

1

(+)

SHIELD

(−)

RETURN

+

SHIELD

(−)

RETURN

RETURN

RETURN

(+)

SHIELD

(−)

(+)

SHIELD

(−)

5

RTD2

RTD1

RTD3

RTD4

2

POWER(+)(−)

CHANNEL 4

10 VPOWER

(+)(−)

CHANNEL 2

10 VPOWER

(+)(−)

CHANNEL 1

10 VPOWER

(+)(−)

CHANNEL 3

REQUIRED ENABLE JUMPER

Channel Shield(1 of 4)

Power Supply Return

Power Supply Return

Power Supply Return

Power Supply Return

SHIELD

SHIELD

4

5

5

5/99 3-449 M0-0053Westinghouse Proprietary Class 2C

Page 516: Ovation Q Line

3-35. QRT

lock.

r ofion

and

nnel

nnelfore,hield.

her at

half-a

er at

alf-a

, the

is,the

is,the

Installation Notes (Refer to Figure 3-234):

1. Use three-conductor shielded cable to interface the RTDs to the terminal b

2. Group 1 QRT – 10 mV full scale (low-range bridge and 10Ω RTD)Group 2 QRT – 33.3 mV full scale (high-range bridge and 100Ω RTD)

3. Move the QRT line frequency jumper (located at the lower left hand cornethe QRT printed circuit card assembly) to the 50 Hz position if 50 Hz operatis desired.

4. One pair of QRT printed circuit card jumpers is used to connect Channel 1Channel 2’s power supply return and channel shield together. Therefore,Channel 1 and Channel 2 share a common power supply return and a chashield.

A second pair of QRT printed circuit card jumpers is used to connect Cha3 and Channel 4’s power supply return and channel shield together. ThereChannel 3 and Channel 4 share a common power supply and a channel s

5. Since Channel 1 and Channel 2’s power supply return are connected togetthe QRT, RTD1 and RTD2 must have their power supply return and shieldconnections tied together and grounded to a single point. Terminal blockterminal number 5 allows RTD1 and RTD2 to be grounded at the cabinet shell. A hole is provided in the half-shell for the RTD cabinet grounding. UseNumber 6 screw and a Number 6 nut for this purpose.

Since Channel 3 and Channel 4’s power supply return are connected togeththe QRT, RTD3 and RTD4 must have their power supply return and shieldconnections tied together and grounded to a single point. Terminal blockterminal number 14 allows RTD3 and RTD4 to be grounded at the cabinet hshell. A hole is provided in the half-shell for the RTD cabinet grounding. UseNumber 6 screw and a Number 6 nut for this purpose.

6. If a QRT is to interface to both plant grounded and cabinet grounded RTDsfollowing rules apply:

Channel 1 and Channel 2 must interface to similarly grounded RTDs (thatboth RTDs must be cabinet grounded or both RTDs must be grounded to same plant ground).

Channel 3 and Channel 4 must interface to similarly grounded RTDs (thatboth RTDs must be cabinet grounded or both RTDs must be grounded to same plant ground).

M0-0053 3-450 5/99Westinghouse Proprietary Class 2C

Page 517: Ovation Q Line

3-35. QRT

RTundspers

ded

For CE MARK Certified System

3 of 4

Installation Notes (Refer to Figure 3-235):

1. Use 3/C Shielded Cable.

2. Group 1 – 10 mV full scale (low-range bridge and 10Ω RTD)Group 2 – 33.3 mV full scale (high-range bridge and 100Ω RTD)

3. Move frequency jumper for 50 Hz operation.

4. When using standard A-B cabinet wiring (twisted pairs), jumpers on the Qcard tying the grounds and shields of channels 1 and 2 together, and the groand shields of channels 3 and 4 together, must be installed. When these jumare installed, only one ground wire of each pair should be connected.

5. The power supply return and shield of the RTD channel must both be grounto a single point.

Figure 3-235. QRT CE MARK Wiring Diagram (Grounded at the B Cabinet)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

RETURN

(−)

RTD 1

SHIELD

(+)

RETURN

(−)

RTD 3

SHIELD

RETURN

SHIELD

(−)

RTD 2

(+)

RETURN

SHIELD

(−)

RTD 4

(+)

5/99 3-451 M0-0053Westinghouse Proprietary Class 2C

Page 518: Ovation Q Line

3-35. QRT

RTundspers

ded

For CE MARK Certified System

4 of 4

Installation Notes (Refer to Figure 3-236):

1. Use 3/C Shielded Cable.

2. Group 1 – 10 mV full scale (low-range bridge and 10Ω RTD)Group 2 – 33.3 mV full scale (high-range bridge and 100Ω RTD)

3. Move frequency jumper for 50 Hz operation.

4. When using standard A-B cabinet wiring (twisted pairs), jumpers on the Qcard tying the grounds and shields of channels 1 and 2 together, and the groand shields of channels 3 and 4 together, must be installed. When these jumare installed, only one ground wire of each pair should be connected.

5. The power supply return and shield of the RTD channel must both be grounto a single point.

Figure 3-236. QRT CE MARK Wiring Diagram (Grounded in the Field)

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

RETURN

(−)

RTD 1

SHIELD

(+)

RETURN

(−)

RTD 3

SHIELD

RETURN

SHIELD

(−)

RTD 2

(+)

RETURN

SHIELD

(−)

RTD 4

(+)

M0-0053 3-452 5/99Westinghouse Proprietary Class 2C

Page 519: Ovation Q Line

3-36. QSC

to ayalogSS

3-36. QSC

Speed Channel Card(Style 2840A75G01 and G02)

3-36.1. Description

The Speed Channel Card (QSC) converts tachometer signal pulses directly in14-bit binary speed number (seeFigure3-237). This binary number can be read ba software program via the DIOB bus interface. The card also contains an anoutput that is proportional to the input frequency. (For new applications, the Qcard is recommended).

Figure 3-237. QSC Block Diagram

5/99 3-453 M0-0053Westinghouse Proprietary Class 2C

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3-36. QSC

enof a viand

Block Diagram

A functional block diagram of the QSC is shown inFigure 3-238.

3-36.2. Features

The card counts zero crossing of the input signal for a sampling period and thlatches the value to allow reading from the DIOB interface. This value consists14-bit binary number that is simultaneously displayed on the cards front edge16 LEDs. To allow missing card detection, one bit (#15) is always high (“1”) athe other bit (#14) is always low (“0”).

There are two groups of QSC cards.

Figure 3-238. QSC Card Functional Block Diagram

DIO

B A

DD

RE

SS

AD

DR

ES

SC

OM

PAR

E

AD

DR

ES

SS

ELE

CT

JUM

PE

RS

RE

AD

EN

AB

LET

IMIN

G &

CO

NT

RO

LC

LOC

K

UP

CO

UN

TE

RLA

TC

HLA

TC

HD

IOB

DAT

A

AN

ALO

GO

UT

PU

T0-

10V

ZE

RO

CR

OS

SIN

GD

ET

EC

TOR

INP

UT

DE

LAY

TO

PR

EV

EN

T S

KE

WIN

G PU

LSE

TO

VO

LTA

GE

CO

NV

ER

TE

R

JUM

PE

R S

ELE

CT

ED

RA

NG

E

+VV

RE

F

0-15

00 R

PM

TO0-

6670

RP

M

SE

TAB

LE P

ULS

EC

IRC

UIT

M0-0053 3-454 5/99Westinghouse Proprietary Class 2C

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3-36. QSC

is

tput

0%3.0,n the

• Group 1 has a sampling period of 1/8 second and the 14-bit binary outputequal to 1/4 of the input frequency.

• Group 2 cards have a sampling period of 1/2 second and the 14-bit binary ouis equal to the input frequency.

In addition, the card contains a 0 to 10 volt analog output that is proportional toto 125% of the nominal input frequency. The nominal input ranges are 1.5, 1.8,4.0 and 6.67 kHz. These ranges are selected via jumpers which are located ocard (seeTable 3-123 andFigure 3-239).

3-36.3. Specifications

Inputs

The Speed Channel (QSC) card accepts a sine wave input. The input may beconnected to 120 Vac RMS without damage.

Sensitivity: 0.5V P-P @ 36 Hz

5.0V P-P @ 4.5 kHz

Common Mode Voltage: 20V P-P (Max.)

Nominal Input Speeds: 1.5 kHz (90,000 RPM)

1.8 kHz (108,000 RPM)

3.0 kHz (180,000 RPM)

3.6 kHz (216,000 RPM)

4.0 kHz (240,000 RPM)

6.67 kHz (400,200 RPM)

Table 3-123. QSC Input Frequency Selection

Nominal Speed(Hz)

1A

2B

4C

8D

16E

32F

64G

128H

1.5K X X

1.8K X X X X

3.0K X X X

3.6K X X X X X

4.0K X X X X X

6.67K X X X X X

X = Jumpers to be installed for desired nominal speed

5/99 3-455 M0-0053Westinghouse Proprietary Class 2C

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3-36. QSC

Input Impedance: 20 k ohms

DIOB Output

Data word: 16 Bits (Bits 0-13 = data, Bit 14 = 0, Bit 15 = 1, Bit 0 = LSB,Bit 13 = MSB)

Update Rate1/8 second for Group 11/2 second for Group 2

Output: Binary value that is 1/4 of the input frequency for Group1.Binary value equals the input frequency for Group2.

Accuracy 0.03% with one bit resolution (min,) over temperature range

Analog Output

Isolated Output Span10V

Nominal Input Speeds1.5, 1.8, 3.0, 3.6, 4.0 and 6.67 kHz

Output 0 to+10V proportional to 0 to 125% of nominaspeed setting

Accuracy: 0.06% of span for 3.0, 3.6, 4.0 and 6.67 kHz ranges0.09% of span for 1.5 and 1.8 kHz ranges

Output Noise<5 mV P-P

Output Load500 ohms or greater. Short circuit protection provided

Output Limits−0.7V + 0.3V to+11V + 0.6V

Reference Condition25 degrees C ambient, 13.0 V supply

Temperature Coefficient+ 0.005% per degree F.

Supply Coefficient0.02%/ volt

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3-36. QSC

persts forw:

3-36.4. Controls/Indicators

The LEDs indicate the output value (seeFigure 3-239)

3-36.5. Wiring

The QSC card employs the standard Q-Series front-edge connector. Eight jumare used to determine the DIOB address. Contacts supplied include two contacthe speed input and two contacts for the analog output signal. See table belo

Power Supply Voltage

Figure 3-239. QSC Card Components

Pin # Field Signals

15A Speed input signal

17A Speed input return

7B Analog output source (+)

5B Analog output return (−)

Minimum Nominal Maximum

Primary 12.4 V + 13.0 V 13.1 V

Optional Backup: 12.4 V -- 13.1 V

Current (Supplied by DIOB) 400 mA

LEDs

Speed SelectionJumpers

5/99 3-457 M0-0053Westinghouse Proprietary Class 2C

Page 524: Ovation Q Line

3-37. QSD

nicrd

f thed.

3-37. QSD

Servo Driver Card(Style 2840A78G01 through G04)

3-37.1. Description

Group 01 is applicable for use in the CE MARK Certified System

The Servo Driver (QSD) card is a position controller which interfaces the electrocontrol system via the UIOB to either two EH or two MH actuators. The QSD capositions the two EH or MH actuators, which operate the turbine steam valves oBFPT and MSR systems.Figure 3-240 shows a typical application of a QSD car

Figure 3-240. QSD Typical QSD Card Application

UIOB QSDCard

Position andIndicators

Pushbuttons

Feedback

Drive

Valve“A”

Valve“B”

M/A Station

Field

PosA

PosB

A

M

DriveFeedback

M0-0053 3-458 5/99Westinghouse Proprietary Class 2C

Page 525: Ovation Q Line

3-37. QSD

OB

tors

EHthe

hen isber.to

nd

gic

erlly

SDdge

3-37.2. Features

The QSD card has two modes of operation, which are:

• AUTO – where the QSD card converts a 12-bit binary number from the UIinto a position control signal to the EH or MH actuators

• MANUAL – where the QSD works with a manual station to produce theposition control signal to the EH or MH actuators

In Auto mode, the QSD card can be configured to control either EH or MH actuawith the insertion of on-card jumpers and resistors (seeTable 3-125 andFigure 3-245). When the EH actuator type is selected, the output control signal to the actuator is determined by applying a proportional plus integral control action toerror between the desired and actual values of the actuator position. The EHactuator position is determined by a Schaevitz DC-DC LVDT at the actuator. Wthe MH actuator type is selected, the output control signal to the MH actuatordetermined by applying an adjustable gain to the converted 12-bit binary numThe output control signal to the MH actuator is adjustable from 0 to 5 VDC or 010 VDC.

In Manual mode, the QSD card works with a manual station (M/A). The M/AStation increases or decreases the output control signal through the RAISE aLOWER pushbuttons. Indicator lamps on the M/A Station display the valveposition. The QSD card contains a two-speed manual clock and the control loused during Manual mode operations.

Operating mode selection is made from the UIOB. Auto mode selection isprevented when the UIOB controller is not ready. Additionally, a watchdog timswitches the card from Auto to Manual mode if the QSD card is not periodicaserviced by the UIOB controller.

The QSD card is available in one group (G01). Electrical connection to the Qcard is made through a 34-pin rear-edge connector (UIOB) and a 56-pin front-econnector (M/A Station and Field Connections).

5/99 3-459 M0-0053Westinghouse Proprietary Class 2C

Page 526: Ovation Q Line

3-37. QSD

3-37.3. Specifications

Block Diagram

Block Diagram Description

The following block diagram descriptions apply toFigure 3-241 throughFigure 3-244.

Figure 3-241. QSD Block Diagram

MASTER CLEARFASTLOWERRAISEAUTOMANUAL

MANUALAUTOREADYALIVE

ControlLogic

UIOBInterface

Up/DownCounter D/A

TP4JDA

Offset

(-)ValveCoil

Drives

LVDTDrive

PositionOutput

PositionFeedback

TJ

TP3

Output A

LVDTGain

LVDTZero

(-)

Direct

Jumpers

P + I

+24VDC

TJ

TJ

D/AOutput

Common

JDB

(-)ValveCoil

Drives

LVDTDrive

PositionOutput

PositionFeedback

TJ

TP1

Output B

LVDTGain

LVDTZero

(-)

Direct

Jumpers

P + I

+24VDC

UIOB

Offset

Span JDA

RFA

P+I

JDB

RFB

P+I

SpanTJ: Test JackTP: Test Point

TP2

M0-0053 3-460 5/99Westinghouse Proprietary Class 2C

Page 527: Ovation Q Line

3-37. QSD

algic.f a

H12-

ter.ion’s

or’syd bytors).t, the-

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e.

Power-Up and Master Clear

When power is applied, the power-up control logic initializes the card to Manumode and initiates RESET and CLEAR signals which set up the QSD card’s loAdditionally, this logic provides a CLEAR to the up/down counter on receipt oMASTER CLEAR from either actuator.

Up/Down Counter and D/A Converter

The up/down counter holds the 12-bit data count for control of either EH or Mactuators through the D/A converter. In Auto mode, the counter is loaded with abit actuator demand from the UIOB controller.Figure 3-242 shows the data wordcoming from the UIOB which contains the 12-bit demand for the up/down counIn Manual mode, the counter is incremented or decremented by the M/A StatRAISE or LOWER push-button.

Manual Mode

In Manual mode, the up/down counter driving the D/A converter is clocked updown when the RAISE or LOWER push-button is pressed on the M/A Stationfront panel. The rate at which the up/down counter is clocked is determined bwhether the FAST push-button on the M/A Station’s front panel is pressed anseparate plug-in resistors for the fast and slow clocks (see Controls and IndicaThe clock (fast or slow) operates at a constant rate when enabled. As a resuloutput of the D/A converter is a linear ramp while the RAISE or LOWER pushbutton remains depressed, causing the up/down counter to count.

When jumper A is not installed, the up/down counter holds its last value if neitRAISE nor LOWER is pressed. In this case, when both are pressed, LOWER tprecedence over RAISE. If jumper A is in place, the counter holds if both buttare pressed or neither button is pressed.

Except for the KEEP ALIVE, GO TO ALIVE, and GO TO MAN bits(Figure 3-242), the output from the UIOB controller is ignored in Manual mod

5/99 3-461 M0-0053Westinghouse Proprietary Class 2C

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3-37. QSD

Input and Output Bit Patterns

Figure 3-242. QSD Card Input Data

Figure 3-243. QSD Card Output Data

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Not Used

1 = Go to Manual

1 = Go to Auto

1 = Keep Alive

Bits

MSB

LSB

Up/Down Counter Data

HighByte

LowByte

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 = Card in Place

1 = Ready

1 = Manual, 0 = Auto

1 = Auto Push-button

Bits

MSB

LSB

Up/Down Counter Data

M0-0053 3-462 5/99Westinghouse Proprietary Class 2C

Page 529: Ovation Q Line

3-37. QSD

TO

s

sed,

TOO

is

ebit,rom

ove

terthedM/

Manual to Auto Transfer Sequence

To initiate a transfer from Manual to Auto mode, the operator must press the AUpush-button at the M/A Station’s front panel. If jumper C is installed, the AUTOpush-button signal generates an AUTO REQUEST, announcing the operator’request. If jumper C is not installed, the UIOB controller must determine if theoperator pressed the AUTO push-button. When the AUTO push-button is presits status is latched and is available in the QSD’s output data word (shown inFigure3-243) for the UIOB controller to read.The UIOB controller sends back a GO AUTO bit (shown inFigure3-242) when it sees that the operator pressed the AUTpush-button. If jumper B is in place, the GO TO AUTO bit generates an AUTOREQUEST.

If jumper G is installed, the QSD must be READY before an AUTO REQUESTgranted. To be READY, the QSD must be in Manual mode and be ALIVE(watchdog not timed-out), and the UIOB controller must output the same valualready contained in the upper 8 bits of the up/down counter. The KEEP ALIVEGO TO AUTO bit, and the correct data can all be contained in the same output fthe UIOB controller (Figure 3-242) if desired.

The QSD card grants the AUTO REQUEST and switches to Auto mode if the abconditions are satisfied and a MANUAL REQUEST has not been initiated.

Auto Mode

In Auto mode, data from the UIOB controller is loaded into the up/down counwhich drives the D/A converter. The QSD card’s UIOB interface logic latches two byte input data (Figure3-242) from the UIOB and transfers the 12-bit demanto the up/down counter. RAISE, LOWER, and FAST inputs to the QSD from theA Station are ignored in Auto mode.

5/99 3-463 M0-0053Westinghouse Proprietary Class 2C

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3-37. QSD

om

el.

se

er

l

ual

redter

us

thest

n inthe

Auto to Manual Transfer Sequence

Several events can generate a MANUAL REQUEST which initiates a transfer frAuto to Manual mode. These events are:

• An operator pressing the MANUAL push-button at the M/A Station’s front pan

• RESET signal due to low power supply voltage.

If appropriate enabling jumpers are installed, three other events can also cauMANUAL REQUESTS:

• Card not ALIVE (jumper D is installed).

• GO TO MAN bit from UIOB controller (jumper E is installed).

• RAISE or LOWER push-button pressed on M/A Station’s front panel (jumpF is installed).

If a MANUAL REQUEST is made, it immediately transfers the QSD to Manuamode even if an AUTO REQUEST is present. A MANUAL REQUEST alsoprevents an AUTO REQUEST from being granted if the QSD is already in Manmode.

Input Data to QSD from UIOB

When data is written to the QSD from the UIOB, it has a two byte format as pictuin Figure3-242. The 12-bit digital valve position is loaded into the up/down counand used to control the EH or MH actuators.

The GO TO AUTO and GO TO MANUAL bits of the input data cause continuoAUTO or MANUAL REQUESTS, respectively, when they are set, for they arelatched by the QSD card. The KEEP ALIVE bit is not latched when received byQSD. To keep the watchdog timer from timing out, a high KEEP ALIVE bit mube written to the card within the watchdog time-out period (Table 3-126).

Output Data from QSD to UIOB

The format for QSD card output data transfers to the UIOB controller is showFigure3-243 with the up/down counter data contained in bits 0 through 11 andQSD card’s status contained in bits 12 through 15.

CAUTION

The QSD card should not be read continuously ata rate faster than 100 times per second.

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3-37. QSD

B

E

reTheofg-in

the

(orto

uator

s a

ingeuntil itthe

Watchdog Timer

The watchdog timer is started on receipt of a high KEEP ALIVE bit from the UIO(seeFigure 3-242). If the UIOB does not write another KEEP ALIVE bit to theQSD within the timer’s selected time-out period, the timer times-out and ALIVgoes high. The ALIVE = high signal resets the card to Manual mode. A switchprovides user selection of watchdog time-out periods as listed inTable3-126 underControls and Indicators.

Valve Actuator Drive Circuits

The operating characteristics of these circuits (A and B, which are identical) adetermined by the plug-in resistors, potentiometers and jumpers JDA or JDB.block diagram ofFigure3-244 shows both the EH and MH actuator applicationsthese circuits. See Controls and Indicators for a detailed description of the pluresistors, potentiometer adjustments, and jumper installations.

When this circuit is set up for EH actuator operation, the plug-in resistors andjumpers are set up for a closed-loop operation as follows:

• RFA (or RFB) installed

• JDA (or JDB) removed

• RDA (or RDB) removed

For EH actuator application, both outputs (COIL1 and COIL2) are used to driveEH valve actuator. The D/A OUT signal from the D/A converter (Figure 3-244)drives the actuator via the summing amp and the P + I amp. With resistor RDARDB) removed, the linear amp provides P + I amplification. The resulting drivethe actuator is determined by the error signal and indicates the desired new actposition. The actual valve position is fed back to this circuit as the LVDTdifferential signal. This signal is presented to the LVDT calibration circuit.

The output of the LVDT calibration circuit is presented to the summing amp a0 to (−)10 VDC level equivalent to the actual position of the valve. This actualposition signal is summed with the desired position signal (D/A OUT), producthe error drive signal to the valve actuator coils. As the difference between thdesired and actual valve position decreases, the error drive signal decreases,is equal to zero (actual position = desired position). Additionally, the output ofLVDT calibration circuit is displayed on a position meter on the M/A Stationindicating the actual valve position.

5/99 3-465 M0-0053Westinghouse Proprietary Class 2C

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3-37. QSD

When this circuit is set up for MH actuator operation, the plug-in resistors andjumpers are set up for an open-loop operation as follows:

• RFA (or RFB) removed

• JDA (or JDB) installed

• RDA (or RDB) installed

Power Requirements

• Primary Voltage: 12.4 VDC minimum13.0 VDC nominal13.1 VDC maximum

• Backup Voltage: 12.4 VDC minimum13.1 VDC maximum

• Current:

Figure 3-244. EH and MH Actuator Applications

With EH actuator – 1.2 A maximum

With MH actuator – 1.6 A maximum

D/A Out Gain andOffset Amp.

EH ValveActuator

1/TES

LVDTCalibration

PositionMeterM/AStation

DC LVDT Position Indication

PositionMeterM/AStation

DC LVDT Position Indication

LVDTCalibration

Gain & Offset

K1+TS

TS( )

P+ I

MHValve

Actuator(TorqueMotor)

D/A Out

Setpoint0 to + 10 V

Position0 to (-)10 V

Error

Coil 1

Coil 2

0 to + 10 V

0 to + 10 V

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act.SD

the

Field Interface

As shown in the block diagram ofFigure 3-241, the control circuitry for eachactuator is identical. The only exceptions are the provisions for individualcalibration of the various circuit parameters which depend on selected resistovalues (seeTable 3-129).

Valve Coil Drive (Two Circuits)

• EH actuator: two current outputs of+24 mA each into 80Ω

• MH actuator: a single output, adjustable from 0 VDC through (-)10 VDC fuscale across 100Ω minimum. (MH output is negative with respect to common

Position Feedback (Two Circuits)

A high impedance differential input receives the position signal from ademodulating Linear Variable Differential Transformer (DC LVDT), where:

• Input Scan:+1.5 VDC to+15.0 VDC depending on LVDT type and stroke

• Input Impedance: Differential (with floating source), 400KΩInputs (tied together) to common, 150 KΩ

• Common Mode Voltage:+10 VDC maximum

LVDT Drive (Two Circuits)

• +24 VDC+1.2 V at 25 mA

• Supply Voltage Coefficient:+0.4%/volt

• Average Temperature Coefficient:+0.025%/°C

Master Clear

The Master Clear is a self-powered differential input connected to a field contClosing the field contact clears the up/down counter but does not switch the Qcard to Manual mode. Specifications include:

• Open Circuit Voltage: 42 VDC+8 V

• Closed Circuit Current: 15 mA maximum

• Contact and Wiring Resistance: 100Ω maximum

• Delay: 6 msec. maximum (The delay is from the time of contact closure toappearance of 0.0 VDC at the D/A output.)

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3-37. QSD

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3-37.4. Operator Interface

DIM Inputs

DIM inputs are typically connected to operator pushbuttons. Specifications incl

• Input Voltage Range: (−)0.5 V to +30 VDC maximum

• Low Input Voltage: 2.0 VDC maximum

• High Input Voltage: 10.0 VDC minimum

• Delay: 0.75 msec. maximum

DIM Outputs

DIM outputs are typically connected to operator panel lamps. Specificationsinclude:

• High Output Voltage: Open Collector, 30 VDC maximum

• High Output Leakage Current: 0.5 mA maximum

• Low Output Voltage: 1.0 VDC maximum

• Low Output Current: 250 mA maximum

Position Output (Two Circuits)

• Output Span: 0 through 10 VDC which corresponds to 0 through 100% ofactuator position

• Load Resistance: 2 KΩ minimum

• Accuracy: Adjustable to within 0.1% of span, measured by comparing theposition output with the position feedback input

• Temperature Coefficient:+0.02% of span/°C

Analog Controller

Each of the two QSD card controllers is jumper programmed as either a DireOutput or a P + I controller.

Direct Output Controller (MH Actuator)

• Offset: (−)1.0 VDC to +1.0 VDC

• Span: 1.0 VDC to 10 VDC

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3-37. QSD

the

• Accuracy:+0.1% of span

• Temperature Coefficient:+0.02% of span/°C

• Output: Single output adjustable from 0 to (-)10V full scale across 100Ωminimum. (Output is negative with respect to common).

P + I Controller (EH Actuator)

• Offset: (−)10% to +10% of demand

• Span: Actuator position from 25% to 200% for 100% demand

• Accuracy: Position Feedback within 0.1% of span for adjusted demand

• Temperature Coefficient:+0.02% of span/°C

• Gain: 1.22 to 122*

• Reset Time Constant: 0.5 sec to 10 sec*

Note*

The gain and reset time constants areinterrelated and controlled by the resistors.The relationships are detailed inTable 3-131.

Signal Interface

The standard front-edge connector interfaces the QSD to the M/A Station andfield. Table 3-124 lists the connector’s pin designations.

Table 3-124. QSD Front-Edge M/A Station and Field Connector

Pin # Signal Name Pin # Signal Name1A Ground (System Common) 1B Ground

2A -Master Clear ContactInput

2B Ground

3A +Master Clear ContactInput

3B Ground

4A Ground (Return to pins 12A, 13A) 4B Ground (Return to pin 16B)

5A Ground (Return in pins 8A, 9A) 5B Ground (Return to pin 17B)

6A Ground (Return to pin 10A) 6B AUTO IN

7A Ground (Return to pin 11A) 7B FAST

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3-37. QSD

7B

A,

In Table 3-124: pins 1A through 17A are Field connections, pins 1B through 1are M/A Station connections, pins 21A through 28A and 21B through 28B areUIOB Address Selection connections.

The following front connector pins are tied together on the QSD: 1A, 4A, 5A, 67A, 1B, 2B, 3B, 4B, and 5B. Pins 1A and 1B should also be tied to the SystemUIOB Ground at one point in the system.

8A COIL 1 -- “A” actuatorvalve coils

8B RAISE

9A COIL 2 -- “A” actuatorvalve coils

9B LOWER

10A LVDT Drive “B” actuator 10B MAN IN

11A LVDT Drive “A” actuator 11B READY

12A COIL 1 -- “B” actuatorvalve coils

12B AUTO

13A COIL 2 -- “B” actuatorvalve coils

13B ALIVE

14A -LVDT Feedback “B”actuator

14B MAN 2

15A +LVDT Feedback “B”actuator

15B MAN 1

16A -LVDT Feedback “A”actuator

16B 0 - 10 V Position Ind. (“B”)

17A +LVDT Feedback “A”actuator

17B 0 - 10 V Position Ind. (“A”)

18A SLOT (NO PIN) 18B SLOT (NO PIN)

19A Unused 19B Unused

20A Unused 20B Unused

21A UIOB Grounds 21B ASEL0

22A UIOB Grounds 22B ASEL1

23A UIOB Grounds 23B ASEL2

24A UIOB Grounds 24B ASEL3

25A UIOB Grounds 25B ASEL4

26A UIOB Grounds 26B ASEL5

27A UIOB Grounds 27B ASEL6

28A UIOB Grounds 28B ASEL7

Table 3-124. QSD Front-Edge M/A Station and Field Connector (Cont’d)

Pin # Signal Name Pin # Signal Name

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3-37. QSD

pin or

3-37.5. Card Addressing

The QSD card address is determined by the eight jumpers detailed inAppendixB.Inserting a jumper between an ASELX pin on the B side and the correspondingon the A side encodes a “1” on the address line. The QSD may be read fromwritten to via the UIOB only if the address from the UIOB is the same as thatselected by the A and B pins on the front-edge connector.

3-37.6. Controls and Indicators

Figure 3-245. QSD Card Outline and User Controls

LEDsRZB,RGB

RZA,RGA

JDB

D/A InvertBuffers

Auto/ManualSelection

WatchdogTimeout

ABCDEFG

RF,RS RFB, ROB,

RSB, RTB,

RDB

RFA, ROA,RSA, RTA,RDA

TestJacks

Pots.

Span BPot. Span A

Pot.

Offset BPot.

Offset APot.

JDA

TP1 - 4

Gain and Zero

Jumpers

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3-37. QSD

Front Edge

Potentiometers (total of 8):

• LVDT ZERO (One each circuit A and B)

• LVDT GAIN (One each circuit A and B)

• OFFSET (One each circuit A and B)

• SPAN (One each circuit A and B)

Test Jacks (total of 4):

• POSITION A

• POSITION B

• D/A OUTPUT

• COMMON

Test Point Pins:

• TP1 (Coil 2, circuit B)

• TP2 (OFFSET, circuit B)

• TP3 (Coil 2, circuit A)

• TP4 (OFFSET, circuit A)

• JDA (Coil 1, circuit A)

• JDB (Coil 1, circuit B)

LED Indicators

• POWER ON

• MANUAL

• READY

• ALIVE

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3-37. QSD

card is

O

Jumpers

Table3-125 provides a list of QSD card jumpers and the selected operationalcharacteristic produced when each is installed. The location of these jumpersshown onFigure 3-245.

Watchdog Timeout Select Switch

The Watchdog Timeout switch (Figure3-245) sets timeout periods as listed inTable3-126.

Table 3-125. QSD Card Jumpers

Jumper Description

JDA Installed for direct configuration of circuit A.

JDB Installed for direct configuration of circuit B.

A When installed, simultaneous RAISE and LOWER signals fromM/A Station cause the output to hold.

B When installed, the GO TO AUTO bit from the UIOB Controllerproduces an AUTO REQUEST (Auto mode).

C When installed, pressing the AUTO push-button at the M/AStation produces an AUTO REQUEST.

D When installed, a timeout (ALIVE = high) from the WatchdogTimer causes the card to switch to Manual mode.

E When installed, the GO TO MAN bit from the UIOB Controllerplaces card in Manual mode.

F When installed, a RAISE or LOWER signal from the M/A Stationplaces card in Manual mode.

G When installed, a READY state must be latched before an AUTREQUEST is granted, placing card in Auto mode.

Table 3-126. QSD Watchdog Timeout Selections

Switch SegmentsWatchdog Timeout

All times +25%H J K

0 0 0 1/16 second (62 msec)

0 0 1 1/8 second (125 msec)

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lues

D/A Converter Input Buffer Selection

Under normal conditions non-inverting buffers (Figure3-245) are used as inputs tothe D/A converter. However, these can be replaced by inverting buffers, which cthe D/A converter to behave inversely. With the inverting buffers installed, inpdata of 000 (hexadecimal) produces +10 VDC at the output from the D/A conveoutput, and input data of FFF (hexadecimal) produces 0 VDC at the output.

Up/Down Counter Clock Rate Selection, Manual Mode

Selection of which clock (FAST or SLOW) is made by the FAST push-button atM/A Station. The FAST clock’s rate is determined by selecting values for plugresistor RF, while the SLOW clock’s rate is determined by selecting values foplug-in resistor RS (Figure 3-245). These clocks, by stepping the counter in theManual mode, produce a linear ramp analog level to the valve actuator at ratesare adjusted by changing the resistor value.Table 3-127 indicates the time for fullscale ramp generation and percent of change per minute for plug-in resistor vain both fast and slow applications.

0 1 0 1/4 second (250 msec)

0 1 1 1/2 second (500 msec.)

1 0 0 1 second

1 0 1 2 seconds

1 1 0 4 seconds

1 1 1 8 seconds

Table 3-127. QSD Clock Rate Selection

RF or RS Value

Full Scale Ramp Percent/Minute

Fast Slow Fast Slow

2 KΩ 15 sec. 30 sec. 400 200

5 KΩ 25 sec. 50 sec. 240 120

10 KΩ 37 sec. 74 sec. 162 81

Table 3-126. QSD Watchdog Timeout Selections (Cont’d)

Switch SegmentsWatchdog Timeout

All times +25%H J K

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3-37. QSD

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cific

Analog Output State Plug-in Resistor Selection

Figure3-246 shows an equivalent circuit for the Analog Output Circuits (A and BEach circuit contains up to seven plug-in resistors determining specificcharacteristics per application needs.Table 3-128 lists each resistor, its function,and typical values for both Direct Output or P + I controller applications.Additionally, operating equations are provided as an aid in determining the speparameters for each application.

20 KΩ 70 sec. 140 sec. 86 43

50 KΩ 175 sec. 350 sec. 34 17

100 KΩ 330 sec. 660 sec. 18 9

Figure 3-246. QSD Analog Output Stage

Table 3-127. QSD Clock Rate Selection (Cont’d)

RF or RS Value

Full Scale Ramp Percent/Minute

Fast Slow Fast Slow

RDX

RTXROX

RFX

ROS

RIN

RLP

V1

VO

V3

SPAN

50K

50K

1µf

RSX

IO

330

JDX

330

80

80-

+

EHValveCoils

V2

D/A Out0 to 10 VDC

Bias± 1.2 VDC

PositionFeedback0 to (-) 10 VDC

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3-37. QSD

Resistor locations are illustrated inFigure 3-245.

Note

The presence or absence of these resistors, aswell as the resistor values varies greatly fromone application to the next. Therefore, theinformation provided here is of a generalnature. (*See calibration notes to select theresistor for the desired system performance.)

Table 3-128. QSD Analog Output Stage Plug-in Resistors

ResistorFunction

Controlled

Typical Values*

Direct Output P + I Controller

RZA or RZB LVDT Zero 10 KΩ 10 KΩ

RGA or RGB LVDT Gain 2 KΩ to 20 KΩ 2 KΩ to 20 KΩ

RFA or RFB PositionFeedback

open 0 to 500 KΩ

ROA or ROB Offset 0 to 200 KΩ 0 to 500 KΩ

RSA or RSB Span 24.9 KΩ 0 to 500 KΩ

RTA or RTB Time Constant open 500 KΩ to 10 MΩ

RDA or RDB Direct Output 10 KΩ to 200 KΩ open

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3-37. QSD

Direct Output Operating Equations

• Voltage Gain:

Note*

Filter Term when RTx = jumper

• Span:

• Offset (referred to D/A OUT):

• Filter Time Constant (when RTx= jumper):

P + I Controller Operating Equations

• Gain:

where:

500Ω = Scale Factor =

Vo

VI------ −( )

RDx

RIN----------

11 RDx 1µf×( )S+--------------------------------------------

=*

SPAN 10VDCRDx

RIN----------

=

OFFSET 1.2VDCRIN

ROS---------

±=

TC RDx( )1 µf=

∆I o

∆V2----------

500Ω410Ω-------------

RTx

RLP----------

11 RTx 1µf×( )S+-------------------------------------------

=

V2

I o------ 10 VDC

20 mA---------------------=

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3-37. QSD

• Proportional Gain:

• Reset Time Constant:

• Offset:

• Span (Position Feedback vs. D/A OUT):

Calibration Notes

This description provides general QSD calibration information.

LVDT Calibration

Plug-in resistors RZA and RZB should be 10KΩ. Plug-in resistors RGA and RGBshould be selected to meet position feedback requirements as follows:

Table 3-129. LVDT Calibration resistor Selection

Position Feedback from LVDT RGA or RGB Value

+1 VDC to+2.5 VDC 2KΩ

+2.5 VDC to+6.0 VDC 5KΩ

+5.0 VDC to+12.5 VDC 10KΩ

+10.0 VDC to+20 VDC 20KΩ

K500410---------

RTx

RLP----------

1.22RTx

RLP----------

= =

TC RTx( )1 µf=

OFFSET 1.2VDCRIN

ROS---------

±=

SPANRIN

RLP---------

=

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3-37. QSD

ted

h

and

The LVDT ZERO potentiometer of each analog output circuit (A and B) is adjusfor 0 VDC at the POSITION output, with the LVDT in its minimum position. TheLVDT GAIN potentiometer is adjusted for 10 VDC at the POSITION output, witthe LVDT in its maximum position.

Direct Output Calibration

The A and B Analog Output Circuits are identical and independently configured calibrated. The plug-in resistor configuration is selected as indicated inTable 3-130.

Table 3-130. QSD Direct Output Resistors

Resistor Range Recommendation

ROA andROB

0 to 200 KΩ As desired

RSA and RSB 0 to 200 KΩ 24.9Ω

RTA andRTB

jumper oropen

As desired

RDA andRDB

10KΩ to200KΩ

Where:

Desired Span1 to 3 VDC3 to 6 VDC6 to 10 VDC

RD Value10KΩ20KΩ50KΩ

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3-37. QSD

ed

P + I Controller Calibration

The A and B Analog Output Circuits are identical and independently configurand calibrated. The plug-in resistor configuration is selected as indicated inTable 3-131.

Table 3-131. QSD P + I Controller Resistors

Resistor Range Recommendation

RFA and RFB 0 to 500 KΩ

Use the lowest possible valuesROA andROB

0 to 500 KΩ

RSA and RSB 0 to 500 KΩ

RTA andRTB

500KΩ to10MΩ

Where the Gain Range vs. Reset TimeConstant is as follows:

TC/GAIN

1 sec/2.44 to 24.410 sec/24.4 to 122

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3-37. QSD

3-37.7. Installation Data Sheet

For CE MARK Certified System

Figure 3-247. QSD CE MARK Wiring Diagram

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

A-Position

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

A-LVDT Feedback

(+)

(SHIELD)

(−)

A-Servo Coll #2

(+)

(SHIELD)

(−)

A-Servo Coll #1

Raise IN/

1

10B

8B

7B

9B

5A

8A

9A

16A

17A

5B

17B

2A

7A

11A

4A

12A

13A

14A

15A

4B

16B

3A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

B-Position

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

(+)

(SHIELD)

(−)

B-LVDT Feedback

(+)

(SHIELD)

(−)

B-Servo Coll # 2

(+)

(SHIELD)

(−)

B-Servo Coll #1

(+)

(SHIELD)

(-)

24 VDC

2

Master Clear (-)

Manual IN/

Fast IN/

Lower IN/

Master Clear (+)

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3-37. QSD

les,

the

Installation Notes (Refer to Figure 3-247):

1. Analog inputs and outputs must use individually-shielded twisted pair cabwith the shields connected to earth ground at the B cabinet, as shown.

2. Digital inputs must use shielded cable (an overall shield is acceptable), withshield connected to earth ground at the B cabinet.

M0-0053 3-482 5/99Westinghouse Proprietary Class 2C

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3-38. QSE

temfE

uts

card.

he

OBangeister

the astime

are

anyfbee

3-38. QSE

Sequence of Events Recorder(Style 7380A36G01 and G02)

3-38.1. Description

Groups 01 and 02 are applicable for use in the CE MARK Certified System

The QSE Card is a DIOB-compatible single-card sequence of events subsyswhich provides monitoring of field status points, recording, and time tagging ochanges in plant status (seeFigure3-248). Through a rear-edge connector, the QSinterfaces with the Distributed I/O Bus (DIOB), a collection of parallel wires(signal, power, and ground), into which point cards are inserted. The digital inpare brought onto the card via a front-edge connector.

The QSE interfaces to sixteen field contacts using a common return line. On-contact-wetting supply, signal conditioning, and optical isolation are providedDigital filtering is used to reject input signal changes with less than a minimumpredetermined time interval (3.5 msec. for Group1 and 3 msec. for Group2). Toutputs of the digital filters can be read at any time by the DIOB controller as“current status.”

The card contains a “mask register” which can be both read or written by the DIcontroller. The mask register content determines which bits are checked for chof state and cause entries in the Event Buffer. During the power-up the mask regis set to all “ones.”

On Group 2 QSE cards, the mask bits have the additional function of holdingcorresponding Chattering Flag and Chattering Counter in the reset condition,long as the mask bit is set to zero. The monitoring for chattering starts at the the mask bit is set to 1.

Dual Event Buffers are used to permit reading of one Event Buffer, while eventsentered into the other Event Buffer.

The Group 2 QSE card has the additional feature of recognizing “chattering” onof its sixteen inputs. “Chattering” is defined as a condition when the number oinput changes exceed four within a specified time interval. This time interval canset from 20 to 255 msec. in firmware only. After the PROMs are “burned” in thtime interval is constant.

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3-38. QSE

rdup1

it

Time Tagging of the status changes is accomplished with the aid of the on-caclock. The clock has a one-minute range, a resolution of 1/8 millisecond for Groand 1 msec. for Group2, and an accuracy of+0.01 percent. The clock can besynchronized by a “Group DIOB Write.”

The frequency of the synchronization is controlled by the DIOB controller andshould occur at least once per second.

Figure 3-248. QSE Block Diagram

DataInterface

AddressDecoder

MaskStatusCurr. Inp

Reg

Buffer#1

Buffer#2

2: 1MUX

DigitalDebouncer

DEMUX

Oscillator

RealTimeClock

EventsStorageMemory

On-CardIsolated

Power Sply.+10VDC

+48VDC16 OpticalIsolators

and SignalConditioners

P07

DIOB Bus

Data Address Control

0 8...

0 15...

0 15...RTN

ControlLogic

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retainsent

bit.tr ofmthe

he

ures:

p2.

To facilitate QSE-DIOB controller communication, status and control words aused. The status register can be read by the DIOB controller at any time. It conthe Enable Stack Operation (freeze) bit (Bit 7), QSE Card OK bit (Bit 6), the EvBuffer Overflow bit (Bit 5) and the Number of Events in Buffer field (Bits 0-4).Bit 4 in this field indicates that the Event Buffer is full.

The control word is used to set or reset the Enable Stack Operation (freeze) When the “freeze” bit is set, new events will be entered into the second EvenBuffer. The status word is read by the DIOB controller to determine the numbeevents (N) in the first Event Buffer. The DIOB controller performs 2N reads frothe Event Stack location to collect all entries. (Event Buffer and Event Stack aresame.)

After the Event Buffer is read, the control word is used to reset the “freeze” bit. Tfirst Event Buffer is now reset and is available for storing new events.

3-38.2. Features

The QSE card is available in groups (G01 and G02) and has the following feat

• DIOB-compatible, single card sequence of events subsystem.

• Sixteen inputs that also can be read directly.

• On-card 48 V contact-wetting supply.

• IEEE surge withstand capability.

• 500 VDC isolation from DIOB.

• Optical coupling.

• Optical isolation for each input.

• Mask register for flexible sequence of event recording.

• Dual event storage memory.

• LED power supply operating indicators.

• Resolution event recording of 1/8 msec. for Group 1 and 1 msec. for Grou

• On-card one-minute range synchronizable clock.

• Recognize, mark and inhibit chattering inputs (Group 2 only)

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3-38. QSE

3-38.3. Specifications

Contact-Wetting Voltage Supplied by QSE

All inputs are optically isolated.

Minimum Nominal Maximum

Open Circuit Voltage (Volts) 42 48 56

Closed Contact Current (mA) 7 14 21

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3-38. QSE

4).

Input Requirements

Field Cable and Contact:

Input Signal Rejection

Power Supply

Electrical Environment

IEEE surge withstand capability (Ref. IEEE 472-1974) (Ref. ANSI C37.902-197500 VDC or peak AC between input command and DIOB ground.

Minimum Nominal Maximum

Leakage Resistance (KΩ) 50 -- --

Group 1 Propagation Delay (msec.) 3.5 4 4.5

Group 2 Propagation Delay (msec.) 3 -- 4

Group 1 Input Signal Duration Group 2 Input Signal Duration

Always Rejected < 3.5 msec. < 3.0 msec.

Always Passed > 4.5 msec. > 4.0 msec.

Minimum Nominal Maximum

Primary Voltage 12.4 V 13.0 V 13.1 V

Optional Backup 12.4 V -- 13.1 V

Current -- 1 A --

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3-38. QSE

unt

ltageumed by

y theust be

d totact’s

Cabling Limitations

Since up to 1.2 mA could flow through any open contact shunt resistance (RS), fromthe+48 volt supply (with open contacts, no current can flow from the+10 voltagesupply due to reverse biased diodes), 50K ohms is required as a minimum shresistance in order to maintain the high level contact-wetting voltage. As anexample, if the open contact shunt resistance was 25K ohms, the nominal vopresent across the open contacts would only be 25 volts. However, the minimopen contact shunt resistance that would permit open contacts to be recognizthe QSE card as open contacts is 10K ohms.

In order to ensure that closed contacts will always be recognized as closed bQSE card, the sum total of the contact series resistance and cable resistance mless that 60 ohms. SeeFigure 3-249.

Table 3-132 shows cable length limitations.

Contact Cycle Time

If the maximum QSE on-card generated contact-wetting voltage is to be applieplant contacts that interface to the QSE card, the elapsed time between the conopening and its subsequent closure must be greater than 15 msec.

Table 3-132. Maximum Cable Lengths (Assume R C = 0) for QSE Card

Cable Wire GaugeFor 16 Commons/Card (RR = 0)Length given is the distance from

contacts to termination

For 1 Common/Card Lengthof return = length of cables

to contacts

12 AWG 15,000 feet 1,800 feet

14 AWG 10,000 feet 1,200 feet

16 AWG 6,000 feet 700 feet

18 AWG 4,000 feet 500 feet

20 AWG 2,500 feet 300 feet

22 AWG 1,500 feet 200 feet

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Event Buffer Capacity

Two Event Buffers are used, each having a capacity of 32 16-bit words. Since eevent requires two 16-bit words, the total capacity of the two buffers is 32 eve

Resolution

Event time tagging resolution is 1/8 msec. for Group 1, and 1 msec. for Grou

Accuracy

One millisecond, relative to synchronizing.

Figure 3-249. Contact Wiring

RS = OPEN CONTACT SHUNT RESISTANCE

RC = CLOSED CONTACT SERIES RESISTANCE

RR = RESISTANCE OF THE COMMON RETURN LINE (IF ANY)

RLINE = RESISTANCE OF NON-COMMON LINE LENGTH TO AND FROM CONTACTS

FROMOTHER

CONTACTS

COMMON

ONE OF SIXTEEN

RS

RC

CONTACT

QSE CONTACTINPUTS

RR

RLINE

FOR A CLOSED CONTACT: RC + RLINE + 16RR < 60 OHMS

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Rate of Input Change Monitor (Group 2 Only)

In order to recognize “Chattering”, the Group 2 QSE card has an additional coufor each input channel to accumulate the number of changes, and a common coto measure the time interval (Ti).

Every time the input is scanned, the corresponding mask bit is tested. If the mbit is 0, then the Chattering Flag and Chattering Counter assigned to the inpureset. Monitoring for chatter starts when the mask bit is set to one.

At the time of an input change, the corresponding input counter is checked focount of four. If the counter is set to four, the Chattering Flag is set and the chais entered into the Event Register with Bit 7 in the Point ID set to a 1. If thecorresponding input counter is less than four, it is incremented and the changentered to the Event Register. No entry is made to the Event Register if theChattering Flag (corresponding to the input channel) is set.

At the end of each time interval (Ti), all the input counters are decremented by oncount. When an input counter reaches the zero count, the corresponding ChatFlag is reset allowing future changes to enter the Event Register. The input couwill not “underflow” or exceed the count of four.

Time Interval (T i)

Ti = 100 msec.

Input rates higher than 1/Ti will set the Chattering Flag. Rates lower than 1/Ti willreset it.

3-38.4. Signal Interface

DIOB Interface

The QSE card is interfaced to the DIOB via the QSE’s pin J1 connector. SeeTable3-133 for a list of the DIOB signals used by the QSE card.

Table 3-133. QSE J1 Connector DIOB Pin Out

Solder Side Signals Card-Edge Pins Component Side Signals

PRIMARY 1 2 PRIMARY

BACKUP 3 4 BACKUP

GROUND 5 6 GROUND

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When the card is addressed by the DIOB controller (read cycles only) and the Dcontrol signal “Data Gate” is received, the QSE card will activate the“Device-Busy” DIOB signal line. The appearance of the “Device-Busy” signalindicates to the DIOB controller that the QSE is on the DIOB and is powered upthe “Device Busy” pulse is missing, the DIOB controller can assume that therno point card capable of recognizing that particular DIOB address.

Card address assignment is accomplished via the front-edge 56-pin J2 conneSeeTable 3-134 for the signal list.

UADD 0 7 8 UADD 1

UADD 2 9 10 UADD 3

UADD 4 11 12 UADD 5

UADD 6 13 14 UADD 7

HI-LO/ 15 16 R/W1

UNIT 17 18 DATA-GATE

GROUND 19 20 DEV-BUSY

UDAT 0 21 22 UDAT 1

USAT 2 23 24 UDAT 3

UDAT4 25 26 UDAT 5

USAT6 27 28 UDAT 7

GROUND 29 30 *

* 31 32 *

33 34 GROUND

*These pins are open. The QSE card does not interface to the following DIOB sigUFLAG UCAL USYNC UCLOCK

Table 3-134. QSE J2 Connector Pin Out for Address Jumpers

Signal Card Edge Pin Number

CA7 28B

CA6 27B

CA5 26B

CA4 25B

Table 3-133. QSE J1 Connector DIOB Pin Out (Cont’d)

Solder Side Signals Card-Edge Pins Component Side Signals

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Contact Inputs

The 16 QSE card contact inputs are interfaced to the field contact via the 56-pinfront-edge connector. Each contact input is single-ended and shares a commreturn connection with the other contact inputs. Since the QSE has an internagenerated, isolated dual voltage supply, there is no need for an externalcontact-wetting voltage supply. Each contact can thus be wired directly betweeQSE card’s field common pin and one of the sixteen contact input pints. SeeTable3-135 for the J2 connector signal pin out.

3-38.5. Circuit Description

A functional block diagram of the QSE card is shown inFigure 3-248.

Power-Up

The power-up circuit performs the following functions:

• Maintains reset as long as the power supply is below 9 volts.

• Extends the reset for a nominal 250 msec. for Group 1 and 2 seconds for G2 after the power supply is above 9 volts.

• After the reset is terminated it, provides a delay of 125 msec. for Group 1 ansecond for Group 2 before it enables the setting of the status bit ST6. Duringdelay, the on-board microcontroller completes over a thousand cycles,providing stable data before the status bit ST6 is set. Thus, status bit ST6indicates both power-up and “card ok” conditions.

CA3 24B

CA2 23B

CA1 22B

CA0 21B

Hi/Lo (Address Protect) 20B

Logic Common 21A-28A

Table 3-134. QSE J2 Connector Pin Out for Address Jumpers

Signal Card Edge Pin Number

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• Continuously monitors the processor cycle time and clears the status bit STthe cycle is shorter than 100µsec.for Group 1 and 700µsec for Group 2, orlonger than 150µsec. for Group 1 and 1700µsec for Group 2. To perform this“Watchdog timer” function, the power-up circuit timing is independent of thprocessor clock.

Reset

During reset, the following circuits are cleared:

• Real time clock. The clock begins at “0” time after the reset is terminated.

• Memory load latch.

• All mask-bits are set to “one.” This enables entries to the Event Buffer whenchange of state of any input bits is recognized.

• The Event Buffer is cleared of all entries.

• The processor is reset.

• The contact-wetting voltage supply is shut down.

Input Circuit

The card handles 16 contact inputs with common return. The input signals ardigitally filtered (debounced). Contact closure produces a “1” at the DIOB, whan open contact produces a “0.” For field input connector pin out, seeTable 3-135.

Table 3-135. QSE J2 Connector Pin Out for Field Inputs

Contact Input Bit Number Card Edge Pin Number

DB15 17B

DB14 17A

DB13 15B

DB12 15A

DB11 13B

DB10 13A

DB9 11B

DB8 11A

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DIOB Control

The card is addressed by means of the six most significant DIOB address lin(UADD7-UADD2). This address is referred to as “Base Address.”

The Base Address is selected by jumpers at the top of the front card-edge connInsertion of a jumper encodes a “one” on that address line, absence of a jumencodes a “zero.” When this pattern of jumpers matches that on the bus, the carbeen selected by the bus controller.

Because the DIOB has eight data lines, the HI/LO line of the DIOB is used todetermine whether the high or the low half of the 16-bit data word is to betransferred.

Data protection during the removal of the front connector is implemented via a sfront-edge pin in the location of the HI/LO jumper (front connector Pins 20A-20

Note

The jumper must be installed.

DB7 9B

DB6 9A

DB5 7B

DB4 7A

DB3 5B

DB2 5A

DB1 3B

DB0 3A

COMMON 1A and 1B

Notes

1. B = Component SideA = Solder Side

2. Pins 19A and 19B are internally tied together on the QSE Card.

Table 3-135. QSE J2 Connector Pin Out for Field Inputs

Contact Input Bit Number Card Edge Pin Number

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If the connector is removed, this contact opens first and removes the card froDIOB address. This allows use of the full DIOB address while allowing removand insertion of the cards in an operating DIOB. However, this feature does nallow these cards in the lower half of the DIOB address while using cards withshort A7 pin type address protection in the DIOB upper half address.

The two least significant DIOB address lines are used as described in the followsections.

Current Input (UADD0 = “zero”, UADD1 = “zero”)

This word can be read any time. Each bit indicates the state of the corresponinput as shown inTable 3-136.

Table 3-136. QSE Current Input

Input Bit Number J2 Card Edge PinNumber DIOB Data Lines DIOB HI/LO

DB15 17B UDAT7 “one”

DB14 17A UDAT6 “one”

DB13 15B UDAT5 “one”

DB12 15A UDAT4 “one”

DB11 13B UDAT3 “one”

DB10 13A UDAT2 “one”

DB9 11B UDAT1 “one”

DB8 11A UDAT0 “one”

DB7 9B UDAT7 “zero”

DB6 9A UDAT6 “zero”

DB5 7B UDAT5 “zero”

DB4 7A UDAT4 “zero”

DB3 5B UDAT3 “zero”

DB2 5A UDAT2 “zero”

DB1 3B UDAT1 “zero”

DB0 3A UDAT0 “zero”

Note

The “Current Input” word is unaffected by the “Mask” word.

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QSE Mask (UADD0 = “one,” UADD1 = “zero”)

The word determines which bits are checked for change of state to cause entrthe Event Buffer (SeeTable 3-137). This word can be both read and written. A“one” in any bit position causes the corresponding input to be checked for chof state every 125µsec. for Group 1 and 1msec. for Group 2, and, in case of chaof state, to enter the change (with corresponding time) to the Event Buffer.

For Group 2 QSE cards, a zero in any bit position of the Mask Word resets thcorresponding Chattering Counter and Chattering Flag in order to disablemonitoring for chatter. Monitoring will start at the time the mask bit is set to 1.

Upon power-up, all QSE Mask bits are set to “one.”

Table 3-137. QSE Status Word Bit Assignment

QSE Mask Bit DIOB Data Lines DIOB HI/LO

MB15 UDAT7 “one”

MB14 UDAT6 “one”

MB13 UDAT5 “one”

MB12 UDAT4 “one”

MB11 UDAT3 “one”

MB10 UDAT2 “one”

MB9 UDAT1 “one”

MB8 UDAT0 “one”

MB7 UDAT7 “zero”

MB6 UDAT6 “zero”

MB5 UDAT5 “zero”

MB4 UDAT4 “zero”

MB3 UDAT3 “zero”

MB2 UDAT2 “zero”

MB1 UDAT1 “zero”

MB0 UDAT0 “zero”

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Status Word (UADD0 = “one,” UADD1 = “one”)

The Status word indicates the condition of the QSE Card (power is up, watchtimer is OK), and the status of the Event Buffer. The two bytes of the Status W(HI/LO) are identical; thus, a byte read operation is sufficient to obtain statusinformation.

Table 3-138 lists the assignment of the bits within the Status Word:

The “freeze” bit (ST7 = “one”) indicates that the “Enable Stack Operation” wainitiated by the DIOB controller. The Card OK flag (ST6 = “one”) means that tcard is operating. Buffer overflow (ST5 = “one”) warns that no more entries arallowed to either buffer; thus information may be lost.

Status bits ST0 to ST4 are meaningful only after the DIOB controller initiates “Enable Stack Operation” (ST7 is set on “one”). Under this condition, bits ST0ST4 indicate the number of events entered to the buffer prior to when it was froBit ST4 = “one” if the buffer is full.

Control Word (UADD0 = “one,” UADD1 = “one”)

The control word is used by the DIOB controller to enable stack operations, anreset the Event Buffers.

The following procedure is used to empty (read) Event Buffer.

Table 3-138. QSE Status Word Bit Assignment

DIOB Data Line Status Bit Number Function

UDAT7 ST7 Freeze bit

UDAT6 ST6 Card “OK” flag

UDAT5 ST5 Buffer overflow

Number of events in theBuffer (ST 4 = “one” meansBuffer-full).

UDAT4 ST4

UDAT3 ST3

UDAT2 ST2

UDAT1 ST1

UDAT0 ST0

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1. The DIOB controller sets the Enable Stack Operation (freeze) bit to “one”writing a word (with the most significant bit = “one”) to the card’s“BaseAddress” + 3. (Only the most significant bit is used in the control word; theother bits can be in any state.)

2. The status word (byte) is read next, so that the number of entries (N) to the EBuffer can be determined.

3. The DIOB controller now reads 2N words from the card’s“Base Address” + 2in order to collect all information.

4. To eliminate the stack operation (unfreeze), the DIOB controller clears thefreeze bit by writing a word (with the most significant bit = “zero”) to the card“Base Address” + 3. This action also clears the Event Buffer (the one just refrom) so that it is free to record new events.

5. The DIOB controller repeats the freeze/status read procedure to check foentries to the second buffer. If additional entries are detected, then the reaunfreeze operations are repeated. With no entries, only the unfreeze (reseprocedure is required.

Events Buffer (UADD0 = “zero,” UADD1 = “one”)

The word is active only when the Enable Stack Operation (freeze) bit is set to “oOtherwise, read operations return all zero data words. Write operations are notwith this address.

If the Enable Stack Operation (freeze) bit = “one,” then the reads from this add(Card Base Address+ 2) are treated as pop operations from the Event Buffer sta

In case the number of reads exceeds 2N words (where N = the number of entrthe Event Buffer at the time of the freeze command), all zero data words arereturned.

Entries to the Event Buffer

All 16 field-input bits are sampled every 125µsec. for Group 1 and 1msec. forGroup 2 to detect change of states. If a change is detected for 32 continuous sacycles (4 msec.) for Group 1 or 4 continuous sample cycles for Group 2, thenmask bit (that corresponds to the bit that registered the change) is tested. Foregistered change that has the corresponding mask bit set, an entry is made Event Buffer.

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For Group 2 QSE cards additional tests are made to determine if the new chacauses a chattering condition. If it does the change is entered with the ChatteFlag set. If the chattering condition already exists, then no entry is made to thEvents Buffer.

An entry consists of two 16-bit words. The first word is referred to as the PointThe bit assignment of the Point ID is shown inTable3-139. The second half of theentry is the 16-bit representation of the time-tag (LSB = 1 msec.).

Event Buffer Stack

Each Event Buffer has a capacity of 16 entries (32 15-bit words). Event 1 is thechange of state (oldest event) since the buffer was last emptied. The first readlocation Base Address+ 2 returns Event 1 Point ID. The next read from the samlocation returns Event 1 Time-Tag. This sequence continues for 2N reads requto empty the buffer stack through location Base Address+ 2.

Table 3-139. QSE Point ID Bit Assignment

Bit Position Description

15 New Point Value

14 Always “one”

13 Always “zero”

12 Always “zero”

10 Always “zero”

9 Always “zero”

8 Always “zero”

7 Always “zero” for Group 1, Chattering Flag for Group 2.

6 Time Tag extension bits, used to provide 1/8 msec. resolution

(LSB [Bit Position 4] = 1/8 msec.) for Group 1. Always “zero” for Group 25

4

3 Bit Identification Code. Binary representation of the bit causing the entry

(MSB = Bit 3, LSB = Bit 0)2

1

0

Event 1 Point ID

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Clock Synchronizing

Clock synchronizing is accomplished by periodic DIOB write operations. Onefour Group Write Addresses can be selected by jumpers J1 and J2 (see “GroWrite Address Selection Jumpers”).

Double byte transfer (word transfer) should be used on the DIOB, low byte firhigh byte second. The QSE clock is synchronized when the high byte is transfeIf the two writes (bytes) are more than 200µsec apart, the QSE aborts thesynchronization attempt.

3-38.6. Firmware Considerations

The 8031 microcontroller is used to perform the following functions:

• Sample the status information from the isolated contact inputs, and compato the previous state of inputs called “Current Input” (Current Input is storedthe 8031’s internal registers and cleared during reset). The result is stored“alarm bits” in internal registers.

• Increment the corresponding counter(s) for each alarm bit. (The 8031’s interegisters are used as counters.)

• Reset all the counters that have no corresponding alarm bits set.

• Test each counter for a terminal count (32 for Group 1 and 4 for Group 2)

• Reset the corresponding alarm bits for each counter that did not reach theterminal count.

• Calculate the new “Current Input” based on “surviving” alarm bits and the o“Current Input.”

Event 1 Time-Tag

Event 2 Point ID

Event 2 Time-Tag

Event 3 Point ID

Event 3 Time-Tag

Event N Point ID

Event N Time-Tag

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• Output new “Current Input” to registers that can be read by the DIOB contro

• Repeat the cycle.

In order for the debounce algorithm to be accomplished within the time restrictin Group 1 QSE cards, the code is written in-line (no loops). In addition, thecode-map is segregated to two separate areas. The program executes from themap area until it detects an alarm bit, then jumps to the “high” map area toincrement and test the corresponding counter. If the test indicates that the coreaches the terminal count, the program jumps back to the “low” map area, rethe counter, and proceeds to test the next alarm bit. If the counter did not reaterminal count, the program will stay in the “high” area, reset the alarm bit jusprocessed, and test the next alarm bit.

The program is written so that it completes the processing of each bit in exactlysame time, regardless of the jumps. Thus, the area from which the program iexecuted indicates the bit being processed and the result.

An additional “shadow PROM” is used to generate “marker” bits to translate tcode address for the control logic.

This approach enables the 8031 to complete each cycle in exactly 125µsec, and withthe shadow PROM supplying the pulses to advance the QSE’s real time clock, tis no contention between events recording, and the advancing of the real-time c

For the Group 2 QSE card, the firmware was written in a more conventional fin order to fit the code into the 512x8 PROM. The sampling rate was loweredKHz. in order to accomplish the additional algorithms. These algorithms recognthe chattering condition, mark the Event Buffer entry using the Chattering Flagprevent additional entries to the Event Buffer while the chattering condition exiIn order to minimize hardware changes, The Group 2 firmware also uses the“Shadow PROM” to communicate the changes to the control logic that is exteto the microcontroller.

Event Memory Arbitration Timing Clock

The Event Memory is accessed by both the microcontroller (to record new eveand the DIOB controller (to read the recorded data).

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To avoid contention, arbitration logic is used. The principal signals are shownFigure 3-250. The designators T1 through T12 refer to the microcontroller’soscillation periods (states).

The CLOCK is generated by a precision oscillator and used by the microcontroThe CLOCK’s frequency is 12 MHz.

The ALE and PSEN/ are generated by the microcontroller and used to strobeaddresses and enable external program memory.

The PSEN.DLD is generated by delaying the inverted PSEN/ signal.

ADD.OK is derived from the DIOB address and control signals, and it isasynchronous, relative to the timing of the microcontroller. The signal SY1 isgenerated, using two flip-flops as synchronizers (U56-A and U56-B); to replacestrobe (STR) that is normally used to access the Event Buffer by the on-cardmicrocontroller. The signal MUC is also generated to control the memory addmultiplexer in advance of the strobe SY1.

In Figure3-250 the timing of the signal ADD.OK is such that it just missed settinthe synchronizers; thus, synchronization is delayed by a full cycle of the signaPSEN.DLD.

Under this worst-case condition, the data will be strobed to the DIOB in less t625 nsec after the DIOB signal “Data Gate” is valid.

Figure 3-250. QSE Event Buffer Memory Arbitration Timing Chart

T1 T12 T1 T12 T1

CLOCK

ALE

PSEN/

PSEN.DLD

ADD.OK

U63-A

U63-B

MUC

SY1

STR

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3-38.7. Controls and Indicators

Figure 3-251 shows the LED card components.

Light Emitting Diodes

When lit, the Power LED indicates the card is receiving DIOB power.When lit, the I/O Power LED indicates the card is generating+10 VDC and48 VDC.

3-38.8. Card Addressing

Group Write Address Selection Jumpers

One of the four group write words (16 bit wide) can be selected with the aid of fjumpers.

Addressing

The QSE card occupies four DIOB addresses. These addresses are described

Figure 3-251. QSE LED Card Components

Jumper Inserted Group Write Word Selected

J1 J3 FC

J2 J3 FD

J1 J4 FE

J2 J4 FF

Power LED

I/O Power LED

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• The first DIOB address is used for reading the current input word, which canread at any time. Each bit of the current input word indicates the state of tcorresponding input. The mask word has no effect on the current input wo

• The second DIOB address is used to set/reset the bits in the mask word. mask word determines which inputs are checked for changes of state, ancauses entries in the event buffer. All bits in the mask word are set to 1 uppower-up.

• The third DIOB address is used for reading the event data from the event sbuffer. This word is only active when the enable stack operation bit (describbelow) is set to 1 (FREEZE). Otherwise, it returns to 0000 when read.

• The event data read through this DIOB address is treated as a “POP” operfrom the event stack buffer. As noted previously, each event is made up o2 words of information (seeFigure 3-252).

• The fourth DIOB address is used to set/reset (FREEZE/UNFREEZE) the enstack operation bit, and to read the status (byte) (seeFigure3-253). The state ofthe bits on the following page can be read at any time:

— Enable stack operation— QSE card OK— Buffer overflow— Buffer fullThe number of events in the event stack buffer can be read only when the enstack operation bit is set (FREEZE).

Figure 3-252. QSE Event Data Format

D

F E D C B A 9 8 7 6 5 4 3 2 1 0

1/8 DIV BIT POSITION

TIME TAG IN msec. (0 TO EA60H)

D = DIGITAL VALUETIME TAG IN 1/8 msec. (RANGE 0 TO 7)BIT POSITION OF DIGITAL VALUE IN THE CURRENT INPUT WORDNUMBER OF msec. (RANGE 0 TO 60000)

===

1/8 DIVBIT POSITION

TIME TAG IN msec.

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3-38.9. Application Information

The QSE card is one element of the WDPF Sequence of Events (SOE) subsywhich provides a means of determining the order in which a set of preselectecontact inputs change state.

In addition to the QSE, the SOE subsystem contains the following elements:

• DPU software to synchronize the QSE with the Data Highway clock, scanQSE for events, buffer the events, and send General Purpose Messages or two designated drops

• Logger, HSR, or HDR software to process event messages (from multipleDPUs), sort the events by time, and print them in chronological order

The resolution of the SOE is 1/8 msec. (within a single DPU). In an SOE subsyswith multiple DPUs, the overall accuracy (between drops) is calculated to be bethan 1.5 msec.

Figure 3-253. QSE Status Byte Format

7 6 5 4 3 2 1 0

ENABLE STACK OPERATIONS BIT

NO. OF EVENTS

(SET = FREEZE, RESET = UNFREEZE)

QSE OK BIT (WHEN SET, INDICATESNORMAL OPERATION)

BUFFER OVERFLOW BIT (WHEN SET, INDICATESTHAT THERE ARE 32 EVENTS ENTERED INTO THEQSE CARD)

BUFFER FULL BIT (WHEN SET, INDICATES THATTHE CURRENTLY USED BUFFER CONTAINS 16EVENTS)

NUMBER OF EVENTS (0 TO 15)

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QSE Capacity

The QSE performs a high-speed scan of its 16 digital inputs, storing event daone of its dual event stack buffers. This dual buffer allows accumulated events tread from one event stack, while the other continues to accept event data as occurs. Each event stack buffer has a 32 word capacity. Since each event req2 words, the total combined capacity of the event buffers is 32 events. When maximum is exceeded, an overflow condition occurs and the card stops colleinformation.

Input Conditioning

The QSE card includes a digital filter for each input, which is used to reject sigchanges within a predetermined time interval (3.5 to 4.5 msec.).

Time Tagging

Time tagging of status changes is accomplished using the QSE clock. This cloca 1 minute range, resolution of 1/8 msec., and accuracy of+ 0.01%. To determinethe relative real time of the events to the system, this onboard clock can besynchronized by a group DIOB offset (1FEH).

DPU Configuration

The user can configure a DPU to monitor up to 576 SOE points; these pointscorrespond to a maximum of 36 QSE cards, each with 16 inputs. For the DPUcollect event information, the user must do the following:

• Connect the appropriate field input signals to the QSE cards.

• Initialize the appropriate process point record fields. In general, the SOE powill be initialized as standard digital inputs (DI type), with the followingexceptions:

— The EQ record field must be set to 1.

— The HW field must be a multiple of 8H (allowing four DIOB word addresseper QSE).

— Optionally, the user may specify a value for the RL field (relay close deltime). Each event read from the QSE card will have this value (in msecsubtracted from the reported time before it is sent to the Logger.

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• Initialize the drop number(s) of the drop(s) to receive SOE data from the D(using the DPU configuration diagram).

Operation

At restart, a DPU configured for SOE handling searches through all DI recordsthe SOE points, and builds a table which it will use to expedite event recording.DPU’s functional processor then resets each QSE card, and subsequently wrvalue to each card (mask) that indicates which of the QSE’s 16 inputs are to bmonitored for SOE.

Note

QSE input points which are not eventmonitored may be used as ordinary contact ordigital input points.

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3-38. QSE

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Each time the functional processor executes its overall loop, it synchronizes tQSE cards with the real time from the Data Highway Controller clock. In additioduring each scan, the DPU functional processor does the following:

• Checks the number of events contained in both event stack buffers on eachcard. If the number is greater than 0, the event data is read and temporarstored in RAM (until it can be sent to the designated drop(s)).

• Checks for buffer overflow condition (Buffer Overflow bit set) and verifiescorrect operation of the QSE card (QSE OK bit set, and Enable Stack Operabit set/reset properly). If QSE hardware failure is detected, the card’s inpupoints are put into alarm. (When the card is repaired or replaced, the DPUautomatically initialize the new card, reset the mask bit, and remove the pofrom alarm.)

Note

Removing a point from digital input scan willalso remove it from SOE scan.

Once the event data is recorded into the DPU’s RAM buffer, it is sent to theuser-specified drop (or drops). Typically, the target drop will be a Logger, whichthe capability of receiving, sorting, and printing SOE data from multiple DPUs

If one target drop is specified by the user, the DPU will send the event data todrop one message at a time. That is, each message requires the receiving dracknowledge, before the DPU will send the next one. If the target drop fails toacknowledge a message, the DPU will periodically repeat the message, untiltarget drop responds. If the target drop continues to fail to respond, the DPU continue to collect data until the RAM buffer is full. Once the RAM buffer is funew events will not be saved. Note that if the target drop fails, the RAM buffer wcontinue to fill and can contain a minimum of 790 events.

If two target drops are specified, the DPU will send the event messages to both dsimultaneously.

Each message requires the receiver to acknowledge it within a pre-determineperiod of time. If neither drop acknowledged its message, the DPU will periodicare-transmit the same message to both drops until at least one of them respononly one drop responds, the DPU will re-attempt the message to the non-respondrop, up to three times. If this fails, the non-responding drop will be considere“dead.” Subsequent messages will still be sent to both target drops; however,DPU will not repeat the messages to the “dead” drop. Once the “dead” dropacknowledges a message, it will be considered “alive”, and the DPU will once agattempt to re-transmit any unacknowledged messages.

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3-38.10. SOE Event and Error Messages

When certain error conditions occur, an error message will be sent to the designdrop(s). The SOE error messages are listed below:

• QSE BUFFER OVERFLOW – Indicates that the number of events stored onQSE card has reached 32. When this occurs, any additional events (exce32) will be lost. The oldest 32 events will be saved.

• DPU DHC CLOCK DISABLE – Indicates that the Data Highway clock isdisabled, although the SOE is otherwise operational. Events entering the cards’ Event Stack Buffers will not be collected while this condition exists.

• DPU DHC CLOCK ENABLE – Indicates that the Data highway clock isre-enabled after a disabled condition. When the clock is re-enabled, the Dresets all the QSE cards and sets their masks. The DPU’s RAM event bufinitialized, and the status of the target drop(s) is set to “alive”.

• DPU SOE RAM BUFFER FILLED – Indicates that the DPU’s RAM eventbuffer is full. In this case, all events (in all QSEs’ FROZEN Event StackBuffers) are slowly dumped into the DPU’s RAM buffer, as event messagessent to the remote drops (creating space in the buffer). Any event data entethe second (UNFROZEN) Event Stack Buffers (in all QSE cards) will beconsidered bad data, and will not be collected, because the base time wilhave been updated.

• INITIALIZING SOE DATA BASE – Indicates that the SOE subsystem is beininitialized. This message will appear after restart and when a redundant DPswitched from Backup to Control mode.

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3-38. QSE

3-38.11. Installation Data Sheet

1 of 2

Figure 3-254. QSE Wiring Diagram

+10VDC

OPTO ISO

OPTO ISO

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

CARD

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

HALF SHELL EXTENSION(B-BLOCK)

EDGE-CONNECTORCUSTOMER CONNECTIONS INTERNAL

BUS STRIP

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

BIT 8

BIT 9

BIT 10

BIT 11

BIT 12

BIT 13

BIT 14

BIT 15

BIT 0

+V

+V

REQUIRED ENABLE JUMPER

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3-38. QSE

For CE MARK Certified System

2 of 2

Figure 3-255. QSE CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 15

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

B

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

CUSTOMER CONNECTIONS

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3-39. QSR

Servo Driver with Positional Readback(Stlye 3A99101G01 through G04)

3-39.1. Description

G01 through G04 (Must be revision L or later) are applicable for use in the CE MARKCertified System

The Q-Line Servo Driver with Position Readback (QSR) card is a valve positicontroller I/O card that interfaces to the WDPF DPU through the DIOB in ordercontrol Electro-Hydraulic (EH) actuators in the field. Group 1 and 3 boards hafour channels and control up to four DC actuators. The only difference betwegroups 1 and 3 is that the DPU demand and readback codes are inverted. The2 and 4 boards have two channels and control up to two AC actuators. The odifference between groups 2 and 4 is that the DPU demand and readback codinverted. The QSR is similar in function to the Q-Line Servo Driver Card (QSD) bhas independent outputs and provides more features. Some features are DPreadback of the valve position for each channel, valve shutdown options, autocalibration of the channels, and electrically isolated channels.

A microcontroller provides the interface function between the DIOB and thechannels. It also handles the auto-calibration function for the card.

The demand Digital to Analog (D/A) converter in each channel of the QSR caconverts a 12 bit binary number (the demand code from the DPU) into a desiposition analog signal. This signal is summed with an Linear Variable DifferenTransformer (LVDT) feedback signal to produce an error signal. A gain D/Aconverter located in each channel scales the channel's feedback voltage befosummed with the demand signal. The output signal which drives the actuatordetermined by applying proportional plus integral (analog) control action to therror between the desired demand and actual feedback values of the actuatoposition. The actuator position is determined by an LVDT at the actuator.

To monitor the feedback or position voltage of the actuator, a 12 bit valuerepresenting the actuator position from the LVDT is available for readback byDPU for each channel. This allows the DPU to digitally compare the actual posiwith the desired output position.

The valve shutdown function on the QSR is used to either fully open or fully clothe actuators (independent of the position feedback or the demand output). Echannel has a jumper to select an overdriven positive or overdriven negative oucoil drive level during shutdown. This drives the actuator to its fully open or closstate. Shutdown is activated by command from the DPU (one channel at a timea card reset, or by a watchdog timer timeout.

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3-39.2. Features

The QSR card provides the following features:

• Channel shutdown capability.

• Configurable valve coil drive levels.

• Electrical isolation between channels and between field and digital controcircuitry.

• High impedance differential inputs for feedback.

• Diode protected feedback inputs.

• Position readback of AC and DC feedback voltage.

• Selectable magnitude (+15V or+16V) bipolar DC LVDT power supply (Group1 and 3 only).

• Resistor programmable 1kHZ or 3kHZ modulated LVDT power supply (Gro2 and 4 only).

• Microprocessor and hardware watchdog timers.

3-39.3. Specifications

Channel Valve Types

A QSR channel may be configured to drive 1 of 3 valve types which include bipounipolar1, and unipolar2. To configure a channel for a specific valve type, instalValve Type Select jumper and Bipolar Select Resistor (RBP) as follows:

1. Bipolar: Valve Type Select jumper set to N-normal position and RBP iinstalled.

2. Unipolar1: Valve Type Select jumper set to N-normal position and RBP iNOT installed.

3. Unipolar2: Valve Type Select jumper set to I-inverted position and RBP iDON'T CARE.

SeeFigure 3-260 andTable 3-145 throughTable 3-148 for location of RBP andValve Type Select jumper for each channel of the QSR.

The four QSR groups define bipolar, unipolar1, and unipolar2 as follows:

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Group 1 - DC LVDT

Unipolar1 DPU Demand: 0% = negative coil drive output; 100% = positive cdrive outputLVDT Feedback: 0VDC = 100%; -10VDC = 0%NOTE: Invert leads of the LVDT feedback so feedback range is 0VDto -10VDC

Unipolar2 DPU Demand: 0% = positive coil drive output; 100% = negative cdrive outputLVDT Feedback: 0VDC = 100%; +10VDC = 0%NOTE: Do NOT invert leads of the LVDT feedback.

Bipolar DPU Demand: 0% = negative coil drive output; 100% = positive cdrive outputLVDT Feedback: -10VDC = 0%; +10VDC = 100%NOTE: Adjust feedback leads so above feedback polarities are tru

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Group 2 - AC LVDT

Group 3 - DC LVDT

Group 4 - AC LVDT

Unipolar1 DPU Demand: 0% = negative coil drive output; 100% = positive cdrive outputLVDT Feedback: 0VAC = 100%;±10VAC = 0%NOTE: Connect LVDT feedback leads to feedback B of channel.

Unipolar2 DPU Demand: 0% = positive coil drive output; 100% = negative cdrive outputLVDT Feedback: 0VAC = 100%;±10VAC = 0%NOTE: Connect LVDT feedback leads to feedback A of channel.

Bipolar DPU Demand: 0% = negative coil drive output; 100% = positive cdrive outputLVDT Feedback:±10VAC on feedback A, 0VAC on feedback B =100%, ±10VAC on feedback B, 0VAC on feedback A = 0%NOTE: Adjust feedback leads so above feedback conditions are tr

Unipolar1 DPU Demand: 0% = positive coil drive output; 100% = negative cdrive outputLVDT Feedback: 0VDC = 0%;−10VDC = 100%NOTE: Invert leads of the LVDT feedback so feedback range is 0VDto -10VDC.

Unipolar2 DPU Demand: 0% = negative coil drive output; 100% = positive cdrive outputLVDT Feedback: 0VDC = 0%;+10VDC = 100%NOTE: Do NOT invert leads of the LVDT feedback.

Bipolar DPU Demand: 0% = positive coil drive output; 100% = negative cdrive outputLVDT Feedback:−10VDC = 100%, +10VDC = 0%NOTE: Adjust feedback leads so above feedback polarities are tru

Unipolar1 DPU Demand: 0% = positive coil drive output; 100% = negative cdrive outputLVDT Feedback: 0VAC = 0%;±10VAC = 100%NOTE: Connect LVDT feedback leads to feedback B of channel.

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Valve Coil Drive

QSR boards are assembled for±40mA into 40 ohms. The resistor which sets thiscurrent (Rout) is installed in spring sockets to allow other drive levels/loads (seFigure 3-260,Table 3-145, andTable 3-146 for location of Rout on board).Configurable drive levels are as follows:

Resolution: 11 BitAccuracy: 10 Bit

LVDT Position Feedback

Groups 1 and 3 - DC LVDT

Input Span: depends upon LVDT type and stroke.Unipolar LVDT Type:±1.5V to±15VBipolar LVDT Type:±1.5V to±10V

See Per Channel Jumper description underControlsand Indicators for necessaryLVDT Input Level Jumper positions which are dependent on the input span. SFigure 3-260 andTable 3-147 for location of LVDT Input Level Jumpers.

Input Impedance:Differential (with floating source): 400 KohmsInputs (tied together) to common: 150 Kohms

Unipolar2 DPU Demand: 0% = negative coil drive output; 100% = positive cdrive outputLVDT Feedback: 0VAC = 0%;±10VAC = 100%NOTE: Connect LVDT feedback leads to feedback A of channel.

Bipolar DPU Demand: 0% = positive coil drive output; 100% = negative cdrive outputLVDT Feedback:±10VAC on feedback A, 0VAC on feedback B = 0%,±10VAC on feedback B, 0VAC on feedback A = 100%NOTE: Adjust feedback leads so above feedback conditions are tr

Resistor Level Load

210 ohms ±40mA 40 ohms

100 ohms ±60mA 60 ohms

158 ohms ±40mA 80 ohms

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Common mode rejection: 55 dB with LVDT Input Level Jumpers in “<10V”position50 dB with LVDT Input Level Jumpers in “>10V”position

Inputs are diode protected against common mode and differential overvoltage

Resolution: 11 BitAccuracy: 9 Bit

Groups 2 and 4 - AC LVDT

SeeFigure 3-260 andTable 3-148 for location of LVDT Input Level Jumpers.

Signal Span:20Vp-p max

Common mode voltage:±10V max

Input Impedance:10K ohm with input floating

Common mode rejection: 55 dB with LVDT Input Level Jumpers in “<10V”position50 dB with LVDT Input Level Jumpers in “>10V”position

Voltage applied:±30V max

Resolution: 11 BitAccuracy: 9 Bit

3-39.4. LVDT Power Supply

Groups 1 and 3 - DC LVDT Supply

Adjustable: Jumper selectable per channel for +15V and -15V or +16V and -1outputs each at±5% tolerance, 30mA max. SeeFigure 3-260 andTable 3-147 forlocation of DC LVDT Supply Level Jumpers.

Average Change Over Temperature:±1% max from 0 to 60oCTracking accuracy:±1.5% max from 0 to 60oC

Groups 2 and 4 - AC LVDT Supply

Signal: Sine wave 2.8 to 3.3 kHz (May be set to 1.0 kHz - see AC LVDT DriResistors underControls and Indicators forlocation of resistor which set the frequency.)

Frequency Stability:1.5% ppm peroC

Amplitude:19Vp-p max±11%

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3-39. QSR

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Load resistance:500 ohm min

3-39.5. Power Requirements

DIOB supply voltage: +12.4 VDC to 13.1 VDC

Current (supplied by DIOB):1.0A typ 1.5A max - Groups 1 and 3

0.9A typ 1.4A max - Groups 2 and 4

3-39.6. Watchdog Timers

The Microprocessor watchdog timer puts all channels in shutdown mode if theboard microprocessor fails to service the QSR within 0.5 seconds.

The hardware watchdog timer causes the Alive LED to blink if the DPU has ncommunicated with the QSR within three seconds. If the Shutdown jumper JSenabled, a timeout will put all channels in shutdown.

3-39.7. Signal Interface

DIOB Connector

The QSR interfaces to the DIOB bus through a 34 pin card-edge connector oDIOB backplane. The card-edge DIOB signal assignments are given inTable 3-140 below.

Table 3-140. QSR DIOB Card Edge Connector Pinout

Signal NameComponent Side Pin # Pin #

Signal NameSolder Side

PRIMARY +V 2 1 PRIMARY +V

BACKUP +V 4 3 BACKUP +V

GROUND 6 5 GROUND

UADD1 8 7 UADD0

UADD3 10 9 UADD2

UADD5 12 11 UADD4

UADD7 14 13 UADD6

DATA-DIR 16 15 HI,LO

DATAGATE 18 17 No Connection

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3-39. QSR

sction

3-39.8. Field/Addressing Connector

The front card edge of the QSR card provides for both the card DIOB addresassignment and for the connections to the field devices. The field device connepoints are different for Group 1,3 cards and Group 2,4 cards as shown inTable 3-141 andTable 3-142.

DEVBUSY 20 19 GROUND

UDAT1 22 21 UDAT0

UDAT3 24 23 UDAT2

UDAT5 26 25 UDAT4

UDAT7 28 27 UDAT6

No Connection 30 29 Ground

No Connection 32 31 No Connection

Ground 34 33 No Connection

Table 3-141. Groups 1 and 3 (DC LVDT) Field/Addressing Front Card Edge Connector

Signal Name Component Side Pin # Pin # Signal Name Solder Side

ADD7 28B 28A +13V

ADD6 27B 27A +13V

ADD5 26B 26A +13V

ADD4 25B 25A +13V

ADD3 24B 24A +13V

Shield 23B 23A Shield

LVDT 2 (+)Feedback 22B 22A LVDT 4 (+)Feedback

LVDT 2 (-)Feedback 21B 21A LVDT 4 (-)Feedback

No connection 20B 20A No connection

Shield 19B 19A Shield

LVDT 2 (+)Supply 18B 18A LVDT 4 (+)Supply

LVDT 2 (-)Supply 17B 17A LVDT 4 (-)Supply

No connection 16B 16A No connection

Shield 15B 15A Shield

COIL DRIVE 2 14B 14A COIL DRIVE 4

GROUND 2 13B 13A GROUND 4

Table 3-140. QSR DIOB Card Edge Connector Pinout

Signal NameComponent Side Pin # Pin #

Signal NameSolder Side

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3-39. QSR

Note

LVDT (+) and (-) Supply signals arereferenced to channel ground.

No connection 12B 12A No connection

Shield 11B 11A Shield

LVDT 1 (+)Feedback 10B 10A LVDT 3 (+)Feedback

LVDT 1 (-)Feedback 9B 9A LVDT 3 (-)Feedback

No connection 8B 8A No connection

Shield 7B 7A Shield

LVDT 1 (+)Supply 6B 6A LVDT 3 (+)Supply

LVDT 1 (-)Supply 5B 5A LVDT 3 (-)Supply

No connection 4B 4A No connection

Shield 3B 3A Shield

COIL DRIVE 1 2B 2A COIL DRIVE 3

GROUND 1 1B 1A GROUND 3

Table 3-142. Groups 2 and 4 (AC LVDT) Field/Addressing Front Card Edge Connector

Signal Name Component Side Pin # Pin # Signal Name Solder Side

ADD7 28B 28A +13V

ADD6 27B 27A +13V

ADD5 26B 26A +13V

ADD4 25B 25A +13V

ADD3 24B 24A +13V

Shield 23B 23A Shield

LVDT 1B (+)Feedback 22B 22A LVDT 2B (+)Feedback

LVDT 1B (-)Feedback 21B 21A LVDT 2B (-)Feedback

No connection 20B 20A No connection

Shield 19B 19A Shield

No connection 18B 18A No connection

No connection 17B 17A No connection

No connection 16B 16A No connection

Shield 15B 15A Shield

COIL DRIVE 1B 14B 14A COIL DRIVE 2B

GROUND 1 13B 13A GROUND 2

No connection 12B 12A No connection

Shield 11B 11A Shield

Table 3-141. Groups 1 and 3 (DC LVDT) Field/Addressing Front Card Edge Connector

Signal Name Component Side Pin # Pin # Signal Name Solder Side

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3-39. QSR

The QSR card address is established by five jumpers on the front card edgeconnector as show inFigure 3-256. Addressing is identical for all groups of thecard.

LVDT 1A (+)Feedback 10B 10A LVDT 2A (+)Feedback

LVDT 1A (-)Feedback 9B 9A LVDT 2A (-)Feedback

No connection 8B 8A No connection

Shield 7B 7A Shield

LVDT 1 (+)Supply 6B 6A LVDT 2 (+)Supply

GROUND 1 5B 5A GROUND 2

No connection 4B 4A No connection

Shield 3B 3A Shield

COIL DRIVE 1A 2B 2A COIL DRIVE 2A

GROUND 1 1B 1A GROUND 2

Figure 3-256. QSR Card Address Jumper Assembly

Table 3-142. Groups 2 and 4 (AC LVDT) Field/Addressing Front Card Edge Connector

Signal Name Component Side Pin # Pin # Signal Name Solder Side

A7 = 1

A6 = 0

A5 = 0

A4 = 1

A3 = 1

JUMPER:

BLANK:

BLANK:

JUMPER:

JUMPER:

CARD-EDGE CONNECTOR(FRONT VIEW)

DIOB CARD ADDRESS = 10011xxx = 9816 - 9F16

See Table 3-143 for valid addresses represented

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3-39.9. Operation

DIOB Data Format

The DPU has access to all channels of the QSR card. The QSR card occupiesDIOB address locations which are assigned as shown inTable 3-143.

where aaaaa is the DIOB address set on the front card edge connector (seeFigure 3-256)

To write a demand to a channel of the QSR, the DPU writes the 12-bit demanone of the last four addresses listed inTable 3-143.

A read operation of a channel requires two steps. First the DPU must write a regnumber to the first address listed inTable 3-143. Register numbers identify fromwhich QSR register the DPU is requesting data. SeeTable 3-144 for registernumbers. The QSR processor then retrieves the desired data from its memorplaces it in the QSR's DIOB read registers. The DPU can then read the latcheobtain the information. A read of any of the eight DIOB address locations provithe same data since there is only one set (two bytes) of DIOB read registers oQSR.

Only double byte (that is, word) DIOB read and write operations are allowed.

Table 3-143. QSR DIOB Address Assignments

DIOB Address Register

aaaaa000 Read Address Request Register

aaaaa001 not used

aaaaa010 not used

aaaaa011 not used

aaaaa100 Channel 1 Demand - Write only

aaaaa101 Channel 2 Demand - Write only

aaaaa110 Channel 3 Demand - Write only

aaaaa111 Channel 4 Demand - Write only

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For each channel, the demand position can be both read and written, and the Lfeedback position can be read where command and status bits are embeddedthe read/write data value. Maximum and minimum scale factors may be readeach channel where valid scale factors only appear for calibrated channels (DVALID status bit=1). The valve type that each channel is currently calibrated tdrive may also be read from the card. The formats of these data types are givFigure 3-257,Figure 3-258, andFigure 3-259.

When reading the feedback position, a Data Valid status bit of 1 indicates thafeedback position value has been determined by the QSR processor. A statuindicates that the QSR has not yet determined the feedback position value orthere is an on-card or LVDT problem (such as an uncalibrated channel) indetermining that value.

Table 3-144. QSR Read Register Assignments

Register Number Assignment

00 Channel 1 Demand

01 Channel 1 Feedback

02 Channel 2 Demand

03 Channel 2 Feedback

04 Channel 3 Demand

05 Channel 3 Feedback

06 Channel 4 Demand

07 Channel 4 Feedback

08 Channel 1 Min Scale Factor

09 Channel 1 Max Scale Factor

0A Channel 2 Min Scale Factor

0B Channel 2 Max Scale Factor

0C Channel 3 Min Scale Factor

0D Channel 3 Max Scale Factor

0E Channel 4 Min Scale Factor

0F Channel 4 Max Scale Factor

10 Valve calibration type for each channel

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3-39. QSR

Figure 3-257. Read Data Format for Reading Demand, Feedback, and Scale Factors

Figure 3-258. Read Data Format for Reading Channel Valve-Type Assignments

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Data Valid (1=Valid 0=Invalid)

Shutdown Direction (1=Positive 0=Negative)

Shutdown Active (1=Active 0=Inactive)

Card OK (1=OK)

MSB

LSB

12 Bit Data

LO ByteHI Byte

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LO ByteHI Byte

Chan4 Chan3 Chan2 Chan1

ChanX =

0 Hex: not yet calibrated for a valve type1 Hex: set up for unipolar1 valve type *2 Hex: set up for unipolar2 valve type *3 Hex: set up for bipolar valve type *F Hex: non-existent channel (used for AC Groups 2 and 4 channels 3 and 4

which do not exist)

* Valve types are listed and explained in the Specificationssection above.

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3-39. QSR

Figure 3-259. Write Data Format for Sending Demands to a Channel

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Not Used

Not Used

Activate Shutdown (1=Activate)

Not Used

MSB

LSB

12 Bit Data

LO ByteHI Byte

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3-39. QSR

3-39.10. Controls and Indicators

Figure 3-260. QSR Card Outline and User Controls

INT

VA

LVE

LEDS

ALIVE

LE1

CAL1

LE2

CAL2

LE3

CAL3

LE4

CAL4

LE5

8 7 6 5 4 3 2 1

UP

1

UP

2

SP

ST

P

CH

1

CH

2

CH

3

CH

4

ST

RT

CA

L

SW1

SW2

TP

2

TP

6

TP

1

TP

3

TP

5

TP

8

TP

11

TP

9 TP

10

TP

7

TP

12 TP13 TP14

TP15

TP

16

TP

17

TP

18

TP

19

TP

20

SH

DN

JS1

DIS

EN

JS2

CT

CA

L

JS3

CA

L

EN

DIS

JS4

DP

U C

TR

L

JS6

NE

G P

OS

NE

G P

OS

JS7

JS9

NE

G P

OS

NE

G P

OS

JS8

NJS10 I

NJS11 I

NJS12 I

TP

4

NJS13 I 15

VJS14 1

6V

15VJS

15 16V

15V JS17

16V

15V JS16

16V

JS18

>10

VJS20

>10

V

JS19

<10

V

JS21

<10

V

JS22

>10

V

JS25

<10

V

JS23

JS24

JS26

>10

V

JS29

<10

V

JS27

JS28

R40 R45R55

R61

R52 R53 R58 R59

RV3

RV

2

RV1

RV

4

R67R68

R10

7R

108

R75R76

R98

R99

R105 R106

R12

5

R12

6

R11

9

R118

R11

5

R113

R167 R162

R14

8

R16

0

JS30

EN

CA

L

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LED Indicators

The following LEDs are located near the card edge (seeFigure 3-260):

ALIVE:

• Stays lit when DPU is communicating with the microcontroller.

• Blinks when the DPU fails to interrupt the microcontroller at least once everseconds.

CALx (x = 1,2,3,4 for Groups 1 and 3; x = 1,2 for Groups 2 and 4):

• Flashes every 0.25 sec when channel x requires internal calibration.

• Blinks every 0.5 sec when channel x requires valve calibration.

• Stays lit when channel x undergoes internal or valve calibration.

• Remains off when channel x has been calibrated and is able to send dempositions to valve and readback valve positions.

Switches

An 8-position DIP switch (SW1) located near the card edge (seeFigure3-260) hasthe following switch configuration:

The start calibration push-button switch (SW2) is also located near the card eThe DIP switch settings are read by the QSR only when this button is presse

UP1 Valve-calibrate channel for unipolar1 valve type

UP2 Valve-calibrate channel for unipolar2 valve type

BP Valve-calibrate channel for bipolar valve type

SSTEP Single-step through valve calibration

CH1 Calibrate channel 1

CH2 Calibrate channel 2

CH3 Calibrate channel 3

CH4 Calibrate channel 4

87

65

43

21

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1)

(see

ardg

Internal Calibration

Internal calibration is performed only by the factory, and is done to set internavoltage ranges for each channel. A channel's calibration LED flashes every 0seconds if the channel has not been internally calibrated. If this occurs in the fithe card should be sent back to the factory.

Valve Calibration

Valve calibration is required of every channel on the QSR each time the channwired to drive a new valve and LVDT. If a channel is already calibrated and powis removed from the card, the channel does not require re-calibration on powif it is wired to drive the same valve and LVDT for which it was most recentlycalibrated to drive. If a channel has never been valve calibrated or if the channbetween valve calibration steps, its calibration LED will blink every 0.5 sec.

Before valve calibration begins, configure the QSR Card as follows (seeFigure 3-260 for locations):

1. Install the Enable Calibration jumper (JS30).

2. Set the DPU Control jumper to the disable (DIS) position (JS4).

3. Set the Calibration Select jumper to the VALVE position (JS3).

4. Set the Valve Type selection jumper to normal (N) or inverted (I) mode baon the valve type (seeChannelValveTypesunderSpecificationsto determinevalve type andTable 3-147 andTable 3-148 to locate jumpers).

5. Select the channel to be calibrated using the front card-edge DIP switch (S(CH1, CH2, CH3, or CH4).

6. Select the valve type being driven using the front card-edge DIP switch (SW(UP1, UP2, or BP).

7. Remove RBP for all channels driving Unipolar1 type valves (seeTable 3-145andTable 3-146 to locate RBP for each channel).

8. Check that feedback wires are installed properly for valve type being drivenChannel Valve Types underSpecifications to determine valve type).

To begin valve calibration, press the start calibration button (SW2) on the front cedge. The Calibration LED (CAL1, CAL2, CAL3, or CAL4) for the channel beincalibrated will remain lit during calibration.

For channels drivingbipolar valves, valve calibration consists of four steps.

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1. Channel coil drive is overdriven in the negative direction which drives the vato its fully driven negative position. An auto-gain coefficient which scales tfully driven LVDT feedback voltage is determined on the card.

2. Channel coil drive is overdriven in the positive direction which drives the vato its fully driven positive position. An auto-gain coefficient which scales thfully driven LVDT feedback voltage is determined on the card. The lesser ofabove two auto-gain coefficients is chosen.

3. Channel coil drive is overdriven in the negative direction and a successiveapproximation is done of the LVDT feedback voltage being scaled by thechosen autogain coefficient. This determines the MAX_SCALE factor.

4. Channel coil drive is overdriven in the positive direction and a successiveapproximation is done of the LVDT feedback voltage being scaled by theautogain coefficient. This determines the MIN_SCALE factor.

Note

MAX_SCALE and MIN_SCALE factors are used totranslate DPU demand codes to coil drive demandvoltages and to translate LVDT feedback voltages toDPU feedback codes.

For channels drivingunipolar valves, valve calibration consists of two steps:

1. Channel coil drive is overdriven in the positive or negative direction (dependon whether the valve is unipolar1 or unipolar2 type) which drives the valveits fully driven positive or negative position. An auto-gain coefficient whichscales the fully driven LVDT feedback voltage is determined on the card. Asuccessive approximation is done of the scaled LVDT feedback voltage todetermine MAX_SCALE factor.

2. Channel coil drive is driven with 0V, and a successive approximation of thLVDT feedback is performed to calculate the MIN_SCALE factor.

Once a channel is calibrated, the channel's calibration LED (CAL1, CAL2, CALor CAL4) is turned off and the microcontroller puts the channel in shutdown.

Note

When all channels driving valves are calibrated, theDPU Control jumper (JS4) must be set to the enable(EN) position so that the DPU may communicatewith the channels.

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If a calibration step fails, any remaining steps are skipped, and calibrationterminates by forcing the channel into its shutdown state. A failure also sets tchannel's Calibration LED (CAL1, CAL2, CAL3, or CAL4) back to its blinkingstate to indicate that the channel still needs valve calibration. If power is cyclethe QSR, the channel's LED will stop blinking if previous successful valvecalibration data was stored for the channel.

To aid in diagnostics, an additional switch setting is provided to allow singlestepping through the calibration routines outlined above. By setting the SSTEswitch on the front card edge DIP switch (SW1) before starting the calibrationroutine, the microprocessor will pause between each step of calibration until calibration button is pressed to proceed on to the next step. The channel'sCalibration LED will be illuminated while a calibration step is executing and wblink between calibration steps.

3-39.11. Plug-in Resistors

Analog Output P/I Loop Circuitry

The output stage of each channel is an analog proportional plus integral (P/I)circuit as shown inFigure 3-261.Figure 3-260 andTable 3-145 andTable 3-146 show the location of the resistors used to locate them on the boa

Bipolar Resistor (RBP)

SeeChannel Valve Types section underSpecifications above to determine whatvalve types require RBP to be installed.Table 3-145 andTable 3-146 list thelocation for RBP in each channel andFigure 3-260 illustrates the location.

Figure 3-261. QSR Analog Output Stage

RF

RLP

V2

1µf

ROUT Valve-

+

RD

RT

RS

RIN

V1

Coil

210 Ωor

100 Ωor

158 Ω

40 Ωor

60 Ωor

80 Ω

D/A Out

FeedbackPosition

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3-39. QSR

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AC LVDT Drive Resistors

Two resistors per channel are used to set the AC LVDT Supply frequency. Thapplies only to Group 2 and 4 boards. Channel 1 resistor locations are R105 R106. Channel 2 resistor locations are R125 and R126.

3-39.12. Jumpers

Per Card

Enable Calibration (EN CAL): When installed, card may be calibrated.(See JS30 onFigure 3-260)

Card Test Calibration (CT CAL): When installed, internal calibration isenabled, only if EN CAL is also installed. (See JS2 onFigure 3-260)

Frequency Resistor

1K Hz 33K Ohms

3K Hz 11K Ohms

Table 3-145. Plug in Resistor Reference Designators (Groups 1 and 3)

Channel RF RS RT RD ROUT RBP

1 R75 R58 R59 R76 R160 R45

2 R99 R98 R115 R113 R162 R55

3 R67 R52 R53 R68 R148 R40

4 R108 R107 R119 R118 R167 R61

Table 3-146. Plug in Resistor Reference Designators (Groups 2 and 4)

Channel RF RS RT RD ROUT RBP

1 R75 R58 R59 R76 R160 R45

2 R67 R52 R53 R68 R148 R40

5/99 3-531 M0-0053Westinghouse Proprietary Class 2C

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3-39. QSR

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Calibration Select (CAL INT/VALVE): In the INT position, pressing the startcalibration button begins internal calibration. In the VALVE position,pressing the button begins valve calibration. (See JS3 onFigure 3-260)

DPU Control Enable/Disable (DPU CTRL EN/DIS): In DIS position, the DPU cannot communicate with the channels. The jumper should be in DIS position on initial power up and during calibration. In EN position,communication is permitted between the DPU and QSR. (See JS4 onFigure 3-260)

Shutdown Enable/Disable (SHDN EN/DIS): In DIS position, channels maintaidemand positions if the DPU breaks communication with the microcontrol In the EN position, communication breakdown drives the channels to th shutdown positions. (See JS1 onFigure 3-260)

Per Channel (see Table 3-147 and Table 3-148 for reference designators)

Valve Shutdown Direction (POS/NEG): In POS position, channel shutdownstate overdrives channel coil drive to approximately +13V. In NEGposition, shutdown state is approximately -13V.

DC LVDT Power Supply Level (15V/16V): In 15V position, LVDT Supplylevels are +15V and -15V referenced to channel ground. In 16V positionLVDT Supply levels are +16V and -16V referenced to channel ground.These jumpers are found on Group 1 and 3 boards only.

LVDT Input Level (>10V/<10V):For Unipolar Valves - feedback span between±1.5V and±7.5V, installjumper in “>10V” position. Feedback span between±7.5V and±15V,install jumper in “<10V” position.

For Bipolar Valves - feedback span between±1.5V and±4V, install jumperin “>10V” position. Feedback span between±4V and±10V, install jumperin “<10V” position.

Valve Type Select (N/I): In N position, Normal valve type is selected. In I positioInverted valve type is selected (see Valve Type section under Specificatiabove).

M0-0053 3-532 5/99Westinghouse Proprietary Class 2C

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3-39. QSR

Table 3-147. Channel Jumper Reference Designators (Groups 1 and 3)

ChannelValve

ShutdownDC LVDT

Supply LevelLVDT Input

LevelValve Type

Select

1 JS8 JS15 JS26, JS27 JS11

2 JS6 JS16 JS18, JS19 JS12

3 JS7 JS14 JS22, JS23 JS10

4 JS9 JS17 JS20, JS21 JS13

Table 3-148. Channel Jumper Reference Designators (Groups 2 and 4)

ChannelValve

ShutdownLVDT Input

LevelValve Type

Select

1 JS8 JS26 - JS29 JS11

2 JS7 JS22 - JS25 JS10

5/99 3-533 M0-0053Westinghouse Proprietary Class 2C

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3-39. QSR

DT

3-39.13. Test Points

Digital Ground: TP1, TP2

Channel Test Points:

3-39.14. Potentiometers for DC LVDT Drive (Groups 1 and 3 only)

These potentiometers are used during internal calibration to adjust the DC LVsupply output levels.

Channel 1: RV1

Channel 2: RV2

Channel 3: RV3

Channel 4: RV4

Table 3-149. Channel Test Point Reference Designators (Groups 1 and 3)

P/I Loop Test Probe for Int.

Channel GND Tie to GND Inject Signal Calibration

1 TP17 TP5 TP6 TP14

2 TP8, TP19 TP7 TP15 TP11

3 TP18 TP3 TP4 TP13

4 TP10, TP20 TP9 TP16 TP12

Table 3-150. Channel Test Point Reference Designators (Groups 2 and 4)

P/I Loop Test Probe for Int.

Channel GND Tie to GND Inject Signal Calibration

1 TP17 TP5 TP6 TP14

2 TP18 TP3 TP4 TP13

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3-39. QSR

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3-39.15. Installation Data Sheet

1 of 5

Installation Notes:

1. Jumpers from A3, A12, B3, and B12 shown above may be jumpered to the (+) Feedsignal instead of the (-) Feedback signal depending on the valve type. The jumpeshould always correspond with the return or COM signal of the LVDT in the field.

2. Although not shown above, jumpers are required from each WDPF shield Term(A2, A5, A8, ..) to ground screw or half shell.

Figure 3-262. QSR Wiring Diagram (Groups 1 and 3)

2B

3B

1B

6B

7B

5B

10B

11B

9B

14B

15B

13B

18B

19B

17B

22B

23B

21B

QSR CARD

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

HALF SHELL EXTENSION(B-BLOCK)

QSR Card

LVDT 2 (-) Supply

Shield

LVDT 2 (+) Supply

Ground 2

Shield

Coil Drive 2

LVDT 1 (-) FB

Shield

LVDT 1 (+) FB

LVDT 1 (-) Supply

Shield

LVDT 1 (+) Supply

Ground 1

Shield

Coil Drive 1

LVDT 2 (+) FB

LVDT 2 (-) FB

Shield

Edge-ConnectorComponent Side

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01 2A

3A

1A

6A

7A

5A

10A

11A

9A

14A

15A

13A

18A

19A

17A

22A

23A

21A

QSR CARD

QSR Card

LVDT 4 (-) Supply

Shield

LVDT 4 (+) Supply

Ground 4

Shield

Coil Drive 4

LVDT 3 (-) FB

Shield

LVDT 3 (+) FB

LVDT 3 (-) Supply

Shield

LVDT 3 (+) Supply

Ground 3

Shield

Coil Drive 3

LVDT 4 (+) FB

LVDT 4 (-) FB

Shield

Edge-ConnectorSolder Side

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3-39. QSR

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Installation Data Sheet

2 of 5

Installation Note:

1. Although not shown above, jumpers are required from each WDPF shield Termin(A2, A5, A8, ..) to ground screw or half shell.

Figure 3-263. QSR Wiring Diagram (Groups 2 and 4)

2B

3B

1B

6B

7B

5B

10B

11B

9B

14B

15B

13B

18B

19B

17B

22B

23B

21B

QSR CARD

B

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

A

TERMINAL BLOCK#8-32 SCREW

HALF SHELL EXTENSION(B-BLOCK)

QSR Card

NC

NC

Ground 1

Shield

Coil Drive 1B

LVDT 1A (-) FB

Shield

LVDT 1A (+) FB

Shield

LVDT 1 (+) Supply

Ground 1

Shield

Coil Drive 1A

LVDT 1B (+) FB

LVDT 1B (-) FB

Shield

Edge-ConnectorComponent Side

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01 2A

3A

1A

6A

7A

5A

10A

11A

9A

14A

15A

13A

18A

19A

17A

22A

23A

21A

QSR CARD

QSR Card

NC

NC

Ground 2

Shield

Coil Drive 2B

LVDT 2A (-) FB

Shield

LVDT 2A (+) FB

Shield

LVDT 2 (+) Supply

Ground 2

Shield

Coil Drive 2A

LVDT 2B (+) FB

LVDT 2B (-) FB

Shield

Edge-ConnectorSolder Side

Ground 1 Ground 2

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3-39. QSR

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Installation Notes (Groups 1 & 3) (Refer to Figure 3-264):

1. Valve interfaces for channels 1 and 3 are shown with the shields connecteearth ground at the B cabinet.

2. Valve interfaces for channels 2 and 4 are shown with the shields connecteearth ground in the field.

Figure 3-264. QSR CE MARK Wiring Diagram (Groups 1 & 3)

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

Ground 1

Coil Drive 1

Ground 3

Coil Drive 3

1

3A

1A

2B

3B

1B

6A

7A

5A

6B

7B

5B

10A

11A

9A

10B

11B

9B

2A

15A

13A

14B

15B

13B

18A

19A

17A

18B

19B

17B

22A

23A

21A

22B

23B

21B

14A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

2

(−) LVDT 1 Supply

(+) LVDT 1 Supply

(−) LVDT 3 Supply

(+) LVDT 3 Supply

(-) LVDT 1 Feedback

(+) LVDT 1 Feedback

(-) LVDT 3 Feedback

(+) LVDT 3 Feedback -16V +16V

Output COM

Ground 2

Coil Drive 2

Ground 4

Coil Drive 4

(−) LVDT 2 Supply

(+) LVDT 2 Supply

(−) LVDT 4 Supply

(+) LVDT 4 Supply

(-) LVDT 2 Feedback

(+) LVDT 2 Feedback

(-) LVDT 4 Feedback

(+) LVDT 4 Feedback -16V +16V

Output COM

LVDT

LVDT

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3. Based on the valve type (unipolar1, unipolar2, or bipolar), the feedback le(Output andCOM) from the LVDT in the field may have to be swapped wheconnected to a channel’s feedback inputs. Whichever feedback lead polarwired in the B cabinet, the earth ground tie should always correspond to tCOM leadnot theOutput lead.

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3-39. QSR

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4 of 5

Figure 3-265. QSR CE MARK Wiring Diagram (Groups 2 & 4 with B Cabinet EarthGrounding)

(-) LVDT 1B Feedback

(+) LVDT 1B Feedback

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

Ground 1

Coil Drive 1A

Ground 2

Coil Drive 2A

1

3A

1A

2B

3B

1B

6A

7A

5A

6B

7B

5B

10A

11A

9A

10B

11B

9B

2A

15A

13A

14B

15B

13B

18A

19A

17A

18B

19B

17B

22A

23A

21A

22B

23B

21B

14A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

2

Ground 1

(+) LVDT 1 AC Supply

Ground 2

(+) LVDT 2 AC Supply

(-) LVDT 1A Feedback

(+) LVDT 1A Feedback

(-) LVDT 2A Feedback

(+) LVDT 2A Feedback

Ground 1

Coil Drive 1B

Ground 2

Coil Drive 2B

(-) LVDT 2B Feedback

(+) LVDT 2B Feedback

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3-39. QSR

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5 of 5

Figure 3-266. QSR CE MARK Wiring Diagram (Groups 2 & 4 with Field Earth Grounding)

(-) LVDT 1B Feedback

(+) LVDT 1B Feedback

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

Ground 1

Coil Drive 1A

Ground 2

Coil Drive 2A

1

3A

1A

2B

3B

1B

6A

7A

5A

6B

7B

5B

10A

11A

9A

10B

11B

9B

2A

15A

13A

14B

15B

13B

18A

19A

17A

18B

19B

17B

22A

23A

21A

22B

23B

21B

14A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

2

Ground 1

(+) LVDT 1 AC Supply

Ground 2

(+) LVDT 2 AC Supply

(-) LVDT 1A Feedback

(+) LVDT 1A Feedback

(-) LVDT 2A Feedback

(+) LVDT 2A Feedback

Ground 1

Coil Drive 1B

Ground 2

Coil Drive 2B

(-) LVDT 2B Feedback

(+) LVDT 2B Feedback

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3-40. QSS

o ayalog

3-40. QSS

Speed Sensor Card(Style 7381A73G01)

3-40.1. Description

Must be sub E or later to be applicable for use in the CE MARK Certified System

The Speed Sensor Card (QSS) converts tachometer signal pulses directly int15-bit binary speed number (seeFigure3-267). This binary number can be read ba software program via the DIOB bus interface. The card also contains an Anoutput that is proportional to the input frequency.

Figure 3-267. QSS Block Diagram

Address Data

DIOB

DIOB

Interface Buffer

Latch

MicroController

Update RateSpeed Range

Select

Timer

ZeroCrossingDetector

D/AConverter

Input SignalAnalog Output

5/99 3-541 M0-0053Westinghouse Proprietary Class 2C

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3-40. QS

S

M0-0053

3-542 5/99

Westinghouse P

roprietary Class 2C

Block D

iagram, D

etailsre

LEDs

Arter

DIOB

DIOB Data

Analog Output0 - 10 V

Address

Figure 3-268. Q

SS

Card F

unctional Block D

iagram

AddressSelect

JumperAddresCompa

BufferLatch

DIOB Control

ZeroCrossingDetector

TimerControl Micro Controller D/

Conve

TimerSpeed Range And

Update RateSelects

InputSine Wave

Signal

Page 609: Ovation Q Line

3-40. QSS

per

OB

with

0%3.0, (see

The QSR card counts zero crossing of the input signal over an update period+/−0.5 T (T is period of the input sine-wave). The update period is selected by jumto be either 50 ms or 25 ms. The Micro Controller (with timer) on the card willdetermine the “2 x frequency” of the input signal. The “2 x frequency” will berepresented by bits 0-14 in a 16 bit output word which can be read via the DIinterface. Bit 15 of the output word is high (“1”) to indicate the presence of afunctional QSS card. This output word is also displayed on the front card edge16 LEDs.

In addition, the card contains a 0 to 10 volt analog output that is proportional toto 125% of the nominal input frequency. The nominal input ranges are 1.5, 1.8,3.6, 6.0, 7.2 kHz. These ranges are selected via a switch located on the cardFigure 3-269 for an illustration of the speed selection switch andFigure 3-270 forthe location of this component.)

Figure 3-269. QSS Speed Selection Switch

ON OFF

SPARE1

1500

1800

3000

3600

6000

7200

SPARE2

(NOMINAL SPEED = 3600 HZ, AS SHOWN ABOVE)

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3-40. QSS

ss

ss

3-40.2. Specifications

Inputs/Outputs

Power Supply Voltage

Inputs

The Speed Channel (QSS) card accepts a sine wave input. The input may beconnected to 120 Vac RMS without damage.

Sensitivity: 0.5 V P-P @ 36 Hz8.0 V P-P @ 7.2 kHz

Common Mode: Voltage: 20V P-P (Max.)

Nominal Input Speeds: 1.5 kHz1.8 kHz3.0 kHz3.6 kHz6.0 kHz7.2 kHz

Input Impedance: 40 k ohms

DIOB Output

Data word:16 Bits (Bits 0-14 = two times the input frequency, Bit 15 = 1,Bit 0 = LSB, Bit 14 = MSB)

Update Rate:Selectable by jumper to be either one of the following:

50 ms±0.5 T for speeds greater than or equal to 20 Hz, 1.0 T for speeds lethan 20 Hz.

25 ms±0.5 T for speeds greater than or equal to 40 Hz, 1.0 T for speeds lethan 40 Hz.

Minimum Nominal Maximum

Primary 12.4 V 13.0 V 13.1 V

Optional Backup 12.4 V -- 13.1 V

Current (supplied by DIOB) - 500mA 650mA

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Page 611: Ovation Q Line

3-40. QSS

where:

Output: Binary value equal to two times the input frequency.

Accuracy: Minimum one LSB resolution (± 0.5 Hz) over temperature range for lowupdate rate (50 ms); minimum two LSB resolution (±1 Hz) overtemperature range for High update rate (25 ms)

Output value indication:16 LEDs (seeFigure 3-270).

Analog Output

Isolated Output Span: 10V

Nominal Input Speeds: 1.5 kHz1.8 kHz3.0 kHz3.6 kHz6.0 kHz7.2 kHz

Output: 0 to +10V proportional to 0 to 125% of nominal speed setting

Accuracy: 0.1% of span at 25 C

Output Load: 500 ohms or greater short circuit protection provided

Output Limits: -0.1V to +10.1V

T = period of input sine-wave.

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3-40. QSS

card

e

3-40.3. Controls and Indicators

LED Errors

In normal operation, the QSS maintains a self test. If an error is detected, thewill enter the error mode.

• If the watchdog timer is enabled via a jumper (seeFigure3-270) the watchdogtimer will time out to reset the card until the error is corrected.

• If the watchdog timer is disabled, errors can be read via flashing LEDs (seLED Detail inFigure3-270). The meaning of the patterns is described inTable3-151:

Figure 3-270. QSS Card Components

Table 3-151. QSS Watchdog Timer

Bit Number Mnemonic Description

0 ANALOG ERROR Error in Analog output circuitry

1 CALIB ERROR Analog output below 10V

2 TIMER ERROR Error in Timer control circuit

3 DIPSWITCH Invalid setting of DIP switch

4 PULSE ERROR Pulse generator malfunction

LEDs

ResetSpeed SelectionSwitch

Update PeriodJumper

Error Mode(Watchdog Timer)Jumper

D07D06D05D04D03D02D01D00

D14D13D12D11D10D09D08

POKCOK

LED Detail

Switch

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3-40. QSS

r

.

5 TIMER FLAGS Error in two second loop

6 AO OVF Speed is greater than 125% of nominal.(This error will cause the QSS to enter error mode, howevethe error is saved for display if another error occurs).

7 AO AVERAGE Analog calibration data too high

8 TIMER DATA Invalid data received from timers, three consecutive times

9 SPI ERROR Invalid serial port interrupt

10 T2I ERROR Invalid Timer 2 Interrupt

11 FPNEG Negative floating point number

12 FPOVF Floating point overflow

13 FPUNF Floating point underflow

14 FPNAN Number not a floating point value

15 COK Card OK bit

16 POK Power OK

Table 3-151. QSS Watchdog Timer

Bit Number Mnemonic Description

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3-40. QSS

persts for

3-40.4. Installation Data Sheet

1 of 3

Field Input Connections (Refer to Figure 3-271)

The QSS card employs the standard Q-Series front-edge connector. Eight jumare used to determine the DIOB address. Contacts supplied include two contacthe speed input and two contacts for the analog output signal. SeeTable 3-152below.

Figure 3-271. QSS Wiring Diagram (Recommended)

Table 3-152. QSS Field Inputs

Pin Number Field Signals

1A Earth ground from card clamp

3A Analog output shield

This configuration is for maximum common mode rejectionand is recommended. Other options are shown on the following pages.

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

20B

20A

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

1B

1A

InputReturn

InputSignal

InputEarth

OutputSource

OutputReturn

+

-

InputCircuit

OutputCircuit

A1

QSS Card

A2

A

20

19

Ground

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Page 615: Ovation Q Line

3-40. QSS

5A Analog output shield

13A Earth ground from card clamp

15A Speed input signal

17A Speed input return

1B Earth ground from card clamp

3B Analog output return (−)

5B Analog output return (−)

7B Analog output source (+)

13B Speed input shield

15B Speed input shield

Table 3-152. QSS Field Inputs

Pin Number Field Signals

5/99 3-549 M0-0053Westinghouse Proprietary Class 2C

Page 616: Ovation Q Line

3-40. QSS

Installation Data Sheet

2 of 3

Figure 3-272. QSS Wiring Diagram

InputReturn

OutputReturn

InputCircuit

QSS

A1

Card

18

17

16

15

14

13

12

11

19B

19A

17B

17A

15B

15A

13B

13A

11B

A

09A

07B

07A

05B

05A

03B

03A

01B

01A

09

08

07

06

05

04

03

02

01

OutputReturn

OutputSource

OutputEarth

+

-

OutputCircuit

A2

QSSCard

This configuration has the speed input cable’s shieldat the DPU chassis.

This configuration has the output shieldterminated at the Field.

19

20

Ground

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Page 617: Ovation Q Line

3-40. QSS

d to

inet.

For CE MARK Certified System

3 of 3

Installation Notes:

1. The output shield must be connected to the output return, with both connecteearth ground at the B cabinet as shown.

2. The input shield may be connected to earth ground in the field or at the B cab

Figure 3-273. QSS CE MARK Wiring Diagram

1B

3A

3B

5A

5B

7A

7B

9A

9B

11A

11B

13A

13B

15A

15B

17A

17B

19A

1A

19B

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

OutputReturn

OutputSource+

-

InputReturn

InputSignal

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3-41. QST

eirer)

PF

tover,acerd,

3-41. QST

Smart Transmitter Interface(Style 4256A76G01 and G02)

3-41.1. Description

There are many field devices (known as “smart” transmitters) that transmit thvalues over a digital link. The HART (Highway Addressable Remote Transducprotocol is one such link specification. Communication via this interface to WDis provided through the Smart Transmitter Interface. Complete details on theinstallation and use of this interface are found in“SmartTransmitterInterface(STI)User’s Guide” (U0-1115).

In brief, the interface consists of three separate printed circuit cards:

• Q-Line Smart Transmitter (QST)

• SBX Smart Transmitter link (SST)

• Q-Line Serial Link Controller (QLC)

The QLC card with one SST card may be connected to up to four QST cardsprovide a hardware interface for up to 24 smart transmitter current loops. Howethe QLC software limits the actual number of QSTs to three, providing an interfto a maximum of 18 smart transmitter loops. For additional detail on the QLC casee “QLC User’s Guide” (U0-1100).

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Page 619: Ovation Q Line

3-42. QTB

e bying

3-42. QTB

Time Base(Style 2840A20G01 through G04)

3-42.1. Description

Groups 03 and 04 are applicable for use in the CE MARK Certified System

The QTB card is the source of DIOB analog control timing signals (seeFigure3-274). The card generates precise analog control timing signals for usanalog point cards within a process control system. The QTB (by digitally trackthe power line frequency) generates integration, clock, and offset conversioncommand signals to the analog input cards via the DIOB.

Figure 3-274. QTB Block Diagram

5/99 3-553 M0-0053Westinghouse Proprietary Class 2C

Page 620: Ovation Q Line

3-42. QTB

iod.

bledB. Aps

z,

z,

Hz

Hz

ard

3-42.2. Features

The QTB provides the following features:

• Calibration not affected when integration period is varied to match line per

• Provides command to signal analog point card to obtain offset value.

• Variable time-base clock.

• Digital power line frequency tracking.

• Optional crystal oscillator controlled timing.

• Compatible with any DIOB controller.

• Optional redundant configuration with primary and backup QTB cards.

• 50 Hz or 60 Hz operation.

• Auto-zeroing.

• Real time clock circuit.

The QTB card has card-edge jumper-selectable options for either normally enaor disabled QTB operation following power up or system initialization. The QTmay also be enabled or disabled at any time by the bus controller via the DIOBcommand on the DIOB overrides the initially jumpered set-up. Four QTB grouare available:

• G01 compatible with 60 Hz systems; provides frequency tracking for a 60 Hinput-voltage frequency.

• G02 compatible with 50 Hz systems; provides frequency tracking for a 50 Hinput-voltage frequency.

• G03 compatible with 60 Hz systems; has no frequency tracking for the 60frequency.

• G04 compatible with 50 Hz systems; has no frequency tracking for the 50frequency.

The QTB Card complies with the DIOB interface design specifications. This cmay be used in a Q-crate assembly.

3-42.3. Specifications

Figure 3-275 shows a functional block diagram of the card.

M0-0053 3-554 5/99Westinghouse Proprietary Class 2C

Page 621: Ovation Q Line

3-42. QTB

Input Voltage (G01 and G02)

120 VAC+ 10 percent (rms)

Sourcing Current: 20 mA

Input Voltage Frequency

G01 – 60 Hz+ 2 Hz

G02 – 50 Hz+ 2 Hz

G03 and G04 – None (internal crystal oscillator)

Maximum Change:+ 0.06 percent/sec

Input Common Mode Voltage

Surge: IEEE Surge Withstand Capability

Continuous:+ 500 VDC (maximum)

Input Normal Mode Voltage

Surge: IEEE Surge Withstand Capability

5/99 3-555 M0-0053Westinghouse Proprietary Class 2C

Page 622: Ovation Q Line

3-42. QTB

Figure 3-275. QTB Card Functional Block Diagram

CO

UN

TE

R

LAT

CH

UIO

BIN

TE

RFA

CE

D I O B

TR

I-S

TAT

EB

UF

FE

R

DIG

ITA

LT

RA

CK

ER

+12V

UC

AL

US

YN

C

UC

LOC

K

UA

DD

UD

AT

DAT

A G

ATE

UN

IT

DAT

A D

IR

HI/L

O

SE

T

RE

SE

T

EN

AB

LE/D

ISA

BLE

STA

RT

CA

RD

-ED

GE

JU

MP

ER

SY

NC

CLO

CK

AC

INP

UT

f L

(G01

AN

DG

02 O

NLY

)

+12V

DIS

AB

LE

M0-0053 3-556 5/99Westinghouse Proprietary Class 2C

Page 623: Ovation Q Line

3-42. QTB

cy

dth

NC

Output Signal UCLOCK

Logic 1: +2.0V (minimum)

+3V (nominal)

+4.5V (maximum)

Logic 0: −0.6V (minimum)

0.0V (nominal)

+0.5V (maximum)

UCLOCK is a pulse train with varying ON/OFF time. The time-averaged frequenis equal to 10,240 times the input-voltage frequency.

Output Signal USYNC

Logic 0: 0V to +3V

Logic 1: +8V to +12V

Output Signal UCAL

Logic 0: +12V (nominal)

Logic 1: 0V (nominal)

UCAL is low true for one pulse every 512 line-frequency cycles. The pulse wiis longer than the USYNC high time by 500 UCLOCK periods.

Power Supply

Primary: +12.4V (minimum)

+13.0V (nominal)

+13.1V (maximum)

Optional Backup: +12.4V (minimum)

+13.1V (maximum)

Current: 100 mA

3-42.4. Real Time Clock

The QTB Card, Real Time Clock is two five-stage counters clocked by the SYsignal. The resulting outputs are:

• 16, 8, 4, 2, and 1 Hz

5/99 3-557 M0-0053Westinghouse Proprietary Class 2C

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3-42. QTB

(i.e.,e thercent

ata

putkingn

y5.

The counter outputs are gated and jumpered for reset circuitry. The jumpers JU5-2 for G01 and G03; JU5-1 for G02 and G04) ensures that the outputs arsame regardless of group type. However, the counter outputs do not have 50 peduty cycles and the duty cycle is not the same on 50 Hz and 60 Hz cards.

The Real Time Clock can be read with a normal DIOB Read operation. The Dformat is shown inFigure 3-276.

NoteThe Real Time Clock stability is excellent for G01and G02 since these groups are synchronized withthe line frequency. However, G03 and G04 have noline tracking and long term stability of the Real TimeClock is slightly lower.

3-42.5. QTB Timing Requirements

The QTB output signals are closely related in timing requirements. As the AC infrequency changes, the USYNC signal must also change since USYNC is tracthe line frequency. During the time USYNC is high, signal integration occurs oanalog input cards. TheUCAL signal may be pulled low by the bus controller at antime, but a QTB-initiatedUCAL occurs on the rising edge of the USYNC pulse 25The UCLOCK signal occurs very rapidly compared to USYNC andUCAL.UCLOCK also varies with the AC input frequency as shown inFigure 3-277. TheUCLOCK signal inFigure 3-277 is magnified for clarity. Normally, UCLOCKoccurs approximately 40,960 times during a USYNC pulse.

Figure 3-276. QTB Real Time Clock Data Format

0.5 Hz (50 PERCENT DUTY CYCLE

ENABLED

1 Hz

2 Hz

4 Hz

8 Hz

16 Hz

USYNC

7 6 5 4 3 2 1 0 BIT

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Page 625: Ovation Q Line

3-42. QTB

Note

The USYNC signal occurs on the rising edge of thesquared-up AC input signal. However, USYNCends 40,960 clock pulses later and this pulse widthmay vary with input frequency.

3-42.6. Control and Indicators

Figure 3-278 shows the card outline.

Figure 3-277. QTB Output Signal Timing Diagrams

Figure 3-278. QTB Card Outline

NORMAL INPUT FREQUENCY

LOW INPUT FREQUENCY

HIGH INPUT FREQUENCY

UCLOCK

2550 1

USYNCPULSE

UCAL

21

LOCK-OUT BY CONTROLLER QTBINITIATED

0

5/99 3-559 M0-0053Westinghouse Proprietary Class 2C

Page 626: Ovation Q Line

3-42. QTB

n to

ere this

ry

AI

Note

There are no user-configurable jumpers on thiscard. All user jumpering is done at the front card-edge connector.

3-42.7. Connectors and Terminations

The QTB uses a standard Q-line front connector. The front connector, in additiothe nine address jumpers, uses the following pins:

• Pins 2B and 8B for the 117 VAC line and neutral, respectively.

• Pin 5A for AC ground.

• Pins 12A and 12B for PRIMARY.

• Pins 14A and 14B for a one-card system jumper.

• Pins 16A and 16B for ENABLE.

• Pins 19A and 19B for INHIBIT UCAL.

The ENABLE jumper must be in place for proper QTB Card operation.

The jumper in pins 14A and 14B is in place for systems using one QTB Card. This no backup QTB. In redundant configurations where a backup QTB is used,jumper must be omitted.

The PRIMARY jumper is used in redundant configurations to identify the primacard in a two-QTB system.

The INHIBIT CAL jumper is used in special applications to defeat theauto-calibration feature. This jumper must be removed for a DIOB which has Qcards.

Note

For CE Mark certified systems, fieldwiring that carries the AC mains musthave double insulation.

M0-0053 3-560 5/99Westinghouse Proprietary Class 2C

Page 627: Ovation Q Line

3-42. QTB

thether ahe

cardRealard

3-42.8. Redundant QTB Configurations

The QTB Card can be configured in a primary-backup connection controlled byjumper selection on the front-edge connector. The active card is selected as eiprimary or backup using a DIOB output cycle. The active card always drives tUSYNC,UCAL and UCLOCK lines.

Both the primary and backup cards are given the same address. The primaryuses the low byte while the secondary card uses the high byte when reading theTime Clock. Both cards respond to the same output cycle (Lo Byte) for active cselection.

5/99 3-561 M0-0053Westinghouse Proprietary Class 2C

Page 628: Ovation Q Line

3-43. QTO

the

s

3-43. QTO

3-43.1. Description

The QTO card receives DIOB signals and provides solid-state AC switching tofield processes within a plant environment (seeFigure 3-279). This card containseight identical solid state relays (TRIAC’s) capable of 120 VAC line frequencyswitching. An on-card read/write latch provides an 8-bit memory function. Thicard also contains a switch selectable dead-computer time-out.

Figure 3-279. QTO Block Diagram

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Page 629: Ovation Q Line

3-43. QTO

ls att out

3-43.2. Features

The QTO card is available in one group only. This card provides the followingfeatures:

• IEEE surge-withstand protection.

• 500 VDC common mode rating.

• Read/write output data operation.

• On-card power-up, bus, and dead-computer time-out resets.

• Card-edge LED indicator for each TRIAC output.

• Switch-selectable dead computer time-out periods.

• Compatible with any DIOB controller.

• Zero voltage switching for reducing inductive load surges (seeFigure 3-280).

The QTO interfaces the DIOB through a rear-edge connector. The DIOB signathis interface are defined by DIOB standards. The TRIAC outputs are broughto the front edge of the card.

5/99 3-563 M0-0053Westinghouse Proprietary Class 2C

Page 630: Ovation Q Line

3-43. QTO

Figure 3-280. TRIAC Zero Voltage Switching

Voltageacrosstriac(Resistiveload)

Voff (Peak)

Voff (RMS)

Vtrigger = 15 V Maximum

Von = 1.5 V Maximum

0=Off10=On

0=Off

Where t delay (On) and t delay (Off) = 5/8 line cycle maximum

tdelay (On) tdelay (Off)

QTOLatchbitstatus

M0-0053 3-564 5/99Westinghouse Proprietary Class 2C

Page 631: Ovation Q Line

3-43. QTO

Figure 3-281. TRIAC Operation with Load Current Below 75 mA

Voltageacrosssolidstateswitch

Voff (Peak)

Voff

0=Off

1=On

0=OffQTOLatchbitstatus

5/99 3-565 M0-0053Westinghouse Proprietary Class 2C

Page 632: Ovation Q Line

3-43. QTO

3-43.3. Specifications

A functional block diagram of the QTO is shown inFigure 3-282.

Figure 3-282. QTO Functional Block Diagram

ADDRESS DATA

POWER

CARD

COMPARE

TO JUMPER

LATCHRESET

OR

9

UNIT

EIGHT-BIT

OPTICAL

DRIVERS

~

DIOB~

9

POINT 0

8

8

+SSR

POINT 7

+SSR

LATCH

ISOLATORSADDRESS

UP

REFRESH

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Page 633: Ovation Q Line

3-43. QTO

Power Requirements

Output Capabilities

Minimum Nominal Maximum

Primary Voltage 12.4 VDC + 13.0 VDC 13.1 VDC

Optional Backup 12.4 VDC -- 13.1 VDC

Current 150mA 250mA

Characteristic Minimum Typical Maximum Units

Voltage (RMS) 80 115 140 VAC

Current (ON) 0.075* -- 1.8 A RMS (continuous)10A RMS (T≤ 5 cycles)

Frequency 47 -- 63 HZ

Common Mode Voltage -- -- 500 VDC (Peak)300 VAC (RMS)(line frequency

Current (OFF) -- -- 8 mA (RMS)

* The load current must be above 75 mA to fire the TRIAC (seeFigure 3-281).

5/99 3-567 M0-0053Westinghouse Proprietary Class 2C

Page 634: Ovation Q Line

3-43. QTO

geine.

3-43.4. Card Addressing

The QTO card address is selected by eight jumpers on the top, front, card-edconnector (seeFigure3-283). Insertion of a jumper encodes a 1 in the address l

3-43.5. Controls and Indicators

QTO card components are shown inFigure 3-284.

The LEDs indicate which Triac output is active.

Figure 3-283. QTO Card Address Jumper Assembly Example

A7 = 1

A6 = 1

A5 = 0

A4 = 0

A3 = 1

A2 = 0

A1 = 0

A0 = 0

JUMPER:

JUMPER:

BLANK:

BLANK:

JUMPER:

BLANK:

BLANK:

BLANK:

CARD-EDGE CONNECTOR(FRONT VIEW)

HI-LO = 1 (i.e., HIGH BYTE)JUMPER:

CARD ADDRESS = 1100 1000(X ‘C8’ HIGH BYTE)

M0-0053 3-568 5/99Westinghouse Proprietary Class 2C

Page 635: Ovation Q Line

3-43. QTO

d is

If the QTO Card is not periodically updated, the card resets. The update perioset by four DIP switches as given inTable 3-153.

Figure 3-284. QTO Card Components

Update PeriodDIP Switches

LEDs

76543210

LEDDetail

5/99 3-569 M0-0053Westinghouse Proprietary Class 2C

Page 636: Ovation Q Line

3-43. QTO

hese

mize.

3-43.6. Connectors and Terminations

The QTO Card interfaces to the DIOB via a standard DIOB, rear, card-edgeconnector.

The Solid-State Relay (SSR) outputs are brought to the front edge of the card. Ttwo-wire outputs have the contact pin allocations listed inTable 3-154. R-Csnubbing networks are provided on the card across the SSR terminals to miniinductive load surges on TRIAC turnoff, and to protect the SSR from damage

Table 3-153. QTO Card Reset Switch Position

DIP SwitchReset Time

A B C D

0 0 0 0 62 ms+ 20%

0 0 1 0 125 ms+ 20%

0 1 0 0 250 ms+ 20%

0 1 1 0 500 ms+ 20%

1 0 0 0 1 sec+ 20%

1 0 1 0 2 sec+ 20%

1 1 0 0 4 sec+ 20%

1 1 1 0 8 sec+ 20%

X X X 1 No time out, data Latched (X = don’t care)

Table 3-154. QTO Digital Output Contact Allocations

Output Digital BitNumber PC Card Edge Pin No. Field Terminal Block Terminal No.

B0 3A 2

3B 3

B1 5A 4

5B 5

B2 7A 6

7B 7

B3 9A 8

9B 9

B4 11A 10

M0-0053 3-570 5/99Westinghouse Proprietary Class 2C

Page 637: Ovation Q Line

3-43. QTO

11B 11

B5 13A 12

13B 13

B6 15A 14

15B 15

B7 17A 16

17B 17

Table 3-154. QTO Digital Output Contact Allocations (Cont’d)

Output Digital BitNumber PC Card Edge Pin No. Field Terminal Block Terminal No.

5/99 3-571 M0-0053Westinghouse Proprietary Class 2C

Page 638: Ovation Q Line

3-43. QTO

3-43.7. Installation Data Sheet

1 of 1

Figure 3-285. QTO Wiring Diagram

19B

19A

17B

17A

15B

15A

13B

13A

11B

11A

9B

9A

7B

7A

5B

5A

3B

3A

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

CARD

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

TERMINAL BLOCK

EDGE-CONNECTOR CUSTOMER CONNECTIONS

20B

20A

TYPICAL

HI/LO JUMPER

5A

19

20

M0-0053 3-572 5/99Westinghouse Proprietary Class 2C

Page 639: Ovation Q Line

3-44. QVP

IMtial

lve

lve

tion.

PF

3-44. QVP

Servo Valve Position Controller(Style 4256A94G01 through G04)

3-44.1. Description

Groups 01, 02, 03, and 04 are applicable for use in the CE MARK Certified System

The QVP is the interface between a WDPF DPU drop’s DIOB controller, an O(M/A station), a hydraulic servo valve positioner, and a linear variable differentransformer (LVDT) attached to the stem of the controlled valve.

The QVP is available in four groups:

• Group 1 LVDT interface, 80 ohm (+/-24 mA) servo-valve coils

• Group 2 LVDT interface, 280 ohm (+/-50 mA) servo-valve coils

• Group 3 4 to 20 mA current loop interface, 80 ohm (+/-24 mA) servo-vacoils

• Group 4 4 to 20 mA current loop interface, 280 ohm (+/-50 mA) servo-vacoils

Consult the “Q-Line Valve Position (QVP) Servo Controller User’s Guide”(U0-1125), or contact your Westinghouse representative for additional informa

3-44.2. Features

• Computer (Automatic) or PB Manual mode operation.

• Computer or PB Manual mode selection via external OIM signals or the WDdrop’s DIOB controller.

• Simplified valve calibration procedures that do not require trim-pots.

• Automatic valve closing bias.

• Servo valve contingency setpoint

• LVDT feedback position rate of change monitoring.

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3-44.3. Functional Description

An on-card 80C32 microcontroller provides a link between the QVP card’s DIinterface circuit, the hydraulic servo valve coil drive circuit, and the LVDT primacoil excitation and LVDT secondary coil demodulation circuit. A valve positionsetpoint is maintained by the QVP.

The setpoint may normally be altered by the OIM’s Raise/Lower pushbuttons othe WDPF drop via the DIOB interface. The QVP’s microcontroller provides closloop proportional-plus-integral (PI) control for real time servo valve positioncontrol. The valve position setpoint causes the QVP card to generate redundcontrol output signals which drive the hydraulic servo valve actuator coils. Thfeedback loop is closed with the valve position measurement obtained from a LVthat is mounted on the valve stem at the actuator.

3-44.4. Specifications

Table 3-155. LVDT Coil Drive Outputs

Signal 1.00 kHz +/-10% sine wave or 3.00 kHz +/-10% sine wave(user selectable via jumpers)

Amplitude: Group 1 Group 2

17.00 Vp-p +/-5%, adjustable23.75 Vp-p +/-5%, adjustable

Gain Change 0.5% maximum (0 to 60 C)

Offset 25 mV maximum (0 to 60 C)

Total Harmonic Content 1% maximum

Protection The QVP card Primary Coil Drive circuit may be short circuitewithout damage to the circuit. Short circuit current is limited to 80mA nominal.

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Table 3-156. LVDT Secondary Inputs

Signal span 25 Vp-p maximum

Common mode voltage +/- 10 volts maximum

Common mode rejection 55 dB maximum

Voltage applied +/-30 volts maximum

Differential InputImpedance

10 k ohm with input open-circuited

Table 3-157. QVP Valve Coil Drive Outputs

Signal span: Groups 1 and 3 Groups 2 and 4

+/-2.00 V (+/-25 mA maximum into 80 ohm coils)+/-14.2 V (+/-50.7 mA maximum into 280 ohm coils)

Load resistance: Groups 1 and 3 Groups 2 and 4

80 ohm +/-12%280 ohm +/-10%

Protection Any output will function correctly if the other output(s) are shocircuited to common. All outputs may be short circuited to +10 Vor to -10 V without suffering damage.

Table 3-158. QVP Setpoint Output

Signal span 0.0 to +10.0 volts nominal

Load resistance 5 k ohm minimum

Gain error 50 mV maximum (0 to 60 C)25 mV maximum (25 C)

Offset 25 mV maximum (0 to 60 C)4 mV maximum (25 C)

Protection The QVP card Setpoint Voltage circuit output terminals may bshort circuited without damage to the circuit. Short circuit currenis limited to 80 mA nominal.

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Table 3-159. QVP Valve Position Output

Signal span 0.0 to +10.0 volts at 25 C

Load resistance 500 ohm minimum

Gain error: CPU alive

CPU dead

50 mV maximum (0 to 60 C)25 mV maximum (25 C)200 mV maximum (0 to 60 C)

Offset: CPU alive

CPU dead

25 mV maximum (0 to 60 C)4 mV maximum (25 C)100 mV maximum (0 to 60 C)

Protection The QVP card Position Voltage circuit output terminals may bshort circuited without damage to the circuit. Short circuit currenis limited to 80 mA nominal.

Table 3-160. QVP Current Loop Input (Groups 3 and 4)

Signal Unipolar DC current

Input range 4 to 20 mA20 mA = 0% (fully closed)4 mA = 100% (fully open)

Input Impedance 250 ohms +/-2%The inpedance converts the 4 to 20 mA input current into a 1 toV input voltage.

Input Circuit A differential input stage is used to reject common mode voltagpresent at the QVP card inputs.

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3-44. QVP

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Table 3-161. QVP Digital Outputs

Quantity 2 (Manual and Servo-Bad)

Power Supply 21.6 to 30 Volts maximum24 Volts nominalThis voltage must be supplied from an external isolated powersupply.

Minimum on voltage 2 VDC sinking 150 mA3 VDC sinking 200mA

Maximum on current 200 mA

Maximum off voltage 30 VDC

Maximum off current 0.5 mA at 30 VDC

Table 3-162. QVP Digital Inputs

Quantity 6 (Man-Sel, Raise, Lower, Prty-Raise, Prty-Lower, Man-Shtdw

Power Supply 21.6 to 30 Volts maximum24 Volts nominalThis voltage must be supplied from an external isolated powersupply.

Minimum on voltage 20 Volts

Maximum on voltage 30 Volts

Maximum off voltage 6 Volts

Minimum on current 4.5 mA

Maximum on current 11.5 mA

Maximum off current 3 mA

Table 3-163. QVP Watchdog Timer

Time-out period 45 msec +/-33%

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3-44.5. Interface

The QVP card occupies a block of eight consecutive DIOB word addresses. Aeight of these DIOB addresses can be written to, but reading any of the eightaddresses will get the same data. Before data transfer to and from the QVP caroccur, the DIOB address lines must contain an address that has been assignedQVP card.

The QVP card’s base DIOB address is selected by the installation of jumpers oQVP card’s P2 connector’s mating front card edge connector (see example inFigure3-286). Five jumpers may be used to select the base address which will alwaysin a 0 or an 8. A sixth jumper, CARD-ENA/, must always be installed to enablQVP card access by the DIOB controller.

The QVP card interfaces the DIOB controller using sixteen bit data words. Sithe DIOB is a byte oriented data bus, two DIOB data transfers are required totransfer DIOB data to or from a QVP card. The order of data transfer must alwbe low byte first, followed by the high byte. Byte data transfers are not permit

Figure 3-286. Example of QVP DIOB Base Address Selection

Up

Jumper installed - Address Bit = Logic 1Jumper removed - Address Bit = Logic 0

QVP card DIOBBase Address = B8

DIOB Addresses B8through BF areassigned to this QVP card

QVP P2 card edge connector’s mating hood(front view)

CA7 = 1

CA6 = 0

CA5 = 1

CA4 = 1

CA3 = 1

CARD-ENA = 1

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3-44.6. Manual Controls

TestpointsThe QVP card contains 12 testjacks mounted at the front edge of the card. Ttestjacks permit a voltmeter to be used to measure specific voltage levels on QVP card or to provide contact inputs in parallel with three of the external isolacontact inputs. Four additional three-position header are used as test points oQVP card.

Table 3-164. QVP Testjacks

Testjack Number Name Function

TP1 AGND Analog power supply common

TP2 VPCAL Bipolar DC output voltage of the LVDT demodulatorcircuit (Groups 1 and 2)

TP3 VSET Setpoint Meter Drive voltage

TP4 VPOS Position Meter Drive voltage

TP5 VC1 Servo-valve coil 1 voltage

TP6 VC2 Servo-valve coil 2 voltage

TP7 VC3 Servo-valve coil 3 voltage

TP8 C-COM Servo-valve coil drive circuit power supply common

TP9 ISO-COM Isolated power supply common

TP10 LMAN-SEL/ Isolated Local Manual mode select contact input

TP11 R/ Isolated Local Manual mode valve Raise contact inpu

TP12 L/ Isolated Local Manual mode valve Lower contact inpu

JS1 Digital Common

JS7 Analog Common

JS10 Analog Common

JS11 +10 V Reference voltage

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3-44. QVP

front

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voP

QVP CardFigure 3-287 illustrates the manual controls and LEDs on a QVP card. Thesecontrols are described in the following sections.

SwitchesThe QVP card contains two switches (SW1 and SW2) that are located near theedge of the card (seeFigure 3-287).

• SW1 is a pushbutton switch. Pressing and releasing this switch will cause a hreset of the QVP.

• SW2 is an SPST toggle switch. The two positions of this switch aretestandon-line.

Thetest, or up position of this switch will disconnect the servo drive from theservo coils and isolate the servo drive amplifiers from the P2 front edge conne

Theon-line, or down position of this switch will connect the servo drive to the sercoils. SW2must be in the on-line, or down position for normal operation of the QVcard

Figure 3-287. QVP Card

JS2JS3

JS5JS6

JS8 JS9

SRVO OKMAN

SW1

SW2

POK

123

123

123

123

123

123

LE1

LE2LE3

Switches

JumpersLEDs

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LEDsThe QVP card contains three LED indicators that are mounted near the front of the card (seeFigure3-287).Table3-165describes what the LEDs indicate whethey are lit or unlit.

JumpersThe QVP card (Groups 1 and 2) contain six three-position single row headersplug-in jumpers installed (seeFigure 3-287). The QVP card (Groups 3 and 4)contain four three-position single row headers with plug-in jumpers installed.

Table 3-165. QVP LEDs

LED Lit Unlit

LE1 The QVP DIOB power fuse is intactand at least one DIOB supply voltageis present.

The QVP DIOB power fuse is open orneither DIOB supply voltage is present.

LE2 If the QVP card is powered, there isno detected problem with the QVPcard’s servo-valve control operation.

There is a problem with the QVP card’sservo-valve control operation.

LE3 The QVP card is operating in PBMANUAL mode.

The QVP card is currently not in PBMANUAL mode, and may be in any othermode.

Table 3-166. QVP Option Select Headers

Header Posts Shorted Function

JS2 1 -22-3

Enable Alive watchdog timerDisable Alive watchdog timer

JS3 1 -22 -3

Normal running modeTest mode

JS5 1 -22 -3

Disable DIOB watchdog timerEnable DIOB watchdog timer

* JS6 1 -22 -3

Configure from QVP algorithmConfigure from on-board EEPROM

**JS8**JS9

1 -22 -3

Selects LVDT Excitation Oscillator sinewave frequency of 1 KHzSelects LVDT Excitation Oscillator sinewave frequency of 3 KHz

* See the Calibration section in“QVP” Servo Controller User’s Guide” (U0-1125).** Groups 1 and 2 only.

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3-44. QVP

3-44.7. Installation Data Sheet

Figure 3-288. QVP Wiring Diagram (Using #6 Screws)

Coil 3 Out (-)

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

9A

10A

8B

9B

10B

16A

17A

18A

20B

21B

22B

20A

21A

22A

16B

17B

18B

8A

13A

14A

12B

13B

14B

2A

2B

3A

3B

4A

4B

5A

1B

1A

6A

12A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

B

Coil 3 Out (+)

Coil 2 Out (-)

Coil 2 Out (+)

Coil 1 Out (-)

Coil 1 Out (+)

VOSC (-)

VOSC (+)

LVDT B(-)

LVDT B(+)

LVDT A(-)

LVDT A(+)

+ 24VDC

+ 24VDC RTN

+ 24VDC RTN

MANUAL/

PRTY-LOWER/

PRTY-RAISE/

RAISE/

LOWER/

MAN-SEL/

MAN-SHTDWN/

V POS (-)

V POS (+)

V SET PT (-)

V SET PT (+)

SERVO-BAD/

Recommended grounding:

(QHS)

(H/S Ext)

Figure 3-288 shows shields grounded at the halfshell. Insert a #6 screw in the holelocated near the shield terminal on halfshell block “A” and add six jumpers(as shown). Six holes have been drilled on each halfshell block for this purpose.

19

20

19

20

5BDigitalOutputs

DigitalInputs

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3-44. QVP

Installation Data Sheet

Figure 3-289. QVP Wiring Diagram (Using #8 Screws)

Recommended grounding:Figure 3-289 shows shields grounded at the halfshell. Insert a #6 screw in the holelocated near the shield terminal on halfshell block “A” and add six jumpers(as shown). Six holes have been drilled on each halfshell block for this purpose.

Coil 3 Out (-)

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

9A

10A

8B

9B

10B

16A

17A

18A

20B

21B

22B

20A

21A

22A

16B

17B

18B

8A

13A

14A

12B

13B

14B

2A

2B

3A

3B

4A

4B

5A

5B

1B

1A

6A

12A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

B

Coil 3 Out (+)

Coil 2 Out (-)

Coil 2 Out (+)

Coil 1 Out (-)

Coil 1 Out (+)

VOSC (-)

VOSC (+)

LVDT B(-)

LVDT B(+)

LVDT A(-)

LVDT A(+)

+ 24VDC

+ 24VDC RTN

+ 24VDC RTN

MANUAL/

PRTY-LOWER/

PRTY-RAISE/

RAISE/

LOWER/

MAN-SEL/

MAN-SHTDWN/

V POS (-)

V POS (+)

V SET PT (-)

V SET PT (+)

SERVO-BAD/

(QHS)

(H/S Ext)

(as shown). Six holes have been drilled on each halfshell block for this purpose.

DigitalOutputs

DigitalInputs

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3-44. QVP

For CE MARK Certified System

Figure 3-290. QVP CE MARK Wiring Diagram

Coil 3 Out (-)

CARD

EDGE-CONNECTOR

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

9A

10A

8B

9B

10B

16A

17A

18A

20B

21B

22B

20A

21A

22A

16B

17B

18B

8A

13A

14A

12B

13B

14B

2A

3A

2B

3B

4B

4A

5A

5B

1A

1B

6A

12A 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

A

PE

2

Coil 3 Out (+)

Coil 2 Out (-)

Coil 2 Out (+)

Coil 1 Out (-)

Coil 1 Out (+)

VOSC (-)

VOSC (+)

LVDT B(-)

LVDT B(+)

LVDT A(-)

LVDT A(+)

+ 24VDC

+ 24VDC RTN

+ 24VDC RTN

MANUAL/

PRTY-RAISE/

PRTY-LOWER/

RAISE/

MAN-SEL/

LOWER/

MAN-SHTDWN/

V POS (-)

V POS (+)

V SET PT (-)

V SET PT (+)

SERVO-BAD/

* DIN-rail mounted tension clamp terminal block

*

*

DigitalOutputs

DigitalInputs

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Appendix A. Worksheets

A-1. Section Overview

The following pages contain three worksheets which can be used to assign arecord Q-Card addresses and Q-Crate slot assignments.

• Worksheet A shows the possible Q-Card hardware addresses, and providspace to record the card which is assigned each address.

• Worksheet B can be used to record the Q-Crate slot assignment and assihardware address for each card (when default naming is not used).

• Worksheet C can be used to record the Q-Crate slot assignment for each (when default naming is used). The address associated with each card slodefault naming) is shown also.

Both Worksheets B and C show the card-edge connector identification andhalf-shell location (zone-row) for each Q-Crate slot, and provide space to recordcard type and group. For additional information on the default naming option, reto “MA C Utilities User’s Guide” (U0-0136).

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A-1. Section Overview

Figure A-1. Q-card Hardware Address Selection Form

Worksheet AQ-Card Address Assignments

*8081828384858687

*9091929394959697

*A0A1A2A3A4A5A6A7

*B0B1B2B3B4B5B6B7

*C0C1C2C3C4C5C6C7

D0D1D2D3

*D4D5D6D7

* E0E1E2E3

*E4E5E6E7

*F0F1F2F3

*F4F5F6F7

*88898A8B8C8D8E8F

*98999A9B9C9D9E9F

*A8A9AAABACADAEAF

*B8B9BABBBCBDBEBF

*C8C9CACB

*CCCDCECF

*D8D9DADB

*DCDDDEDF

*E8E9EAEB

*ECEDEEEF

*F8F9FAFBFCFDFEFF

0001020304050607

*1011121314151617

*2021222324252627

*3031323334353637

*4041424344454647

*5051525354555657

*6061626364656667

*7071727374757677

* 08090A0B0C0D0E0F

*18191A1B1C1D1E1F

* 28292A2B2C2D2E2F

*38393A3B3C3D3E3F

*48494A4B4C4D4E4F

*58595A5B5C5D5E5F

* 68696A6B6C6D6E6F

*78797A7B7C7D7E7F

Indicates restricted address – DO NOT USEIndicates reserved address (80 = QTB; AA and 55 = QBO; F8-FB = QRT)

Indicates address used with default naming feature*Q-Cards with:

12 channels (QAX) must start at zero and use 2 blocks of 6 addresses

4 channels (QAI, QAO, QPA, QSE) must start at x0, x4, x8, xC2 channels (QAA, QAM, QLC) must start at x0, x2, x4, x6, x8, xA, xC, xE

where x = 0 through F

Other cards (QBI, QCI, QDI, QID, QRO, QSC, QSP, QTO) may use any address

Available only if QTB and/or DIOB checking is not implemented

8 or 6 channels (QAH, QAV, QAW, QLI, QLJ) must start at x0, x8

Note

QBI and QDI are being replaced by the QID card

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A-1. Section Overview

Worksheet B

Worksheet B

Drop No. Cabinet No.Q-Crate 1 (Q1)

Q-Crate 2 (Q2)

Q-Crate 3 (Q3)

Q-Crate 4 (Q4)

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 102 104 106 108 110 112 114 116 118 120 122 124

Address

Half-Shell A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 202 204 206 208 210 212 214 216 218 220 222 224

Address

Half-Shell C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 302 304 306 308 310 312 314 316 318 320 322 324

Address

Half-Shell E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 402 404 406 408 410 412 414 416 418 420 422 424

Address

Half-Shell G1 H1 G2 H2 G3 H3 G4 H4 G5 H5 G6 H6

Q-Line I/O Layout

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A-1. Section Overview

Worksheet C

Worksheet CQ-Line I/O Layout

Drop No. Cabinet No.

Q-Crate 1 (Q1)

Q-Crate 2 (Q2)

Q-Crate 3 (Q3)

Q-Crate 4(Q4)

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 102 104 106 108 110 112 114 116 118 120 122 124

Address 08 10 18 20 28 30 38 40 48 50 58 60

Half-Shell A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 202 204 206 208 210 212 214 216 218 220 222 224

Address 68 70 78 80 88 90 98 A0 A8 B0 B8 C0

Half-Shell C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 302 304 306 308 310 312 314 316 318 320 322 324

Address C8 CC D0 D4 D8 DC E0 E4 E8 EC F0 F4

Half-Shell E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6

Slot 1 2 3 4 5 6 7 8 9 10 11 12 13

Card Type QBE

Group

Card Edge 402 404 406 408 410 412 414 416 418 420 422 424

Address

Half-Shell G1 H1 G2 H2 G3 H3 G4 H4 G5 H5 G6 H6

(Default Naming Option)

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Appendix B. Setting Q-Card Addresses

B-1. Introduction

This appendix shows how to set the appropriate jumpers to define an addresQ-card.FigureB-1 shows the connector handle and position of the address jump

FigureB-2 shows a head-on view of the address jumpers. The figure also showconversion of the hexadecimal address (supplied by Westinghouse on theworksheets) and the binary equivalent via jumpering.

Table B-1 shows the binary equivalent for hexadecimal 00 to FF (256)

Figure B-1. Address Jumpers on Cable Connector (“B” Cabinet Terminations)

28 (Last Address Jumper)27262524232221 (First Address Jumper

Location)

Note:The first 20 locations arereserved for card wiring.

WDPFIIQ- L i n eI / O

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B-1. Introduction

Figure B-2. Card Address Jumper Assembly

DIOB CARD ADDRESS = 00100011 = 23H

A5 = 1

A6 = 0

A4 = 0

A1 = 1

A0 = 1

JUMPER:

BLANK:

BLANK:

JUMPER:

JUMPER:

A3 = 0BLANK:

A2 = 0BLANK:

A7 = 0BLANK:

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B-1. Introduction

Table B-1. Conversion of Hexadecimal Number to Jumper Address

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

00 0 0 0 0 0 0 0 0

01 0 0 0 0 0 0 0 1

02 0 0 0 0 0 0 1 0

03 0 0 0 0 0 0 1 1

04 0 0 0 0 0 1 0 0

05 0 0 0 0 0 1 0 1

06 0 0 0 0 0 1 1 0

07 0 0 0 0 0 1 1 1

08 0 0 0 0 1 0 0 0

09 0 0 0 0 1 0 0 1

0A 0 0 0 0 1 0 1 0

0B 0 0 0 0 1 0 1 1

0C 0 0 0 0 1 1 0 0

0D 0 0 0 0 1 1 0 1

0E 0 0 0 0 1 1 1 0

0F 0 0 0 0 1 1 1 1

10 0 0 0 1 0 0 0 0

11 0 0 0 1 0 0 0 1

12 0 0 0 1 0 0 1 0

13 0 0 0 1 0 0 1 1

14 0 0 0 1 0 1 0 0

15 0 0 0 1 0 1 0 1

16 0 0 0 1 0 1 1 0

17 0 0 0 1 0 1 1 1

18 0 0 0 1 1 0 0 0

19 0 0 0 1 1 0 0 1

1A 0 0 0 1 1 0 1 0

1B 0 0 0 1 1 0 1 1

1C 0 0 0 1 1 1 0 0

1D 0 0 0 1 1 1 0 1

1E 0 0 0 1 1 1 1 0

1F 0 0 0 1 1 1 1 1

20 0 0 1 0 0 0 0 0

21 0 0 1 0 0 0 0 1

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B-1. Introduction

22 0 0 1 0 0 0 1 0

23 0 0 1 0 0 0 1 1

24 0 0 1 0 0 1 0 0

25 0 0 1 0 0 1 0 1

26 0 0 1 0 0 1 1 0

27 0 0 1 0 0 1 1 1

28 0 0 1 0 1 0 0 0

29 0 0 1 0 1 0 0 1

2A 0 0 1 0 1 0 1 0

2B 0 0 1 0 1 0 1 1

2C 0 0 1 0 1 1 0 0

2D 0 0 1 0 1 1 0 1

2E 0 0 1 0 1 1 1 0

2F 0 0 1 0 1 1 1 1

30 0 0 1 1 0 0 0 0

31 0 0 1 1 0 0 0 1

32 0 0 1 1 0 0 1 0

33 0 0 1 1 0 0 1 1

34 0 0 1 1 0 1 0 0

35 0 0 1 1 0 1 0 1

36 0 0 1 1 0 1 1 0

37 0 0 1 1 0 1 1 1

38 0 0 1 1 1 0 0 0

39 0 0 1 1 1 0 0 1

3A 0 0 1 1 1 0 1 0

3B 0 0 1 1 1 0 1 1

3C 0 0 1 1 1 1 0 0

3D 0 0 1 1 1 1 0 1

3E 0 0 1 1 1 1 1 0

3F 0 0 1 1 1 1 1 1

40 0 1 0 0 0 0 0 0

41 0 1 0 0 0 0 0 1

42 0 1 0 0 0 0 1 0

43 0 1 0 0 0 0 1 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

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B-1. Introduction

44 0 1 0 0 0 1 0 0

45 0 1 0 0 0 1 0 1

46 0 1 0 0 0 1 1 0

47 0 1 0 0 0 1 1 1

48 0 1 0 0 1 0 0 0

49 0 1 0 0 1 0 0 1

4A 0 1 0 0 1 0 1 0

4B 0 1 0 0 1 0 1 1

4C 0 1 0 0 1 1 0 0

4D 0 1 0 0 1 1 0 1

4E 0 1 0 0 1 1 1 0

4F 0 1 0 0 1 1 1 1

50 0 1 0 1 0 0 0 0

51 0 1 0 1 0 0 0 1

52 0 1 0 1 0 0 1 0

53 0 1 0 1 0 0 1 1

54 0 1 0 1 0 1 0 0

55 0 1 0 1 0 1 0 1

56 0 1 0 1 0 1 1 0

57 0 1 0 1 0 1 1 1

58 0 1 0 1 1 0 0 0

59 0 1 0 1 1 0 0 1

5A 0 1 0 1 1 0 1 0

5B 0 1 0 1 1 0 1 1

5C 0 1 0 1 1 1 0 0

5D 0 1 0 1 1 1 0 1

5E 0 1 0 1 1 1 1 0

5F 0 1 0 1 1 1 1 1

60 0 1 1 0 0 0 0 0

61 0 1 1 0 0 0 0 1

62 0 1 1 0 0 0 1 0

63 0 1 1 0 0 0 1 1

64 0 1 1 0 0 1 0 0

65 0 1 1 0 0 1 0 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

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B-1. Introduction

66 0 1 1 0 0 1 1 0

67 0 1 1 0 0 1 1 1

68 0 1 1 0 1 0 0 0

69 0 1 1 0 1 0 0 1

6A 0 1 1 0 1 0 1 0

6B 0 1 1 0 1 0 1 1

6C 0 1 1 0 1 1 0 0

6D 0 1 1 0 1 1 0 1

6E 0 1 1 0 1 1 1 0

6F 0 1 1 0 1 1 1 1

70 0 1 1 1 0 0 0 0

71 0 1 1 1 0 0 0 1

72 0 1 1 1 0 0 1 0

73 0 1 1 1 0 0 1 1

74 0 1 1 1 0 1 0 0

75 0 1 1 1 0 1 0 1

76 0 1 1 1 0 1 1 0

77 0 1 1 1 0 1 1 1

78 0 1 1 1 1 0 0 0

79 0 1 1 1 1 0 0 1

7A 0 1 1 1 1 0 1 0

7B 0 1 1 1 1 0 1 1

7C 0 1 1 1 1 1 0 0

7D 0 1 1 1 1 1 0 1

7E 0 1 1 1 1 1 1 0

7F 0 1 1 1 1 1 1 1

80 1 0 0 0 0 0 0 0

81 1 0 0 0 0 0 0 1

82 1 0 0 0 0 0 1 0

83 1 0 0 0 0 0 1 1

84 1 0 0 0 0 1 0 0

85 1 0 0 0 0 1 0 1

86 1 0 0 0 0 1 1 0

87 1 0 0 0 0 1 1 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

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B-1. Introduction

88 1 0 0 0 1 0 0 0

89 1 0 0 0 1 0 0 1

8A 1 0 0 0 1 0 1 0

8B 1 0 0 0 1 0 1 1

8C 1 0 0 0 1 1 0 0

8D 1 0 0 0 1 1 0 1

8E 1 0 0 0 1 1 1 0

8F 1 0 0 0 1 1 1 1

90 1 0 0 1 0 0 0 0

91 1 0 0 1 0 0 0 1

92 1 0 0 1 0 0 1 0

93 1 0 0 1 0 0 1 1

94 1 0 0 1 0 1 0 0

95 1 0 0 1 0 1 0 1

96 1 0 0 1 0 1 1 0

97 1 0 0 1 0 1 1 1

98 1 0 0 1 1 0 0 0

99 1 0 0 1 1 0 0 1

9A 1 0 0 1 1 0 1 0

9B 1 0 0 1 1 0 1 1

9C 1 0 0 1 1 1 0 0

9D 1 0 0 1 1 1 0 1

9E 1 0 0 1 1 1 1 0

9F 1 0 0 1 1 1 1 1

A0 1 0 1 0 0 0 0 0

A1 1 0 1 0 0 0 0 1

A2 1 0 1 0 0 0 1 0

A3 1 0 1 0 0 0 1 1

A4 1 0 1 0 0 1 0 0

A5 1 0 1 0 0 1 0 1

A6 1 0 1 0 0 1 1 0

A7 1 0 1 0 0 1 1 1

A8 1 0 1 0 1 0 0 0

A9 1 0 1 0 1 0 0 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

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B-1. Introduction

AA 1 0 1 0 1 0 1 0

AB 1 0 1 0 1 0 1 1

AC 1 0 1 0 1 1 0 0

AD 1 0 1 0 1 1 0 1

AE 1 0 1 0 1 1 1 0

AF 1 0 1 0 1 1 1 1

B0 1 0 1 1 0 0 0 0

B1 1 0 1 1 0 0 0 1

B2 1 0 1 1 0 0 1 0

B3 1 0 1 1 0 0 1 1

B4 1 0 1 1 0 1 0 0

B5 1 0 1 1 0 1 0 1

B6 1 0 1 1 0 1 1 0

B7 1 0 1 1 0 1 1 1

B8 1 0 1 1 1 0 0 0

B9 1 0 1 1 1 0 0 1

BA 1 0 1 1 1 0 1 0

BB 1 0 1 1 1 0 1 1

BC 1 0 1 1 1 1 0 0

BD 1 0 1 1 1 1 0 1

BE 1 0 1 1 1 1 1 0

BF 1 0 1 1 1 1 1 1

C0 1 1 0 0 0 0 0 0

C1 1 1 0 0 0 0 0 1

C2 1 1 0 0 0 0 1 0

C3 1 1 0 0 0 0 1 1

C4 1 1 0 0 0 1 0 0

C5 1 1 0 0 0 1 0 1

C6 1 1 0 0 0 1 1 0

C7 1 1 0 0 0 1 1 1

C8 1 1 0 0 1 0 0 0

C9 1 1 0 0 1 0 0 1

CA 1 1 0 0 1 0 1 0

CB 1 1 0 0 1 0 1 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

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B-1. Introduction

CC 1 1 0 0 1 1 0 0

CD 1 1 0 0 1 1 0 1

CE 1 1 0 0 1 1 1 0

CF 1 1 0 0 1 1 1 1

D0 1 1 0 1 0 0 0 0

D1 1 1 0 1 0 0 0 1

D2 1 1 0 1 0 0 1 0

D3 1 1 0 1 0 0 1 1

D4 1 1 0 1 0 1 0 0

D5 1 1 0 1 0 1 0 1

D6 1 1 0 1 0 1 1 0

D7 1 1 0 1 0 1 1 1

D8 1 1 0 1 1 0 0 0

D9 1 1 0 1 1 0 0 1

DA 1 1 0 1 1 0 1 0

DB 1 1 0 1 1 0 1 1

DC 1 1 0 1 1 1 0 0

DD 1 1 0 1 1 1 0 1

DE 1 1 0 1 1 1 1 0

DF 1 1 0 1 1 1 1 1

E0 1 1 1 0 0 0 0 0

E1 1 1 1 0 0 0 0 1

E2 1 1 1 0 0 0 1 0

E3 1 1 1 0 0 0 1 1

E4 1 1 1 0 0 1 0 0

E5 1 1 1 0 0 1 0 1

E6 1 1 1 0 0 1 1 0

E7 1 1 1 0 0 1 1 1

E8 1 1 1 0 1 0 0 0

E9 1 1 1 0 1 0 0 1

EA 1 1 1 0 1 0 1 0

EB 1 1 1 0 1 0 1 1

EC 1 1 1 0 1 1 0 0

ED 1 1 1 0 1 1 0 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

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B-1. Introduction

ding a

For an adjacent cabinet, the next 256 (decimal) addresses are obtained by adjumper below the A0 (or number 20) location as seen inFigure B-2.

EE 1 1 1 0 1 1 1 0

EF 1 1 1 0 1 1 1 1

F0 1 1 1 1 0 0 0 0

F1 1 1 1 1 0 0 0 1

F2 1 1 1 1 0 0 1 0

F3 1 1 1 1 0 0 1 1

F4 1 1 1 1 0 1 0 0

F5 1 1 1 1 0 1 0 1

F6 1 1 1 1 0 1 1 0

F7 1 1 1 1 0 1 1 1

F8 1 1 1 1 1 0 0 0

F9 1 1 1 1 1 0 0 1

FA 1 1 1 1 1 0 1 0

FB 1 1 1 1 1 0 1 1

FC 1 1 1 1 1 1 0 0

FD 1 1 1 1 1 1 0 1

FE 1 1 1 1 1 1 1 0

FF 1 1 1 1 1 1 1 1

Table B-1. Conversion of Hexadecimal Number to Jumper Address (Cont’d)

Hexadecimal Card Address

Jumper Settings

A7 A6 A5 A4 A3 A2 A1 A0

M0-0053 B-10 5/99Westinghouse Proprietary Class 2C

Page 665: Ovation Q Line

a

andl

Appendix C. Card-Edge FieldTermination

C-1. Section Overview

The DPU drop utilizes one of two methods of field signal terminations. Thisappendix discusses the card-edge termination, where the drop is packaged insingle “A” Cabinet.

In the second method (cabinet termination), the drop is packaged in dual (“A”“B”) cabinets. Refer toSection 2 for information on the cabinet method of signatermination.

Note

There are two types of A and B cabinets, theStandard and the Enhanced. With theEnhanced cabinets, there are more slots forQ-Cards, more half-shell zones, and moreterminals per half-shell zone.

5/99 C-1 M0-0053Westinghouse Proprietary Class 2C

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6

alserted

ts 20ideinto

C-2. Card-Edge Connectors

Card-edge terminations are recommended only for “A” Cabinets with threeQ-crates with a maximum of 12 Q-cards per crate, providing a maximum of 3cards. When using card-edge termination, field connections are made toscrew-down terminals on each card’s edge connector.

Note

Use of card-edge connections is notrecommended with the Enhanced “A” cabinetwith 4 Q-Crates.

Field termination edge connectors are used at each Q-card for user field signconnections. Q-Card addresses are assigned using jumper clips which are ininto the termination card-edge connector.

The field termination card-edge connector also contains address selection slothrough 28, as shown inFigure C-1. These 9 slots are located on the top right sof the connector. A specific card address is selected by the insertion of jumpersthe appropriate slots.

Note

The card-edge termination connector cannotbe used with a QAA or QAX card.

Figure C-1. Address Jumpers on Card-Edge Termination Connector

M0-0053 C-2 5/99Westinghouse Proprietary Class 2C

Page 667: Ovation Q Line

oded

et

Figure C-2 shows the standard card-edge termination hardware, with an explview of a card-edge connector.

The cabinet illustrated inFigure C-2 is a Standard cabinet. An Enhanced cabinwould contain four Q-Crate zones.

Figure C-2. Standard Card-Edge Field Connections

Edge Connector for Field Terminations

FUSE

Paddle Cardfor Expansion

CARD

EDGE

CONNECTOR

Slot 1Q-Card

Q-Crate

ElectronicsA-Cabinet

Front

Q

CRATE

ZONES

Q1

Q2

Q3

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ld

ell

p to

rafter

As shown inFigureC-3, each connector contains 20 screw-down terminals for fiesignal terminations. The top 7 screw-down terminals (1 through 7) are fieldtermination tie points, which duplicate the function of the B-block in the half-shtype terminations. These tie points are not used in analog terminations.

Field connections to and from the card-edge connector can be made using uNo. 14 AWG conductor wire. However, for ease of connector removal andreplacement after installation, Westinghouse recommends that No. 16 AWG osmaller conductor wire be used. Each connector’s wires are bundled togetherthe field connections are completed, and are tie-wrapped to the cabinet framedirectly under the Q-crate.

Figure C-3. Screw-Down Terminal Numbers

19A17A15A13A11A9A7A5A3A1A

7

6

5

4

3

21

19B17B15B13B11B9B7B5B3B1B

Fuse Field

Field

TerminationTie Points

SignalTerminations

FieldSignal

Terminations

M0-0053 C-4 5/99Westinghouse Proprietary Class 2C

Page 669: Ovation Q Line

ate

Table C-1, which illustrates the Q-crate terminal locations, can be used to locterminals for field signal connection.

Table C-1. Card-Edge Terminal Locations

Card Slot Numbers

1 2 3 4 5 6 7 8 9 10 11 12

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

Q1

Q

CRATE

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

Q2

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

19B • 19A •• ••1B•1A

Q3

Note: Field Termination Tie Points not shown.

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tionthe

toove

,

uld be

ector

ors.

and/

to the

ector

C-3. Field Wiring Card-Edge Terminations

Follow these procedures for field wiring the WDPF System to the terminationcard-edge connectors within the electronics cabinet. Use the custom TerminaLists supplied for the system to locate specific termination points. Also refer tospecific card information provided inSection 3.

WARNING

Remove drop power and use extreme cautionwhen making field connections to theseedge-connectors. A shock hazard to personnelmay exist on some of the higher voltage signals.

1. Select a card-edge termination connector for field wiring. It is usually beststart at Q-crate 1, slot 1. Then work across to slot 12 of Q-crate 1, and then mdown to Q-crate 2, slot 1 and so on. Another option is to start at Q-crate 3working up to Q-crate 1.

2. If not previously done at the factory, insert the appropriate jumpers in theupper-right hand side of the connector. Each card’s selected address shoin compliance with the terminations list.

Caution

After address selection, take care not to switchconnectors between cards. Doing so willindiscriminately switch card addresses.

3. Locate the field wires or cables to be connected to the selected edge-connand make connections to the screw-down terminals.

Connection to these terminals may be made with up to No. 14 AWG conductHowever, for ease of connector installation and removal, Westinghouserecommends no greater than No. 16 AWG conductors be used. Only wiresor cables which comply with each field connection’s signal and noiseminimization requirements should be used.

4. Bundle the wires connected to the terminal block with tie wraps and thentie-wrap to the cabinet frame directly under the Q-crate. Use wire tags toidentify the cables.

Remember to leave service loops to relieve stress and/or to permit accesscabinet when it is to be moved out of position for maintenance purposes.

5. Repeat the procedures of Steps 1 through 4 for each remaining edge-connuntil all field terminations to the cabinet have been completed.

M0-0053 C-6 5/99Westinghouse Proprietary Class 2C

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Index

----

Numerics12 Point Analog Input card 3-1738039 3-423

AA/D converter 3-49actuator auto manual card 3-14actuator position 3-15address blocks 2-29address jumpers B-1address selection slot C-2address selection via jumper 2-36addresses

setting B-1addressing constraints 2-32Air Temperatures 2-39analog conditioning card 3-37analog high level input point 3-148analog input card 3-61analog input point 3-49analog output card 3-100analog position 3-19analog signal conditioner 3-37analog signal filtering 2-12Analog Signal Shielding Techniques 2-15analog to digital 3-119, 3-148, 3-173analog velocity 3-18analog-to-digital converters 3-61Auto mode 3-344, 3-353Automatic mode 3-91Automatic/Manual card 3-74

BB Cabinet

compensation 2-19enhanced 2-23standard 2-23Termination Structure 2-25

Beck drive 3-14bridge power supply 2-19Bridge Resistor 3-436, 3-439

Ccabinet number, def. 2-5Cabinet Termination 2-22cable length 3-260cable routing 2-37card replacement 2-37

Card Type Index 3-179, 3-180card-edge

connectors 2-3, C-2, C-6field termination C-1termination 2-22, C-6

cascaded control loop 3-332CCI 2-21CCO 2-21CD 3-179, 3-180CE MARK Certified System 3-49, 3-61, 3-

100, 3-119, 3-148, 3-173, 3-193, 3-200, 3224, 3-235, 3-254, 3-265, 3-276, 3-282, 3296, 3-317, 3-318, 3-351, 3-365, 3-398, 3399, 3-420, 3-421, 3-458, 3-483, 3-512, 3541, 3-553, 3-573

Chattering 3-483, 3-490clock 3-86, 3-87Clock Synchronizing 3-500Cold Junction 3-193common mode rejection 3-128common-mode voltage 2-11compensation

B-cabinet 2-19half-shell 2-18on-board 2-20

configuration constants 3-325, 3-338configuration data 3-325, 3-338contact allocations 3-417contact input card 3-254contact-wetting voltage 3-254Continuous Scan 3-50control timing 3-66copper RTD 3-423Current Amplifier card 3-235current to pressure, I/P converter 3-74

Ddatabase

limitations 2-35daughter card 3-16derived QPA functions 3-386diagnostic test card 3-276differential input 3-50digital contact input 3-254Digital Controller 3-265digital input 3-213, 3-266digital input card 3-212digital multiplexed interface 3-61

5/99 Index-1 M0-0053Westinghouse Proprietary Class 2C

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Index

----

,,,

digital output card 3-224digital signal 3-100digital signal isolation 2-11digital, increased cable length 3-296digital-to-analog 3-100DIOB 3-70, 3-318, 3-332, 3-359

Addressing 3-381definition 3-366interface 3-20, 3-44, 3-79monitor 3-283

DIP switch 3-99Display mode 3-279DPU 2-2drops 1-1

EE/P, voltage to pressure 3-74EEPROM 3-325elapsed time measurement 3-365electromagnetic 2-13electromagnetic field 2-11electrostatic 2-13electrostatic field 2-11ENABLE jumper 2-36Enable signal 2-32errors, LED 3-546

Ffast acting actuator 3-14field signal

connections 2-38termination 2-22, C-1

list 2-3wiring 2-2

field termination 2-2field wiring 2-1, 2-2FLAG 3-366flag bit 3-133, 3-160flow-rate meter 3-365Four Wire RTD Input Amplifier 3-399frequency summation 3-421frozen 3-366

Gground connection, def. 2-5Grounding 2-13

Hhalf-shell 2-3

compensation 2-18Termination 2-38termination C-4zone location, def. 2-5

hardware addresses 2-29available 2-29determining 2-29restricted blocks 2-29Selection Form 2-31worksheet A-1

HART 3-552highways 1-1Hl/LO jumper 2-36Hl/LO signal 2-32Humidity Rating 2-39

II/P, current to pressure 3-74increased cable length (digital) 3-296Input Amplifier

Four Wire RTD card 3-399Input Amplifier card 3-421

Jjumper 2-36, 3-19, 3-34, 3-57, 3-97, 3-131, 3

135, 3-158, 3-178, 3-196, 3-207, 3-228, 3257, 3-290, 3-326, 3-339, 3-380, 3-415, 3416, 3-435, 3-455, 3-500, 3-503, 3-543, 3544, 3-546, 3-558, 3-561, 3-568

ENABLE 2-36HI/LO 2-36

Llamps 3-224LED 3-33, 3-95, 3-114, 3-134, 3-137, 3-162,

3-164, 3-185, 3-207, 3-221, 3-231, 3-2623-274, 3-278, 3-291, 3-306, 3-326, 3-3393-349, 3-353, 3-357, 3-457, 3-472, 3-5033-543, 3-546, 3-568

LIM 1-4, 3-319, 3-333, 3-343Block Diagram 3-344Components 3-349Features 3-344groups 3-10power consumption 2-41ranges 3-10

M0-0053 Index-2 5/99Westinghouse Proprietary Class 2C

Page 673: Ovation Q Line

Index

Specifications 3-348limit check 3-121, 3-149line frequency switching 3-562links DIOB backplane 3-200LMAN 3-19LMNA 3-19Local mode 3-345, 3-353Loop Interface card 3-318

with output readback 3-332Loop Interface Module 3-343low pass filtering 2-9Lower output 3-344, 3-352Lower setpoint 3-344, 3-352low-level signal, shielding 2-15

MManual mode 3-91, 3-345, 3-353memory bus 3-359Memory Bus Terminator card 3-359monitor DIOB 3-283mother card 3-16multiple channel hardware address 2-32multiplex 3-61multi-speed DPU 2-35

Nnickel RTD 3-423noise

class 2-10discrimination 2-7minimization techniques 2-7problems 2-37source 2-10

noise and signal sources 2-10noise minimization techniques 2-1noise rejection 2-11noise-sensitive suppression 2-12

OOn-Board Compensation 2-20open thermocouple detection 3-64optical isolator 2-11output data 3-159output flashing 3-232Output Signal Noise Rejection 2-12Ovation

QAV 3-139QAX 3-180

overrange bit 3-49, 3-160

Ppin assignments 3-261platinum 3-423platinum RTD 3-423plug braking 3-14point number, def. 2-4position encoder 3-365position feedback 3-14potentiometers 3-98Power Consumption 2-40power line frequency 2-9Proper Grounding and Shielding 2-13Pulse Accumulator 3-365

QQAA 1-4, 3-14

Card Addressing 3-20Card Outline 3-16Controls and Indicators 3-23groups 3-4power consumption 2-40ranges 3-4Specifications 3-18Tuning 3-24Word Format 3-20

QAC 1-4, 3-37Block Diagram 3-37Controls and Indicators 3-48groups 3-4power consumption 2-40ranges 3-4Specifications 3-42

QAH 1-4, 3-49Block Diagram 3-49Card Addressing 3-53CE MARK Wiring Diagram 3-60Controls and Indicators 3-57groups 3-4Installation Data Sheet 3-59power consumption 2-40ranges 3-4Specifications 3-50

QAI 1-4, 3-61Block Diagram 3-61Card Addressing 3-70Card Diagram 3-71

5/99 Index-3 M0-0053Westinghouse Proprietary Class 2C

Page 674: Ovation Q Line

Index

CE MARK Wiring Diagram 3-73groups 3-4, 3-62Installation Data Sheet 3-72power consumption 2-40ranges 3-4Specifications 3-63

QAM 1-4, 3-74Block Diagram 3-74Controls and Indicators 3-91groups 3-5power consumption 2-40ranges 3-5Reset 3-94Specifications 3-78

QAO 1-4, 3-100Block Diagram 3-100Card Addressing 3-113CE MARK Wiring Diagram 3-117Controls and Indicators 3-113groups 3-5, 3-101Installation Data Sheet 3-116power consumption 2-40ranges 3-5Specifications 3-105

QAV 1-4, 2-19analog input point 3-119Block Diagram 3-119Card Addressing 3-131CE MARK Wiring Diagram 3-147Controls and Indicators

(Level 6 and earlier) 3-134(Level 8 and later) 3-136

Features 3-123groups 3-5Installation Data Sheet 3-143power consumption 2-40ranges 3-5Specifications 3-126

QAW 1-4, 3-148Block Diagram 3-148Card Addressing 3-158CE MARK Wiring Diagram 3-172Controls and Indicators 3-162, 3-163groups 3-6Installation Data Sheets 3-165power consumption 2-40ranges 3-6Specifications 3-151

QAX 1-4, 3-173Block Diagram 3-173Card Addressing 3-178CE MARK Wiring Diagram 3-189Controls and Indicators 3-184groups 3-6Installation Data Sheet 3-186power consumption 2-40ranges 3-6Specifications 3-176

QAXD 1-4, 3-190groups 3-6power consumption 2-40ranges 3-6

QAXT 1-4, 3-193Block Diagram 3-193Controls and Indicators 3-195groups 3-6power consumption 2-40ranges 3-6Specifications 3-194Wiring 3-196

QBE 1-4, 3-200Block Diagram 3-200Controls and Indicators 3-207groups 3-6power consumption 2-40ranges 3-6Specifications 3-205

QBI 1-4, 3-212Block Diagram 3-215Card Addressing 3-217Controls and Indicators 3-221groups 3-7Installation Data Sheet 3-222power consumption 2-40QID replacement 3-296ranges 3-7Specifications 3-215

QBI - QID equivalence 3-212QBO 1-4, 3-224

Block Diagram 3-224, 3-226, 3-228, 3-229,3-231, 3-232, 3-233, 3-234

Card Addressing 3-228CE MARK Wiring Diagram 3-234Controls and Indicators 3-231groups 3-7Installation Data Sheet 3-233

M0-0053 Index-4 5/99Westinghouse Proprietary Class 2C

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Index

power consumption 2-40ranges 3-7Specifications 3-227

QCA 1-4, 3-235Card Outline 3-248, 3-249, 3-250, 3-251, 3-

252, 3-253CE MARK Wiring Diagram 3-253Controls and Indicators 3-248groups 3-7Installation Data Sheets 3-251Operation 3-240power consumption 2-40ranges 3-7Signal Interface 3-238Specifications 3-236

Q-Card 3-1hardware address 2-29Hardware Address Selection 2-34

Q-card address, def. 2-4Q-Card Addresses

setting B-1Q-card Hardware Address A-2Q-Cards 1-3

list of available 1-4QCI 1-4, 3-254

Block Diagram 3-254Card Addressing 3-257CE MARK Wiring Diagram 3-264Controls and Indicators 3-262groups 3-7Installation Data Sheet 3-263power consumption 2-40ranges 3-7Specifications 3-256

Q-Crate card slots 2-35QDC 1-4, 3-265

groups 3-7power consumption 2-40ranges 3-7

QDI 1-4Block Diagram 3-267Card Addressing 3-269Controls and Indicators 3-274groups 3-8, 3-267Installation Data Sheet 3-275power consumption 2-40QID replacement 3-296ranges 3-8

Specifications 3-268QDI - QID, equivalence 3-266QDT 1-4, 3-276

Block Diagram 3-276Controls and Indicators 3-279groups 3-8power consumption 2-41ranges 3-8Specifications 3-277

QFR 1-4, 3-282groups 3-8ranges 3-8

QIC 1-4, 3-283Block Diagram 3-283, 3-289, 3-290, 3-293,

3-294Controls and Indicators 3-290groups 3-8power consumption 2-41ranges 3-8Signal Interface 3-292Specifications 3-289

QID 1-4, 3-212, 3-266Block Diagram 3-296Card Addressing 3-305CE MARK Wiring Diagram 3-314Controls and Indicators 3-306groups 3-9Installation Data Sheet 3-310power consumption 2-41Q-Line Digital Input 3-296ranges 3-9Specifications 3-300Wiring 3-307

QID - QBI equivalence 3-212QID - QDI, equivalence 3-266QLC 1-4, 3-317, 3-552

groups 3-9power consumption 2-41ranges 3-9

QLI 1-4, 3-318, 3-343, 3-351Block Diagram 3-318Card Addressing 3-323CE MARK Wiring Diagram 3-330Circuit Description 3-322Controls and Indicators 3-324groups 3-9Installation Data Sheet 3-327Interface Specifications 3-322

5/99 Index-5 M0-0053Westinghouse Proprietary Class 2C

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Index

power consumption 2-41ranges 3-9Specifications 3-321

Q-Line Bus Extender 3-200Q-Line DIOB Monitor 3-283Q-Line Loop Interface Card 3-318, 3-332Q-Line RTD Input Amplifier

RTD card 3-421Q-line Serial Link Controller 3-317QLJ 1-4, 3-332

Block Diagram 3-332Card Addressing 3-337Circuit Description 3-336Controls and Indicators 3-338groups 3-10Installation Data Sheet 3-340power consumption 2-41ranges 3-10Specifications 3-335

QMT 1-4, 3-359Block Diagram 3-359, 3-361groups 3-10ranges 3-10Signal Requirements 3-363

QPA 1-4, 3-365Addressing 3-377Applications 3-386Average Inverse Speed Measurement 3-390Block Diagram 3-365CE MARK Wiring Diagram 3-395Definitions 3-366Elapsed Time Measurement 3-388External Inputs’ Digital Filter Clock 3-376groups 3-10Implementation Example 3-390Installation Data Sheet 3-393Internal Timebase Clocks 3-376power consumption 2-41ranges 3-10Specifications 3-373Speed Measurement 3-387Speed Ratio Measurement 3-389

QRC 1-4, 3-398power consumption 2-41

QRF 1-4, 3-399Block Diagram 3-400Card Addressing 3-405CE MARK Wiring Diagram 3-409

Controls and Indicators 3-407groups 3-11Installation Data Sheet 3-408power consumption 2-41ranges 3-11Specifications 3-402

QRO 1-4, 3-410Block Diagram 3-410Card Addressing 3-415Controls and Indicators 3-416groups 3-11Installation 3-417Installation Data Sheet 3-419power consumption 2-41ranges 3-11Specifications 3-412

QRS 1-4, 3-420groups 3-11power consumption 2-41ranges 3-11

QRT 1-4, 2-19, 3-421Application Information 3-435Block Diagram 3-421Card Addressing 3-434CE MARK Wiring Diagram 3-451Controls and Indicators 3-435Definition of Terms 3-422Field Input Connection 3-432groups 3-11Installation Data Sheet 3-447power consumption 2-41ranges 3-11Specifications 3-429

QSC 1-4, 3-453Block Diagram 3-453Controls/Indicators 3-457groups 3-11power consumption 2-41ranges 3-11Specifications 3-455Wiring 3-457

QSD 1-4, 3-458Card Addressing 3-471CE MARK Wiring Diagram 3-481Controls and Indicators 3-471groups 3-11Installation Data Sheet 3-481Operator Interface 3-468

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Index

-

power consumption 2-41ranges 3-11Specifications 3-460

QSE 1-4, 3-483Application Information 3-505Card Addressing 3-503CE MARK Wiring Diagram 3-511chattering 3-490Circuit Description 3-492Controls and Indicators 3-503Firmware Considerations 3-500groups 3-11Installation Data Sheet 3-510power consumption 2-41ranges 3-11Signal Interface 3-490Specifications 3-486

QSR 1-4, 3-512CE MARK Wiring Diagram 3-537Controls and Indicators 3-526groups 3-11Installation Data Sheet 3-535Operation 3-522power consumption 2-41ranges 3-11Signal Interface 3-518Specifications 3-513Test Points 3-534Valve Calibration 3-528

QSS 1-4, 3-541Block Diagram 3-541CE MARK Wiring Diagram 3-551Controls and Indicators 3-546groups 3-12Installation Data Sheet 3-548power consumption 2-41ranges 3-12replacing QSC 3-453Specifications 3-544

QST 1-4, 3-552groups 3-12power consumption 2-41ranges 3-12

QTB 1-4, 3-553Block Diagram 3-553Control and Indicators 3-559groups 3-12power consumption 2-41

ranges 3-12Specifications 3-554

QTO 1-4, 3-562Block Diagram 3-562Card Addressing 3-568Controls and Indicators 3-568groups 3-12Installation Data Sheet 3-572power consumption 2-41ranges 3-12Specifications 3-566

QVP 1-4CE MARK Wiring Diagram 3-582, 3-583, 3-

584power consumption 2-41

RRaise output 3-344, 3-352Raise setpoint 3-344, 3-352Redundant Station Interface card 3-420reference junction compensation 3-193relay coils 3-224relay output card 3-410relay switching 3-410Remote I/O Fiber-Optic Interface 3-282Remote Q-Line Controller card 3-398reset 3-493resistors 3-95restricted block address 2-29row 2-23RTD 3-399, 3-423

copper 3-423Input Amplifier card 3-421nickel 3-423signal field connection 2-19use of 3-443

Ssafe operation 3-414Scan and Hold 3-50scan rate 3-50sequence of events 3-483serial link controller 3-317servo driver card 3-235, 3-458Servo Driver with Positional Readback card 3

512setpoint zero 3-98shielding 2-13

5/99 Index-7 M0-0053Westinghouse Proprietary Class 2C

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Index

low-level signal 2-15sign bit 3-160signal termination 2-1signal wire coupling 2-11Simulator mode 3-278single-speed DPU 2-35site preparation and planning 2-37slidewire power supply 3-36SLIM 1-4, 3-319

Block Diagram 3-352CE MARK Certified System 3-358Components 3-356Features 3-352groups 3-10power consumption 2-41ranges 3-10Small Loop Interface Module 3-351Specifications 3-356

slot assignmentworksheet A-1

smart transmitter interface 3-552smart transmitter interface card 3-552solid-state AC switching 3-562sort-by-hardware 2-3sort-by-point 2-3speed channel card 3-453speed measurement 3-365speed ratio measurement 3-365speed sensor card 3-541SSR 3-570SST 3-552standard card-edge termination hardware C-3stepping motors 3-224STI 3-552Surge Protection 2-14switching transients 2-9

Ttachometer 3-365tachometer signal pulse 3-453, 3-541Temperatures 2-39terminal block temperature sensing 3-193terminal strip connection points, def. 2-5termination

cabinet 2-22, 2-38card-edge 2-22point 2-38

thermocouple 3-66, 3-120, 3-193

coefficient 3-181considerations 2-18grounding 2-20

thresholding 2-8tie point C-4time base card 3-553Time Interval (Ti) 3-490timing signal 3-553transient noise 2-9TRIAC Output card 3-562tuning constant 3-345turning constant 3-353twisted pairs 2-13

VValve Actuator 3-465Vibration 2-39voltage to pressure, E/P 3-74

WW2500 I/O subsystem 3-283watchdog timer 3-15, 3-19, 3-75, 3-465, 3-

493, 3-546WDPF field wiring 2-1WDPF Installation 1-1, 1-2WEMAC 3-14worksheets A-1

Zzone 2-23

M0-0053 Index-8 5/99Westinghouse Proprietary Class 2C