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Optical Modulator Driver with Internal Attenuator and Power Detector
Data Sheet HMC7810A
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES 32.0 Gbps maximum data rate 13 ps typical output rise time and fall time 28 GHz bandwidth Self biased, no power sequencing required Adjustable gain Integrated output peak detector Low power consumption
0.5 W with 3.3 V positive/negative external supply voltage 0.44 W with 2.5 V positive/negative external supply voltage
Use with compact bias tee: 1 inch × 0402 + 1 inch × 0603, SMT only
16-terminal, 2.9 mm × 2.9 mm, leadless chip carrier (LCC) package
Differential balanced outputs
APPLICATIONS Communication infrastructure: 400 G 16 QAM, 100 G
DP-QPSK pluggable optical modules in CFP/CFP2 Broadband gain stage and pre-amplifiers Broadband test and measurement equipment
FUNCTIONAL BLOCK DIAGRAM
GNDATTENUATOR
CONTROL(VCTL)
AMPLITUDECONTROL
(VC)
PEAK DETECTOR(VDET, VREF)
OUTP
OUTN
BIAS TEE
BIAS TEE
VDD_EXTN
VDD_EXTP
VDD
INP
INN
HMC7810A
1622
9-00
1
Figure 1.
GENERAL DESCRIPTION The HMC7810A is a differential input and differential output, broadband linear amplifier, capable of driving a differential indium phosphate (InP) Mach-Zehnder (MZ) modulator for data center interconnect fiber optics or silicon photonics, or driving a single-ended, electroabsorption modulated laser (EML) modulator for short reach or metro applications. The HMC7810A supports data rates up to 32.0 Gbps with a gain flatness of up to 20 GHz. The integrated peak detector at the
output enables system designers to maintain constant output by adjusting the gain of the amplifier via the VCTL pin through an external automatic gain control (AGC) circuit. The IC provides module designers with scalable supplies for optimizing power dissipation vs. required linearity. The IC is in a 2.9 mm × 2.9 mm leadless chip carrier (LCC) package and requires an external bias tee. The differential input and differential are externally ac-coupled. No power supply sequencing is required.
HMC7810A Data Sheet
Rev. 0 | Page 2 of 14
TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4 Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ..............................................7 Frequency Domain Properties ....................................................8
Theory of Operation ...................................................................... 10 Applications Information .............................................................. 11
Reflow Solder Profile ................................................................. 11 Evaluation Board ............................................................................ 12
Evaluation Board Schematic ..................................................... 12 Evaluation PCB Outline ............................................................ 13
Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 14
REVISION HISTORY 2/2018—Revision 0: Initial Version
Data Sheet HMC7810A
Rev. 0 | Page 3 of 14
SPECIFICATIONS All specifications with positive supply voltage (VDD) = 3.3 V, positive and negative external supply voltage (VDD_EXTP/VDD_EXTN) = 2.5 V or 3.3 V, TMIN to TMAX, typical values are specified at TA = 25°C at maximum data rate, unless otherwise stated.
Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments MAXIMUM DATA RATE 28.3 32.0 Gbps Nonreturn to zero (NRZ), pseudorandom binary
sequence (PRBS31) = 231 − 1 BANDWIDTH
High 28 GHz
Low Cutoff 1 MHz
VOLTAGE RANGE
Differential
Input 0.2 1.0 V With adjusted control voltage (VCTL); for differential input voltage levels higher than 550 mV p-p, adjust VCTL to keep the driver in linear operation
Output 4.4 V Measured with PRBS31 and differential input of 600 mV p-p and VCTL = −1.5 V
Single-Ended 2.2 V Measured with PRBS31 and differential input of 600 mV p-p and VCTL = −1.5 V
SMALL SIGNAL GAIN Differential to Differential 4 17 18 dB Adjustable through VCTL control voltage, 1 MHz to
28 GHz, maximum gain: VCTL = −1.5 V, minimum gain: VCTL = 0 V
Differential to Single-Ended 2 11 12 dB 1 MHz to 28 GHz
GAIN FLATNESS ±1 dB 1 MHz to 20 GHz, −1.5 V < VCTL < 0 V
RETURN LOSS
Input
Differential 15 dB 100 MHz to 20 GHz, VCTL = −1.15 V
10 dB VCTL = −1.5 V
Single-Ended 15 dB 100 MHz to 10 GHz, VCTL = −1.15 V
10 dB VCTL = −1.5 V
Single-Ended Output 15 dB 100 MHz to 10 GHz 10 dB 10 GHz to 30 GHz
SIGNAL-TO-NOISE RATIO (SNR) 22 dB Input voltage (VIN) = 560 mV p-p, VCTL = −1.5 V
TOTAL POWER CONSUMPTION VDD = 3.3 V
0.44 W VDD_EXTP, VDD_EXTN = 2.5 V
0.5 W VDD_EXTP, VDD_EXTN = 3.3 V
TOTAL HARMONIC DISTORTION (THD) At 1 GHz
2 % At 3 V p-p
3 % At 4 V p-p
VC PIN VOLTAGE VVC 0 0.5 1.5 V
VCTL PIN VOLTAGE VVCTL −1.5 0 V
CONTROL SOURCE CURRENT
IVC 2 mA
IVCTL 1 mA
COMMON-MODE REJECTION RATIO 25 dB
SUPPLY VOLTAGE TOLERANCE
−8 +5 % VDD = 3.3 V
−8 +5 % VDD_EXTP/VDD_EXTN = 3.3 V
−5 +5 % VDD_EXTP/VDD_EXTN = 2.5 V
HMC7810A Data Sheet
Rev. 0 | Page 4 of 14
Parameter Symbol Min Typ Max Unit Test Conditions/Comments RESISTANCE
Input
Differential 100 Ω
Single-Ended 50 Ω
Output
Differential 100 Ω
Single-Ended 50 Ω
TIMING SPECIFICATIONS
Table 2. Parameter Min Typ Max Unit Test Conditions/Comments GROUP DELAY VARIATION ±7.5 ps 1 GHz to 30 GHz
OUTPUT
Rise Time 13 ps 20% to ~ 80%
Fall Time 13 ps 20% to ~ 80%
Jitter VCTL = −1.5 V
Additive RMS 350 fs VDD_EXTP, VDD_EXTN = 2.5 V 400 fs VDD_EXTP, VDD_EXTN = 3.3 V Deterministic 3 ps VDD_EXTP, VDD_EXTN = 3.3 V and 2.5 V
Data Sheet HMC7810A
Rev. 0 | Page 5 of 14
ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating Positive VDD Supply to GND 12 V INN and INP to GND 2 V OUTP to GND 12 V VC to GND 2.5 V VCTL to GND −2.5 V to +0.5 V Electrostatic Discharge (ESD) Protection
Human Body Model (HBM) Class 1A, 250 VRF, 500 VDC
Charged Device Mode (CDM) 1500 V Maximum Reflow Temperature
Moisture Sensitivity Level 3 (MSL3) 260°C Operating Temperature Range −40°C to +130°C Maximum Junction Temperature (TJ) 175°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 300°C
Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required.
Table 4. Thermal Resistance Package Type1 θJA
2 θJC3 Unit
E-16-1 53 51 °C/W 1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with nine thermal vias. 2 θJA is the natural convection, junction to ambient thermal resistance
measured in a one cubic foot sealed enclosure. 3 θJC is the junction to case thermal resistance.
ESD CAUTION
HMC7810A Data Sheet
Rev. 0 | Page 6 of 14
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
2INN
3INP
4GND
1GND
9 GND
10 OUTP
11 OUTN
12 GND
13
VREF
14
NIC
15
VDET
16
VDD
5
NIC
6
VCTL
7
NIC
8
VC
HMC7810ATOP VIEW
(Not to Scale)
NOTES1. NIC = NOT INTERNALLY CONNECTED. THIS PIN
IS NOT CONNECTED INTERNALLY.2. EXPOSED PAD. THE LCC PACKAGE HAS AN
EXPOSED PAD THAT MUST BE CONNECTED TOSUPPLY GND. 16
229-
002
Figure 2. Pin Configuration
Table 5. Pin Function and Descriptions Pin No. Mnemonic Description 1, 4, 9, 12 GND Supply GND. 2 INN Data Negative Differential Input. 3 INP Data Positive Differential Input. 5, 7, 14 NIC Not Internally Connected. This pin is not connected internally. 6 VCTL Analog Attenuator Control Voltage. 8 VC Amplitude Control Voltage. 10 OUTP Positive Differential Output. 11 OUTN Negative Differential Output. 13 VREF Reference Voltage for Detector. 15 VDET Detector Voltage Output. 16 VDD Supply Voltage. EPAD Exposed Pad. The LCC package has an exposed pad that must be connected to supply GND.
Data Sheet HMC7810A
Rev. 0 | Page 7 of 14
TYPICAL PERFORMANCE CHARACTERISTICS Time domain properties, typical 32 Gbps NRZ output eye diagram, measured with PRBS31 pattern and 600 mV p-p differential input.
BIT RATE31.780GBPS
DCD(%)2%
EYE AMPL2.317V
SNR15.52
EYE HEIGHT (AMPL)1.869V
FALL TIME13.130ps
RISE TIME13.200ps
CROSSING %51.2%
JITTER (p-p)4.6545ps
JITTER (rms)767.5fs
1 OPEN950mV
1 OPEN950mV
0 OPEN–920mV
0 OPEN–920mV
1622
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Figure 3. Single-Ended Output, 2.3 V p-p Swing
BIT RATE32.060GBPS
DCD(%)0%
EYE AMPL4.536V
SNR16.59
EYE HEIGHT (AMPL)3.716V
FALL TIME13.545ps
RISE TIME13.685ps
CROSSING %49.6%
JITTER (p-p)5.4185ps
JITTER (rms)905.5fs
1 LEVEL2.26V
1 LEVEL2.26V
0 LEVEL–2.28V
0 LEVEL–2.28V
1622
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4
Figure 4. Differential Output, 4.5 V p-p Swing
CURRENT MINIMUM TOTAL MEASMAXIMUMJITTER RMS 969fs 933fs 29980fsRISE TIME 14.22ps 13.56ps 2914.22psEYE SNR 7.25 7.24 297.30EYE AMP 1.95V 1.94V 291.95V 1622
9-00
5
Figure 5. Differential Output, VCTL = 0 V
CURRENT MINIMUM TOTAL MEASMAXIMUMJITTER RMS 686fs 674fs 28699fsRISE TIME 13.11ps 13.11ps 2813.33psEYE SNR 8.28 8.28 288.37EYE AMP 3.19V 3.19V 283.19V 16
229-
006
Figure 6. Differential Output, VCTL = −1 V
CURRENT MINIMUM TOTAL MEASMAXIMUMJITTER RMS 1.058ps 1.045ps 291.089psRISE TIME 14.44ps 14.44ps 2912.67psEYE SNR 15.46 15.33 2915.46EYE AMP 4.76V 4.75V 294.76V 16
229-
007
Figure 7. Differential Output, VCTL = −1.5 V
HMC7810A Data Sheet
Rev. 0 | Page 8 of 14
FREQUENCY DOMAIN PROPERTIES 16
14
12
10
8
6
4
2
0
–20.01 4.79 9.57 14.35 19.13 23.91 28.69
DIF
FER
ENTI
AL
TO S
ING
LE-E
ND
ED G
AIN
(dB
)
FREQUENCY (GHz)
VCTL = 0.8VVCTL = 0.9VVCTL = 1.0VVCTL = 1.1V
VCTL = 1.2VVCTL = 1.3VVCTL = 1.4VVCTL = 1.5V
VCTL = 0VVCTL = 0.1VVCTL = 0.2VVCTL = 0.3V
VCTL = 0.4VVCTL = 0.5VVCTL = 0.6VVCTL = 0.7V
1622
9-00
8
Figure 8. Differential to Single-Ended Gain (S21) vs. Frequency with Respect to the VCTL Pin, Measurement Taken with EV1HMC7810ALC3 Evaluation
Board (Fixture Not De-Embedded)
0
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0.01 4.79 9.57 14.35 19.13 23.91 28.69
DIF
FER
ENTI
AL
TO D
IFFE
REN
TIA
L G
AIN
(dB
)
FREQUENCY (GHz)
VCTL = –1VVCTL = –1.1VVCTL = –1.2V
VCTL = –1.3VVCTL = –1.4VVCTL = –1.5V
1622
9-00
9
Figure 9. Differential to Differential Gain (S11) vs. Frequency with Respect to
the VCTL Pin, Measurement Taken with EV1HMC7810ALC3 Evaluation Board (Fixture De-Embedded)
0
–70–65–60–55–50–45–40–35–30–25–20–15–10–5
0.01 4.79 9.57 14.35 19.13 23.91 28.69
DIF
FER
ENTI
AL
TO D
IFFE
REN
TIA
L G
AIN
(dB
)
FREQUENCY (GHz)
+130°C, S11 (dB)+130°C, S22 (dB)+25°C, S11 (dB)
+25°C, S22 (dB)–40°C, S11 (dB)–40°C, S22 (dB)
1622
9-01
0
Figure 10. Differential to Differential Gain (S11, S22) vs. Frequency,
VCTL Pin = −1.5 V, Zoomed for Gain Flatness (Fixture De-Embedded)
5.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
200 300 400 500 600 700 800
DIF
FER
ENTI
AL
OU
TPU
T (V
p-p
)
DIFFERENTIAL INPUT (mV p-p)
+130°C+25°C–40°C
1622
9-01
1
Figure 11. Differential Output vs. Differential Input, Measured at 1 GHz
Sine Wave
0.12
0
0.02
0.04
0.06
0.08
0.10
–1.5 –1.3 –1.1 –0.9 –0.7 –0.5 –0.3 –0.1
V PEA
K (V
) = V
DET
– V
REF
ANALOG ATTENUATION (V) 1622
9-01
2
Figure 12. Peak Voltage (VPEAK) = Detector Output Voltage (VDET) – Reference
Voltage (VREF) vs. Analog Attenuation
300
50
100
150
200
250
2.3 2.6 2.9 3.2 3.5 3.8 4.44.1 4.7 5.0
V PEA
K (V
) = V
DET
– V
REF
DIFFERENTIAL OUTPUT (V) 1622
9-01
3
Figure 13. VPEAK = VDET – VREF vs. Differential Output
Data Sheet HMC7810A
Rev. 0 | Page 9 of 14
9
0
1
2
3
4
5
6
7
8
200 300 400 500 600 700 800
TOTA
L H
AR
MO
NIC
DIS
TOR
TIO
N (%
)
DIFFERENTIAL INPUT (mV p-p)
+130°C+25°C–40°C
1622
9-01
4
Figure 14. Total Harmonic Distortion (THD) vs. Differential Input
8.0
0
7.07.5
6.06.5
5.05.5
4.04.5
3.03.5
2.02.5
1.01.5
0.5
–1.5 –1.4 –1.3 –1.2 –1.1 –0.9–1.0 –0.8 –0.7
TOTA
L H
AR
MO
NIC
DIS
TOR
TIO
N (%
)
VCTL (V)
800mV p-p600mV p-p400mV p-p200mV p-p
1622
9-01
5
Figure 15. Total Harmonic Distortion vs. VCTL, Voltage Measured at Various
Differential Input Voltages
5.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
–1.5 –1.3 –1.1 –0.9 –0.7 –0.5 –0.3 –0.1
DIF
FER
ENTI
AL
OU
TPU
T (V
p-p
)
VCTL (V)
900mV p-p700mV p-p500mV p-p300mV p-p
1622
9-01
6
Figure 16. Differential Output vs. VCTL, Voltage Measured at Various
Differential Input Voltages, 32 Gbps PRBS31 Data at the Input
HMC7810A Data Sheet
Rev. 0 | Page 10 of 14
THEORY OF OPERATION The HMC7810A is a broadband linear amplifier with a differential input and output. The device supports a maximum data rate of 32.0 Gbps with a typical bandwidth of 28 GHz. The HMC7810A is self biased and does not requires any bias sequencing or current adjustment circuitry. The device has two external supply voltages: VDD = 3.3 V supply at the supply pin and VDD_EXTP/VDD_EXTN. The VDD_EXTP/VDD_EXTN supply has two options: 2.5 V, which achieves better jitter performance, and 3.3 V, which achieves higher output voltage swings.
The HMC7810A includes an integrated analog that allows a gain adjustment of at least 6 dB. When VCTL is −1.5 V, the gain is maximum, and when VCTL is 0 V, the gain is minimum. The HMC7810A contains a peak detector that behaves linearly with respect to the output swing. The peak detector has two outputs, VDET and VREF. Use the difference of these voltages to read the output voltage swing. To implement an external automatic gain control, use an analog attenuator and the features of the peak detector.
Data Sheet HMC7810A
Rev. 0 | Page 11 of 14
APPLICATIONS INFORMATION The HMC7810A can drive Mach-Zehnder modulators in differential or single-ended operation. To keep the output swing constant at a desired value, build an analog or digital gain control loop. To build a gain control loop, use the voltage difference of the VREF and VDET pins (VPEAK) as an input to an analog or digital gain control mechanism to drive the VCTL pin (see Figure 17). The HMC7810A requires an external bias from the output side; however, the modulator bias can be provided after a dc blocking capacitance.
1622
9-02
7
VC
TL
OUTP
OUTN
INP
INN
VD
ET
VR
EF
ANALOG ORDIGITAL
GAIN CONTROL
VDD_EXTN
VDD_EXTP
MODULARNEGATIVE
BIAS
MODULARPOSITIVE
BIAS
MACH-ZEHNDERMODULATOR
Figure 17. Analog or Digital Gain Control Loop
REFLOW SOLDER PROFILE Figure 18 shows the typical, Pb-free reflow solder profile.
1622
9-02
6
TEM
PER
ATU
RE
(°C
)
217°C
RAMP UP3°C/SECOND MAX
RAMP DOWN6°C/SECOND MAX
TIME (Second)
60 TO 150SECONDS
60 TO 180SECONDS
20 TO 40SECONDS480 SECONDS MAX
260 – 5°C/260 + 0°C
150°C TO 200°C
Figure 18. Typical Pb-Free Reflow Solder Profile
HMC7810A Data Sheet
Rev. 0 | Page 12 of 14
EVALUATION BOARD EVALUATION BOARD SCHEMATIC Figure 19 shows the schematic for the EV1HMC7810ALC3 evaluation board. Table 6 lists the bill of materials.
2 INN
INN C4
C104.7µF
L410µH
R2475Ω
TP1VDD
C5
100nF
100nF1492-04A-5
1492-04A-5
INP
J1
J2
3 INP4
GND
1 GND
9GND
10
FB2470Ω
OUTP
11OUTN
12GND
13
VREF
14
NIC
15
VDET
16
VDD
5
NIC
6
VCTL
7
NIC
8
VC
1492-04A-5
OUTP J3
1492-04A-5
OUTN J4
C25
C26
C27
C28
J5
J6
J7
J8
C171nF
TP4VCTL
NIC
C71nF
TP5
C8
TP6VC
TP7VDD_EXTPC91nF C29
100pFC301nF
C311µF
C15100pF
C13
TP2VDET
C191nF
C18 C16
TP3VREF
C201nF
C21
L210µH
R1475Ω
FB1470Ω
TP8VBIAS_EML_P
TP10
GND
TP11
C38100pF
C391nF
C401µF
L810µH
R4475Ω
C22
100nF
C1
100nF
FB4470Ω
TP9VDD_EXTN
C32100pF
C331nF
C341µF
L610µH
R3475Ω
FB3470Ω
VBIAS_EML_N
C35100pF
C361nF
C371µF
1622
9-01
7
U1HMC7810ALC3
Figure 19. Evaluation Board Schematic
Table 6. Bill of Materials Qty. Reference Designator Description Manufacturer/Part Number 1 EV1HMC7810ALC3 Evaluation board Analog Devices, Inc./EV1HMC7810ALC3 4 C1, C4, C5, C22 100 nF, 16 V, tin, ultra broadband capacitor American Technical
Ceramics/ATC550L101KT16T 5 C7, C9, C17, C19, C20, C30,
C33, C36, C39 1 nF, 50 V, X7R, 0402, ceramic capacitor Murata/GRM15555C1H101J
9 C8, C13, C16, C18, C21, C25 to C28
Do not populate Not applicable
1 C10 4.7 μF, 25 V, 10%, X7R, 0603, gold terminal ceramic capacitors
Capax Technologies, Inc./0603X475K250GW
5 C15, C29, C32, C35, C38 100 pF, 50 V, 5%, C0G, 0402, ceramic capacitors Murata/GRM155R71H102KA01D 4 C31, C34, C37, C40 1 μF, 16 V, 10%, X5R, 0402, ceramic capacitors Taiyo Yuden/EMK105BJ105KV-F 4 FB1 to FB4 Ferrite chips, 470 Ω, 200 mA, 0402 Murata/BLM15GG471SN1D 4 J1 to J4 Connectors, K connector SRI Connector Gage Co./25-146-1000-92 3 J5 to J8 Do not populate 4 L2, L4, L6, L8 Inductors, 10 μH, 0603, 5%, 0.18 A Coilcraft/0603LS-103XJLB 4 R1 to R4 475 Ω, 1/10 W, 1%, 0402, resistors, SMD Panasonic/ERJ-2RKF470X
Data Sheet HMC7810A
Rev. 0 | Page 13 of 14
Qty. Reference Designator Description Manufacturer/Part Number 8 TP1 to TP4, TP6 to TP9 Test point, PC compact, 0.063 inch, red Keystone Electronics/5005 1 TP5 Do not populate 1 TP10 Test point, PC, compact, 0.063 inch, black Keystone Electronics/5006 1 U1 Optical modulator driver with internal attenuator and
power detector Analog Devices/HMC7810ALC3
EVALUATION PCB OUTLINE
1622
9-02
8
INN
INP
600-01085-00-2
VCTL VC V_EX_P
VDD V_EX_NVREFVDETGND
VB_E
THRU CAL
OUTP
OUTN
TP3
C20J1
J2
J3
TP8
TP7TP4
C31
C7 C9
C10
R1
R2
TP6
TP1
L2C40
C19
L4
TP2
FB1
FB2
C15
C17
TP10
J4
TP9
FB3
FB4 C37
C34
L6L8
R3
R4
C29C30
C32C33
C35C36
C38C39
C1C22
C4
C5
U1
SEE NOTE 44×
1 PCBNOTES1. SOLDER QUALITY TO IPC-A-610 CLASS 2.2. MANUALLY DISPENSE SOLDER (ITEM 5) FOR ALL COMPONENTS.3. J1 TO J4, ATTACH TO PCB WITH CENTER PIN ON TOP SIDE TRACE.
MANUALLY DISPENSE SOLDER (ITEM 5) TO CENTER PIN ANDGROUND LEADS, TOP AND BOTTOM. AFTER REFLOW, SOLDERMUST JOIN CONNECTOR AND PCB EDGE.
4. TRIM EDGE PLATING WITH ITEM 6 (106356). Figure 20. Evaluation Board PCB
HMC7810A Data Sheet
Rev. 0 | Page 14 of 14
OUTLINE DIMENSIONS
TOP VIEW
SIDE VIEW
02-2
4-20
17-C
PKG
-004
838
PIN 1INDICATOR
3.052.90 SQ2.75
EXPOSEDPAD
0.360.300.24
1.601.50 SQ1.40
1
0.50BSC
BOTTOM VIEW
16
58
9
12
13
4
0.08BSC
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
1.50REF
2.10 BSC
SEATINGPLANE
0.32BSC
PIN 1
0.900.800.70
Figure 21. 16-Terminal Leadless Ceramic Chip Package [LCC]
(E-16-1) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Lead Finish Package Option HMC7810ALC3 –40°C to +130°C 16-Terminal Leadless Ceramic Chip Carrier [LCC] Nickel/gold (NiAu) E-16-1 HMC7810ALC3TR –40°C to +130°C 16-Terminal Leadless Ceramic Chip Carrier [LCC] NiAu E-16-1 EV1HMC7810ALC3 Evaluation Board with Bias Tee and AC-Coupled
Input/Output Capacitors
1 The HMC7810ALC3 and the HMC7810ALC3TR models are RoHS Compliant Parts.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16229-0-2/18(0)
