Op_amp [Compatibility Mode]

Analog Signal Processing Using Operational Amplifiers (Op-amps)

Chew Chee Meng

Department of Mechanical EngineeringNational University of Singapore

2

Introduction

General purpose of amplifier: To deliver a larger signal to a load than is

available from the signal source Op Amp

a high gain differential voltage amplifier Used in 1950s to implement analog computers Capable of realising many mathematical operations in

electrical domain, e.g. scaling, integration, addition of voltage signals

Now commonly found in engineering instrumentationand analog signal processing, e.g. differential amplification, filters, etc.

3

Introduction

4

Introduction

Objectives: Understand properties of operational amplifier and

concepts of gain, input impedance, and output impedance

Understand difference between open-loop and closed-loop op-amp configurations

Analyse op-amp circuits using ideal op-amp analysis

Understand physical limitations of an op-amp Know how to design basic op amp circuits for

analog signal processing

5

Introduction

Op-amp consisting of transistors, resistors and capacitors fabricated on a

single IC (integrated circuit) chip. Two inputs and one output

Internal circuit of 741* Op Amp

Output

Non-inverting input

Inverting input

*a general purpose op amp

6

Introduction

Op-amp

Schematic representation

Non-inverting input

Inverting input

vo+-

+VS (supply)

-VS (supply)

output

7

Ideal Op-amp Characteristics

Characteristics Ideal Typical (eg 741)1. Open-loop gain, AOL 105

2. Input impedances 2M3. Output impedance 0 754. Bandwidth, BW Limited5. Obeys eqn (2-1) Yes Yes (within limits)6. Common mode rejection ratio (CMRR) 90dB

Non-inverting input

Inverting input

vo+-

+VS (supply)

-VS (supply)

output

( 2-1)Vo = AOL (V+-V-)

8

Equivalent Circuit Model for Ideal Op-amp

AOL Vid+V-

V+

Vo

( 2-1)

+Vid

Remark: Op-amp amplifies the difference between voltages at noninverting and inverting terminals.

Vid : differential input voltage (difference between the input voltages)AOL : open-loop gain

9

Inverting Amplifier

v1

vo+

R1

Rf

How to analyse such a circuit?

11

fo

Rv v

R

10

Negative Feedback

Open-loop (no feedback) vs closed-loop (with feedback) gains

Closed-loop: positive vs negative feedback Negative feedback results in stable behavior

+

negative feedback

11

Ideal Op-Amp Technique

Assumption 1: V+ = V-(Since output is typically finite with negative feedback and from Eq. (2-1) which has high open loop gain, A)

Assumption 2: No currents flowing into op-amp’s input terminals (Due to high input impedance)

If negative feedback is present

V+

V-

Non-inverting input

Inverting input

vo+

-

12

Ideal Op-Amp Technique

General procedure:1. Check negative feedback is present2. Apply Assumptions 1 & 23. Apply Kirchhoff’s current law at non-inverting terminal, V+

4. Apply Kirchhoff’s current law at inverting terminal,V-

5. Obtain expression for output

Limitations of ideal op-amp technique: If result calculated is either infinity or 0, more precise op-amp

model may be needed (E.g., using circuit model in Slide 8).

13

Inverting Amplifier

To obtain input/output relationship expression (transferfunction) for inverting amplifier circuit.

v1

vo

+

XR1

Rf

1

1

0o

f

v vv vR R

Negative Feedback present, can applyideal op-amp technique Apply Assumption 1, v-=v+=0 Apply KCL at V- (node X) =>

(*)

11

1

fo

C

Rv v

RA v

Hence

v-

v+

Remarks: •All voltages are referenced to the ground voltage.•In (*), we have applied Assumption 2, i.e. the currents flowing into the input terminals are zero.•Ac=Rf/R1 is the closed-loop gain

Circuit analysis:

14

Inverting Amplifier

Input impedance of inverting amplifier circuit

v1 vo+

XR1

Rfi1

1 11

1 1

v v viR R

Input impedance: 11

1 RivRIN

15

Inverting Amplifier

Remark: Typically, resistors used are in the range

between 500 and 1M. Lower bound – to ensure not putting too much load

on power supply (P = V2/R) (see pg 646, Hampbley,3rd ed, & Example 5.1 of Alciatore & Histand)

Upper bound (typically for feedback resistor) – toavoid problem due to bias current error (will discusslater)

16

Inverting Summing Amplifier

V1

Rf

R1

R2V2 X

-

+Vo

Vn

V-

Rn

01 2

1 2

0n

n f

V V V VV V V VR R R R

fn

nRVo

RV

RV

RV

2

2

1

1 )( 22

11

nfff

o VRnR

VRR

VRR

V

)( 21 nf

o VVVRR

V

)( 21 no VVVV

Applying KCL at node 'X‘ and using Assumption 2:

Negative feedback is present, can use ideal op-amp technique

From Assumption 1: V- = 0

or

If R1 = R2 = … = Rn= R, we have the summing amplifier:

If Rf =R, we have the summer:

17

Non-inverting amplifier

V1

Rf

R1 X-

+

Vo

of

VRR

RV

1

1

11

1o

f

RV VR R

11

1RR

VV fo

Considering Assumption 2 (ib =0) and by voltage divider equation:

Since V-=V1, =>

ib=0Negative feedback is present, can use ideal op-amp technique

From Assumption 1: V- = V+ = V1

Remark: Gain is positive => Non-inverting

V-

Rf

R1 X

Vo

18

Non-inverting amplifier (cont.)

• Input impedance of non-inverting amplifier:

(Since i ≈ 0)

iV1

Rf

R1-

+

Vo

i

VRIN1

19


Impedance buffer

iV+

RTH = 500K

V VL i

50

50 500 0000

,

iRL= 50 VL

+-

By voltage divider:

How to achieve VL = Vi?

20


Voltage follower/buffer amplifier (a special case of non-invertingamplifier)

V1

-

+

VoVV

ie V V

0

1

0 1

1 0 1

.

Remarks: •High input resistance•Low output resistance •Power gain•Useful as a buffer to interface circuits

Here, Rf = 0 and R1= ∞Hence,

21


Use of a Voltage Follower for impedance buffer problem

Since RIN (input impedance of the amplifier) is very large,

For the voltage follower (assume output current is within the limit),

RTH = 500K

RL= 50VoV1

i 0 and hence,

i 0

Vi

-

+

Voltage follower

1L OV V V

1OV V

1 iV V

VL

Hence,

22

Differential Amplifier

Amplification of small transducer signals

V1+Vn

Vo

+

XR1

R2

V1

Transducer’s output

)( 11

2no VV

RRV

E.g.: Electrocardiogram (ECG) measurement

If inverting amplifier is used:

Leading wire susceptible to electromagnetic wave interference (results in noise signal added to original input signal)

23


Circuit analysis:

i

V2

i12

Vo

V1

R2R1

R3

R4

Ideal Op-Amp:

Assumption 1: V+ = V-Assumption 2: i1=i2=0

Negative feedback is present

Circuit to achieve differential voltage amplification

24


V2

Vo

V1

R2R1

R3

R4

V VR

V VR

1

1

0

2

0

V VR

VR

2

3 4

0 0

))((21

21

43

43

3

2

21

1RRRR

RRRR

RV

RV

RV o

KCL at node X

KCL at node Y

Therefore

25


V2

Vo

V1

R2R1

R3

R4))((21

21

43

43

3

2

21

1RRRR

RRRR

RV

RV

RV o

V RR

V V02

12 1 ( )

Now set R1=R3, and R2=R4, then

Differential amplification

26


Amplification of small transducer signals (cont)

))()(( 211

2nno VVVV

RRV

)( 211

2 VVRRVo i.e.

V1+VnV1

V2 V2+Vn

Twisted pair (noise will be

common to both wires)

Vo

R2R1

R3

R4

If differential amplifier is used:

27

Integrators

How would you design an integrator circuit to integratevoltage signals?

Vo

Vi

R

C

Integration

b

adxxf )(

28

Integrators

Circuit analysis:

V VR

C d V Vdt

i

( )0 0

V

R C

dVdt

i 0 0 dtVRC

V io1

Ideal Op-amp: Ib = 0

KCL at node X:

Vo

Vi

R

Ib

C

Negative feedback is present

0V V

29

Integrators

Application ExampleDesign a circuit for an electronic camera shutter application togenerate a voltage signal proportional to the total amount of lightthat has fallen on a detector during the time it is exposed to the light.When the voltage reaches a desired voltage, the shutter will beclosed.

Thevenin equivalent circuit can be derived for the detector: Open circuit voltage (Thevenin voltage), Vs = L (L is light density in

photons per second and =10-15 Vs/photon) Thevenin resistance, Rs = 106 .

Design a circuit that produces an output voltage of –1V after 1011

photons strike the detector.

Integrators

Example (cont)

30

VoVs

-

+

R1R

+

-

sC

t

ss

o dtVCRR

tV01)(

1)(

t

so Ldt

CRV

0)(

Choose appropriate values for the resistor and capacitor to satisfy design specification:

Let choose R1=0 so that

t>0Detector’s equivalent circuit

A switch to short capacitor so that output Vo is zero. Switch is opened just before start of integration operation

Integration is required for the application.

(*)

Integrators

Example (cont)

31

VoVs

-

+

R1R

+

-

sC

11

0

10t

Ldt

1110)(

1 CRs

pFC 10010

10106

1511

We want Vo= -1V when

Sub into (*),

Therefore,

What other application can you apply this integrator circuit?

Differentiator

Differentiation

32

Vo

Vi

R

C

dtdvi

How would you design a differentiator circuit to to obtainthe derivative of a voltage signal at current time t?

(t, vi )

Differentiator

Circuit analysis

33

KCL at node X:

VR

C dVdt

V RC dVdt

i

i

0

0

0

Negative feedback is presentIdeal Op-amp: ib = 0,

Vo

Vi

R

C

0V V

ib

34

Practical Op Amp circuit design considerations

Bandwidth limitations

Typical Op-Amp's open-loop gain vs frequency plot (frequency response curve)

frequency (Hz)

Definition: Decibel (dB):

Gain A in dB, A dB = 20 log10 A

Open loop

0

20

40

60

80

100

120

A dB

1 10 100 1k 10k 100k 1M 10M 100M

-20dB/decade

35


Bandwidth limitations (cont)

Bandwidth of a system:•The range of frequencies where gain of the system does notdrop by 3 dB (corresponds to 70.7% of DC gain value).

Open loop

frequency (Hz)

0

20

40

60

80

100

120

1

AdB

3dB

Bandwidth=100Hz

-3dB => 0.707

10 100 1k 10k 100k 1M 10M 100M

Break frequency

36



frequency (Hz)

Open loop

0

20

40

60

80

100

120

AdB

Approximation of frequency response curve

1 10 100 1k 10k 100k 1M 10M 100M

37



Gain-bandwidth product (GBP or GBW) of an op amp = DC gain x bandwidth

Remarks: GBP is constant for a particular op-amp (for both open loop and closed loop)=> Trade-off between gain and bandwidth

Closed-loop response

frequency (Hz)

Open loop

Closed-loop

0

20

40

60

80

100

120

AdB

1 10 100 1k 10k 100k 1M 10M 100M

38


Bandwidth limitations

Example: Determine the GBP for the op-amp whose open-loop gain vs frequency plot is given below:

A dB

Freq (Hz)

0

20

40

60

80

100

120

Solution:

GBP can be obtained by multiplying the frequency and the gain values at any point on the curve to the right of the break frequency.

Using 80 dB (A = 10,000) and 1kHzGBP = 10,000 X 1 kHz

= 10MHz.Using 0 dB (A = 1) and 10 MHz:

GBP = 1 X 10 MHz= 10 MHz.

break frequency

1 10 100 1k 10k 100k 1M 10M 100M

39


Voltage supply limits

Slope = A

v+ - v-

vo

vo = A (v+ - v-)

Ideally,

vo+

-

V+

V-

40


Voltage supply limits

-Vs

+Vs

Vs/A

-Vs/A

Slope = A

v+ - v-

vo

Saturation (due to negative supply rail)

Saturation (due to positive supply rail)

Linear region

Actual Vo is limited by the voltage supplies (Vs )

vo+

-

+VS(supply)

-VS

(supply)

V+

V-

41


Output Current Limits

Limits to the current that an op amp can supply to a load (mainly due to heat issue)

For 741 op amp, limits are 40 mA If current being drawn from output exceeds

these limits, output (voltage) waveform becomes clipped (deviate from theoretical value)

vo+

-

io

43


Input bias current error Small input bias currents (in the order of 100nA for

op amps with bipolar transistor input stages) arepresent at inverting and noninverting terminals

Bias currents cause a small shift to output voltage(input bias current error) in amplifier circuits (seefollowing example)

Ib+

Ib-

44


Input bias current error (cont)Consider the following circuit where both inputs are grounded and let Vo be the error in the output voltage due to the input bias currents:

+

-

RfRi

VoIb

45


Input bias current error (cont)

0

b

f

o

i

IR

VVRV

)0( VAVoA

VV o

Let ib denote the input bias current

Applying KCL at node X,

(1)

=>

Sub (2) into (1),

(2)

( ) ( )f i f io o ob

f f i f f i

R R R RV V VI VR R R R A R R

+

-

RfRi X

VoIb

By op-amp equation,

46



f

ob R

VI

V I Rb f0

As A ,

or,

Remark:• Input bias current error, Vo, is directly proportional to Rf. Hence, Rf

should not be too large (usually limited to 1 M or less). Recall, theresistors used in op amp circuits should be between 500 to 1 M

+

-

RfRi X

VoIb

47



Bias current balancing:

“Extra” resistor Rb added to reduce the input bias current error:

Vo

R2

R1

Rb

48

Practical Op Amp circuit design considerations Input bias current error (cont)

VR

V VR

Ix xb

1

0

2

0

VR

Iy

bb 0

VR

V VR

VR

x x y

b1

0

2

KCL at node X:

KCLat node Y:

From the above equations,

When V0=0, V A V Vy x0 ( )

bb IIAssume:

V Vy x=>

VR

VR

VR

x x x

b1 2

Hence the input bias current error can be eliminated by choosing Rb as above.

Vo

R2

Ib-R1

Rb

Ib+

R R Rb 1 2

1 1 1

R R Rb 1 2 / /

Hence, or

Let ib+ and ib- denote the input bias currents flowing into the noninverting and inverting terminals, respectively

49


Common-mode rejection ratio (CMRR)

cm

d

AA

CMRR

Common-mode input voltage

Ideally, output should be zero

Common-mode voltage gain:

Common-mode rejection ratio,differential-mode gain

common-mode gain

+-+

- Vicm

+Vocm

icm

ocmCM V

VA

• Measure ability of differential amplifier to “reject” common-mode inputs

50



dBAA

CMRRcm

d10log20

CMRR typically expressed in decibel:

• Desirable to have CMRR as high as possible - Typical values: 80 to 100 dB

51



Example: A differential amplifier circuit with R1=R3=10k, R2=R4=270k. Given V1 = 2.00 V and V2= 2.05 V, determine V0 for: (a) CMRR = , (b) CMRR = 80 dB, (c) CMRR = 40 dB.

2710/2701

2 RRAd

Gain of differential amplifier,

V2

Vo

V1

R2R1

R3

R4

52



Example (cont)

VV

d0 2 05 2 00 271 35

( . . ).

(a)For CMRR = , no amplification of common mode input.The output voltage is only given by amplification of differential input voltage,

V2

Vo

V1

R2R1

R3

R4

53



Example (cont)

A Acm

dCMRR

102 7 10

20

3

( )

.

V

V

icm

( . . )

.

2 00 2 052

2 025

V A VV

mV

cm cm icm032 7 10 2 025

5 47

. ..

V V VmV

V

d cm0 0 0

1 35 5 471 355

. .

.

(b) With finite CMRR, output is composed of differential-mode output Vod and common-mode output Vocm.

Total output of differential amplifier is

dBAA

CMRRcm

d10log20

whereCommon-mode output,

54



Example (cont)

(c) For CMRR=40 dB, the overall voltage is found to be V V0 1897 .

Remark:• Importance of CMRR in differential amplification application• A special class of differential amplifier used for transducer conditioning is the instrumentation amplifier. Such instrumentation amplifier has very high input impedance, low drift and high CMRR

55

Specification sheets of 741 Op Amp

56

Specification sheets of 741 Op Amp

57

58

Design of Op-amp circuit (for Analog Computing)

To design op-amp circuit given a desired input/output relationship Example: Obtain the voltage output

from two given voltage inputs V1 and V2, using op-amps.V V V0 1 22

R2=2R1

R

R1V1

Vo=2V1-V2

R

R

R

4

3

5

6

7

R

where R2=2R1, and R5=R6=R7

R3 and R4 are chosen for bias current balancing.

Note: In practice, the resistors used are usually between 500 to 1 M.

Solution:

-2V1

V2

59

Multiple-stage Op-Amp designs

Amplification requirements of many applications cannot be metusing single stage circuit.For example: Desired specifications: closed-loop gain = 200 and bandwidth =

100 kHz Given Op-amps with GBP=10MHz

A single op-amp will not meet the specifications as 200x100kHz = 20 MHz > GBP.

If closed-loop gain = 200, bandwidth = GBP/200 = 50kHz

Less than desired bandwidth

60


Need to reduce closed-loop gain to increase bandwidth

And to achieve overall gain requirement by cascading more than 1op-amp amplifier circuit, e.g.:

Gain 14.14

Gain 14.14 Gain = 200

BW = GBP/gain = 10 MHz / 14.14 = 707 kHz

BW = GBP/gain= 10 MHz / 14.14 = 707 kHz

Vi Vo VoVi

1/

1/ 2

2 1

707 2 1 455 100

noverall sBW BW

kHz kHz

n is the number of stages

BWs is the smallest BW along the path

61


Procedure in design process: Step 1: Determine maximum amount of gain per stage (=

GBP/required bandwidth) => number of required stages can beestimated

Step 2: Determine whether input connections should be made toinverting or non-inverting terminal of op-amp. As a rule of thumb, if required input impedance > 1M, first stage

should be a non-inverting amplifier which has large input impedance Step 3: Draw a block diagram of circuit (each block represents an

inverting, noninverting, or summing amplifier circuit) so that targetoutput(s) vs input(s) relationship can be achieved.

Step 4: Check that overall bandwidth is indeed satisfied (for allpaths). If not, add one more stage to the path and go to Step 3.

Step 5: Select values for resistors to achieve the desired gain ofeach block and add bias current balancing resistors

62


ExampleDesign an amplifier circuit that is composed of 741 op-amps in order toobtain a gain of 800 with an input impedance of at least 1 M . Theamplifier must respond to a signal with frequency up to 40 kHz. Given GBP= 1 MHz.

Solution:

Step 1: Determine the maximum amount of gain per stage.

Maximum gain per stage = GBP/ desired bandwidth =1 MHz / 40 kHz = 25

To achieve an overall gain of 800, need at least three stages of amplification (25 X 25 = 625 only).

Overall gain should be split among three stages, e.g. 8x10x10

63


Example (cont)

Step 2: To achieve high input impedance (>1M), first stage must be a non-inverting amplifier. Next 2 stages can be either inverting or non-inverting as long as overall output is achieved.

Let’s choose non-inverting amplifier circuit for all stages.

Step 3: Draw a block diagram of the circuit (each block represents an inverting, noninverting, or summing amplifier circuits) so that target output(s) vs input(s) relationship can be achieved.

8 10 10vi 8vi 80vi 800vi

64


Example (cont)

Step 4: Check that the overall bandwidth is indeed satisfied

Since GBP = constant, smallest bandwidth, BWs, corresponds to highest gain. Here, maximum gain = 10, hence,

kHzkHzBWBW nsoverall 40511210012 3/1/1

Satisfy design requirement!

kHzMHzBWs 10010

1

65


Example (cont)

Step 5: Select the values for the resistors to achieve the desired gain of each blockand add bias current balancing resistors (all resistors should have values between500 to 1 M )

A possible set of resistor values for non-inverting amplifier with gain = 10 is (R1= 90 k, R2= 10 k). Corresponding bias current balancing resistor, Ra = 90 k// 10k = 9k

For amplifier with gain = 8, R1= 70 k, R2= 10 k; bias current balancing resistor, Rb = 70k // 10k = 8.75kHence, the overall circuit is as follows:

Ra=9 kRa=9 k

90 k90 k

70 k

10 k10 k

10 k

Rb=8.75 k

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Op_amp [Compatibility Mode]