Ob-Chip Networks and Testing1 On-Chip Networks and Testing-II

Ob-Chip Networks and Testing 1

On-Chip Networks and Testing-II


Aethereal NoC as Communication Fabric for

SoC

1. Goosens et al., “Aetherial Network on Chip ...,” IEEE D&T Magazine, Sept-Oct 2005, 414-421.

2. Vermeulen et al., “Bringing Communication Networks on a Chip: Test and VerificationImplications,” IEEE Communications Magazine, Sept. 2003, 74-81.


Rationale for AetherealAs SoC complexity grows, its communication infrastructure is a major concern.Expert opinion says NoCs are increasingly likely to be the choice for on-chip communication because they provide structure, modularity, and performance advantages over alternative designsAethereal NoC is a research product from Philips to explore NoC-based SoC designs.Vermeulen et al. [2] consider an Aethereal-based SoC design for multimedia applications and discuss how it can be tested and verified.


Example SoC with Aethereal NoC

The picture shows routers, network interfaces, processor, memory, and memory-interface cores, and neighbor-links.


Combined Guaranteed- Throughput (GT) and Best-Effort (BE) Router

Conceptual View Hardware View


Aethereal Chip: Contention-Free Routing

Contention-free routing: network of three routers (R1, R2, and R3)at slot s 2, with corresponding slot tables (T1, T2, and T3).


Default Core-Based Testing

The default method assumes the cores are wrapped, according to IEEE1500 and uses dedicated TAMs to transport test data.The example shows cores tested simultaneously by 4 TAMs.Disadvantage: Wire congestion due to TAMs.


NoC Reuse Based TestingNoC blocks (routers and network interfaces) are tested first (top).If ok then NoC can be used to help test other cores (bottom).Further, because routers are identical, their test data sets can be broadcast and applied concurrently and their responses can be compared to each other for mismatches (for go/no-go testing)


Reuse-Based Test Scheduling

1. C. Aktouf, “A Complete Strategy for Testing an On-ChipMultiprocessor Architecture,” IEEE D&T, Jan-Feb 2002, 18-28.

2. C. Liu et al., “Reuse-Based Test Access and Integrated Test Scheduling for NoC,” DATE’06, 303-308


Complete Strategy Summary [1]

Homogeneous fine-grain, massively parallel, message-passing, multiprocessor in 2D topologyTesting in three phases:

1. Router Testing (by groups of cells)2. RAM Block Testing (using BIST)3. Distributed Processor Testing (using

PMC model)


Multiprocessor Architecture

Interconnection network on top – shading shows two cells communicating using shared buffers.Cell Structure at the bottom. Each cell consists of Processor, Memory, and RouterMessages include relative x and y displacements, address, and data.


Boundary-Scan Based Testing of Routers in Groups of Cells (GCs)

Basic-cell groups (top) and test-circuit configuration for external test (right)


Reuse-Based Test Access and Test Scheduling [2]

Summary2D mesh architecture similar to [1].Each cell consists of a core and router.Progressive reuse of network resources for transporting test dataRouters and cores tested concurrently


System ArchitectureThe top picture shows a 12-node system in which a particular SoC (ITC02 benchmark d695) has been mapped to 10 available nodes.Two shaded cores are being tested using dedicated paths from external inputs to the core an from the core to an external outputThe paper compares results to those in [1] that uses the GC approach (bottom) to testing routers first.

1x1 groups 2x2 groups


Progressive Scheduling for Router Testing

Constraint: Only pretested routers can be reused for test-data transport, hence need for schedulingTest responses are assumed to be processed on-chip or compressed and transported off-chip through dedicated pathsThe picture shows 2x2 I/O, numbers represent groups of cells that can be tested simultaneously, in increasing order of group numbers.Even though only 10 cells are occupied, for testing all 12 must be tested.Only the router-under-test is in test mode, others on the path are in normal mode.

Multicast network Unicast network


On-Chip Test Response Processing

Using MISRs Using Comparators


Integrated Test SchedulingConsider the unicast network scheduling example from before: Assume both bottom row routers have been tested in steps 1, 2, and 3. We can reuse Input 2 and Output 2 to test bottom-row cores; at the same time we can reuse Input1 and Output 1 to test routers in group 4.The paper gives an algorithm for scheduling such integrated testing


A Sample of Results

Col 2: Boundary-scan results from [1] assuming all routers are tested simultaneously - only router testing times are shownCol 3: router testing time when network is reused (Savings over Col 2)Col 4: Test bus results from TAM co-optimization by Iyengar et al. (DATE 2002) – discussed earlier.Col 5: Routers and cores test separatelyCol 6: Integrated testing (savings over Col 5)


Conclusion

Testing research on NoC-based SoC is still in infancy.Approaches are highly dependent on assumptions about the system and NoC architectures, hence hard to compare against each other.ITRS projections, however, show that NoC is likely to be the dominant communication mechanism of the future SoC, hence this is good field of research to get into.


Bibliography• Goosens et al., “Aetherial Network on Chip ...,” IEEE D&T

Magazine, Sept-Oct 2005, 414-421.• Vermeulen et al., “Bringing Communication Networks on a Chip:

Test and Verification Implications,” IEEE Communications Magazine, Sept. 2003, 74-81.

• C. Liu et al., “Reuse-Based Test Access and Integrated Test Scheduling for NoC,” DATE’06, 303-308.

• C. Aktouf, “A Complete Strategy for Testing an On-Chip Multiprocessor Architecture,” IEEE D&T, Jan-Feb 2002, 18-28.

• Nahvi and Ivanov, “A Packet Switching Communication-Based TAM for SoC,” ETW01, 81-86.

Documents

Ob-Chip Networks and Testing1 On-Chip Networks and Testing-II