Nmos and Cmos Fabrication

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  • *FABRICATION

  • *SCHEMATIC CROSS SECTION OF MOSFET

  • *Create N-well (for PMOS devices) & Channel Stop RegionsGrow Field & Gate OxideDeposit & Pattern Poly LayerImplant S, D & Substrate ContactsCreate Contact WindowsDeposit & Pattern Metal LayerImpurity Implant Into The Substrate.Thick Around The nMOS And pMOS Active Regions And Thin Respectively Through Thermal Oxidation.Creation Of n+ And p+ Regions.Metallization

  • *PHOTOLITHOGRAPHYIC Is Set Of Patterned Layers Of Doped Silicon, Polysilicon, Metal And SiO2.

    All Areas Are To Be Defined By Proper Masks.A Layer Must Be Patterned Before Another Is Applied On The Chip.Every Layer Will Undergo Lithography With Different Mask.

    Si SubstrateSiO2 layer by thermal oxidationUnpatterned StructureSi SubstrateSiO2SiO2Patterned StructurePhotolithography

  • *Si SubstrateSi Substrate5-200 nm SiO2 layer by thermal oxidationSi SubstrateLight Sensitive, Acid Resistant compound= PhotoresistSi SubstrateUV LightInsoluble PhotoresistSoluble PhotoresistvGlass MaskSi SubstrateHardened PhotoresistChemical or Dry EtchSi SubstrateHardened PhotoresistSiO2 Window reaching down to Si substrateSi SubstrateHardened photoresist removed by stripping solvents.Obtained Patterned SiO2 feature on the Si SubstrateFor High Density Patterns Required In Sub Micron Devices, E-beam Lithography Is Used Instead Of Optical Lithography.

  • *Fabrication of nMOS: Basic stepsSi SubstrateSi SubstrateThick Oxide layer(field oxide)Si SubstrateSi SubstrateThin high quality Oxide Layer(gate oxide)OXIDATIONSELECTIVE ETCHING FOR DEFINING ACTIVE AREA ON WHICH MOSFET WILL BE FABRICATEDSi SubstrateDeposition of polysilicon(gate + interconnect medium)Si SubstratePatterned and etchedpolysilicongate oxideoxide

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  • *Si SubstratePatterned and etchedpolysilicongate oxideoxideFabrication of nMOS: Basic stepsBare Si surface to form S & Dpolysilicongate oxideoxiden+n+n+n+Doping : Diffusion or ion implantation(high concentration of impurity atoms)Insulating oxiden+n+Patterned and etchedContact windows for D & S

  • *Fabrication of nMOS: Basic stepsn+n+n+n+Evaporated AluminumPatterned and etchedMetal contactsBy creating another insulating oxide layer, cutting contact holes (via), depositing and patterning metal, two more layers of metallic interconnects can also be added on the top of this structure.

  • *Electrical isolation on a single chip containing many devices is necessaryTo prevent undesired conducting paths;To avoid creation of inversion layers outside the channels;To reduce leakage currents.

    CHALLENGES:

  • *ETCHED FIELD OXIDE ISOLATION: Devices are created in dedicated regions called active areas. Each active area is surrounded by thick oxide barrier called field oxide. Thick oxide is grown on complete surface of the chip and then selectively etched to define active areas.

    Straight forward method. Thickness of oxide leads to large oxide steps at the boundaries of active areas and isolation regions. May lead to chip failure due to cracking of deposited layers due to large height difference at the boundaries.

    DEVICE ISOLATION TECHNIQUES:

  • *DEVICE ISOLATION TECHNIQUES: II Local oxidation of silicon

  • *LOCOS technique is based on the principle of selectively growing the field oxide in certain regions , instead of selectively etching away active areas after oxide growth.For selective growth of oxide, active areas are covered with Silicon nitride.

  • *DEVICE ISOLATION TECHNIQUES:LOCOSSi SubstrateSi3N4Thin PAD OXIDE(stress relief oxide)Protects Si surface from stress caused by nitride during subsequent process steps.(Patterned and etched)(Doping of exposed Si surface with p type impurity)Si Substratep+p+p+Si3N4Si3N4Isolation Regions(Channel stop implants)Si Substrate

  • *Si Substratep+p+p+Lateral extension under nitride layerSi3N4Si3N4 Thick Field Oxide which partially recesses into Si substrateBirds beak** Reduces active areaSi Substratep+p+p+THE ACTIVE AREAS(Patterned and etched)LOCOS is popular :More planar surface topologyBirds beak encroachment can be reduced up to some limit by device scaling

  • *III) MULTILEVEL INTERCONNECTS & METALLIZATION:

    4 to 8 metal layers are used to create interconnections between the transistors and for routing the power supply, signal lines and clock lines on the chip surface.Allows higher integration densities. Adds to the third dimension.Electrical connections between the layers are made by vias.Each via is formed by creating an opening in isolation oxide before every metallization step and filling it with a special metal plug (Tungsten).After creation of via, new metal layer is deposited and subsequent patterning is done.

    DEVICE ISOLATION TECHNIQUES:

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  • *SOME FACTS:Due to various process steps chip surface is highly nonplanar.It may inhibit local thinning and discontinuities at uneven surface edges.Deposition of multiple metal interconnect lines is not desirable on such irregular topography.They will lead to hills and valleys on the chip surface.Hence surface is usually planarised before every new metal deposition step.For this, a fairly thick SiO2 layer is grown on the wafer surface to cover all existing surface nonuniformities.Its surface is then planarised by any one of:Glass reflow (heat treatment),Etch back,Chemical mechanical polishing (CMP).CMP: Actual polishing of wafer surface using abrasive silica slurry.Adopted in recent years.

  • *EXERCISE: *Epitaxial layer** Difference between ion implantation and diffusion processes of doping.*** Design masks for all patterning and etching steps in the fabrication of nMOS transistor for positive and negative photoresist material.